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| User's Manual V850ES/KJ1 32-Bit Single-Chip Microcontrollers Hardware PD703216 PD703216(A) PD703216(A1) PD703216(A2) PD703216Y PD703216Y(A) PD703216Y(A1) PD703216Y(A2) PD703217 PD703217(A) PD703217(A1) PD703217(A2) PD703217Y PD703217Y(A) PD703217Y(A1) PD703217Y(A2) PD70F3217 PD70F3217(A) PD70F3217Y PD70F3217Y(A) PD70F3217H PD70F3217HY PD70F3218H PD70F3218HY Document No. U16889EJ1V0UD00 (1st edition) Date Published March 2004 N CP(K) 2004 Printed in Japan [MEMO] 2 User's Manual U16889EJ1V0UD NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. Purchase of NEC Electronics I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. Caution: PD70F3217H, 70F3217HY, 70F3218H, and 70F3218HY use SuperFlash (R) technology licensed from Silicon Storage Technology, Inc. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. User's Manual U16889EJ1V0UD 3 These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. * The information in this document is current as of February, 2004. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1 4 User's Manual U16889EJ1V0UD Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: * * * * * Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements * In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [GLOBAL SUPPORT] http://www.necel.com/en/support/support.html NEC Electronics America, Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 NEC Electronics (Europe) GmbH Duesseldorf, Germany Tel: 0211-65030 * Sucursal en Espana NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-558-3737 Madrid, Spain Tel: 091-504 27 87 * Succursale Francaise Velizy-Villacoublay, France Tel: 01-30-67 58 00 * Filiale Italiana NEC Electronics Shanghai Ltd. Shanghai, P.R. China Tel: 021-5888-5400 Milano, Italy Tel: 02-66 75 41 * Branch The Netherlands NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Eindhoven, The Netherlands Tel: 040-244 58 45 * Tyskland Filial NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 6253-8311 Taeby, Sweden Tel: 08-63 80 820 * United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 J04.1 User's Manual U16889EJ1V0UD 5 PREFACE Readers This manual is intended for users who wish to understand the functions of the V850ES/KJ1 and design application systems using these products. The target products are as follows. * Standard products: PD703216, 703216Y, 703217, 703217Y, 70F3217, 70F3217H, 70F3217HY, 70F3217Y, 70F3218H, 70F3218HY * Special products: PD703216(A), 703216Y(A), 703217(A), 703217Y(A), 70F3217(A), 70F3217Y(A), 703216(A1), 703216Y(A1), 703217(A1), 703217Y(A1), 703216(A2), 703216Y(A2), 703217(A2), 703217Y(A2) Purpose This manual is intended to give users an understanding of the hardware functions of the V850ES/KJ1 shown in the Organization below. Organization This manual is divided into two parts: Hardware (this manual) and Architecture (V850ES Architecture User's Manual). Hardware * Pin functions * CPU function * On-chip peripheral functions * Flash memory programming * Electrical specifications Architecture * Data types * Register set * Instruction format and instruction set * Interrupts and exceptions * Pipeline operation How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. Cautions 1. The application examples in this manual apply to "standard" quality grade products for general electronic systems. When using an example in this manual for an application that requires a "special" quality grade product, thoroughly evaluate the component and circuit to be actually used to see if they satisfy the special quality grade. 2. When using this manual as a manual for a special grade product, read the part numbers as follows. PD703216 PD703216Y PD703217 PD703217Y PD70F3217 PD70F3217Y PD703216(A), 703216(A1), 703216(A2) PD703216Y(A), 703216Y(A1), 703216Y(A2) PD703217(A), 703217(A1), 703217(A2) PD703217Y(A), 703217Y(A1), 703217Y(A2) PD70F3217(A) PD70F3217Y(A) 6 User's Manual U16889EJ1V0UD To find the details of a register where the name is known Refer to APPENDIX C REGISTER INDEX. To understand the details of an instruction function Refer to the V850ES Architecture User's Manual. Register format The name of the bit whose number is in angle brackets (<>) in the figure of the register format of each register is defined as a reserved word in the device file. To understand the overall functions of the V850ES/KJ1 Read this manual according to the CONTENTS. To know the electrical specifications of the V850ES/KJ1 Refer to CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET), CHAPTER 29 ELECTRICAL SPECIFICATIONS ELECTRICAL (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS), CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (TARGET). The "yyy bit of the xxx register" is described as the "xxx.yyy bit" in this manual. Note with caution that even if "xxx.yyy" is described as is in a program, however, the compiler/assembler cannot recognize it correctly. Conventions Data significance: Memory map address: Note: Caution: Remark: Numeric representation: Higher digits on the left and lower digits on the right Higher addresses on the top and lower addresses on the bottom Footnote for item marked with Note in the text Information requiring particular attention Supplementary information Binary Decimal Hexadecimal K (kilo): G (giga): ... xxxx or xxxxB ... xxxx ... xxxxH SPECIFICATIONS ((A1) GRADE PRODUCTS) (TARGET), and CHAPTER 31 Active low representation: xxx (overscore over pin or signal name) Prefix indicating power of 2 (address space, memory capacity): 210 = 1,024 230 = 1,0243 M (mega): 220 = 1,0242 User's Manual U16889EJ1V0UD 7 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/KJ1 Document Name V850ES Architecture User's Manual V850ES/Kx1, V850ES/Kx1+ On-chip Debug User's Manual V850ES/KJ1 Hardware User's Manual Document No. U15943E U16972E This manual Documents related to development tools (user's manuals) Document Name IE-V850ES-G1 (In-Circuit Emulator) IE-703217-G1-EM1 (In-Circuit Emulator Option Board) CA850 Ver. 2.50 C Compiler Package Operation C Language Assembly Language PM plus Ver. 5.10 ID850 Ver. 2.50 Integrated Debugger SM850 Ver. 2.40 System Simulator SM850 Ver. 2.00 or Later System Simulator Operation Operation External Part User Open Interface Specifications RX850 Ver. 3.13 or Later Real-Time OS Basics Installation Technical RX850 Pro Ver. 3.15 Real-Time OS Basics Installation Technical RD850 Ver. 3.01 Task Debugger RD850 Pro Ver. 3.01 Task Debugger AZ850 Ver. 3.20 System Performance Analyzer PG-FP3 Flash Memory Programmer PG-FP4 Flash Memory Programmer U13430E U13410E U13431E U13773E U13774E U13772E U13737E U13916E U14410E U13502E U15260E Document No. U16313E U16594E U16053E U16054E U16042E U16569E U16217E U15182E U14873E 8 User's Manual U16889EJ1V0UD CONTENTS CHAPTER 1 INTRODUCTION .................................................................................................................19 1.1 K1 Family Product Lineup......................................................................................................... 19 1.1.1 1.1.2 V850ES/Kx1+, V850ES/Kx1 products lineup..................................................................................19 78K0/Kx1+, 78K0/Kx1 products lineup ...........................................................................................22 1.2 1.3 1.4 1.5 1.6 1.7 Features ...................................................................................................................................... 25 Applications................................................................................................................................ 26 Ordering Information ................................................................................................................. 27 Pin Configuration (Top View).................................................................................................... 28 Function Block Configuration .................................................................................................. 31 Overview of Functions .............................................................................................................. 35 CHAPTER 2 PIN FUNCTIONS ................................................................................................................36 2.1 2.2 2.3 2.4 List of Pin Functions ................................................................................................................. 36 Pin Status.................................................................................................................................... 45 Pin I/O Circuits and Recommended Connection of Unused Pins......................................... 46 Pin I/O Circuits ........................................................................................................................... 49 CHAPTER 3 CPU FUNCTIONS ..............................................................................................................51 3.1 3.2 Features ...................................................................................................................................... 51 CPU Register Set ....................................................................................................................... 52 3.2.1 3.2.2 Program register set .......................................................................................................................53 System register set.........................................................................................................................54 3.3 3.4 Operating Modes........................................................................................................................ 60 Address Space ........................................................................................................................... 61 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 CPU address space........................................................................................................................61 Wraparound of CPU address space ...............................................................................................62 Memory map...................................................................................................................................63 Areas ..............................................................................................................................................65 Recommended use of address space ............................................................................................70 Peripheral I/O registers...................................................................................................................73 Special registers .............................................................................................................................85 Cautions .........................................................................................................................................88 CHAPTER 4 PORT FUNCTIONS............................................................................................................91 4.1 4.2 4.3 Features ...................................................................................................................................... 91 Basic Port Configuration........................................................................................................... 91 Port Configuration ..................................................................................................................... 92 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 Port 0..............................................................................................................................................97 Port 1............................................................................................................................................100 Port 3............................................................................................................................................102 Port 4............................................................................................................................................107 Port 5............................................................................................................................................109 Port 6............................................................................................................................................112 Port 7............................................................................................................................................117 User's Manual U16889EJ1V0UD 9 4.3.8 4.3.9 Port 8 ........................................................................................................................................... 118 Port 9 ........................................................................................................................................... 121 4.3.10 Port CD ........................................................................................................................................ 129 4.3.11 Port CM........................................................................................................................................ 130 4.3.12 Port CS ........................................................................................................................................ 132 4.3.13 Port CT ........................................................................................................................................ 134 4.3.14 Port DH ........................................................................................................................................ 136 4.3.15 Port DL......................................................................................................................................... 138 4.4 4.5 4.6 Block Diagrams ........................................................................................................................ 141 Port Register Setting When Alternate Function Is Used...................................................... 170 Cautions .................................................................................................................................... 178 4.6.1 4.6.2 Cautions on bit manipulation instruction for port n register (Pn) .................................................. 178 Hysteresis characteristics ............................................................................................................ 179 CHAPTER 5 BUS CONTROL FUNCTION .......................................................................................... 180 5.1 5.2 Features .................................................................................................................................... 180 Bus Control Pins ...................................................................................................................... 181 5.2.1 5.2.2 Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed................... 182 Pin status in each operation mode............................................................................................... 182 Chip select control function.......................................................................................................... 184 5.3 5.4 5.5 Memory Block Function .......................................................................................................... 183 5.3.1 External Bus Interface Mode Control Function..................................................................... 184 Bus Access ............................................................................................................................... 185 5.5.1 5.5.2 5.5.3 Number of clocks for access........................................................................................................ 185 Bus size setting function .............................................................................................................. 185 Access by bus size ...................................................................................................................... 186 Programmable wait function ........................................................................................................ 193 External wait function................................................................................................................... 194 Relationship between programmable wait and external wait ....................................................... 195 Programmable address wait function........................................................................................... 196 5.6 Wait Function............................................................................................................................ 193 5.6.1 5.6.2 5.6.3 5.6.4 5.7 5.8 Idle State Insertion Function................................................................................................... 197 Bus Hold Function ................................................................................................................... 198 5.8.1 5.8.2 5.8.3 Functional outline......................................................................................................................... 198 Bus hold procedure...................................................................................................................... 199 Operation in power save mode .................................................................................................... 199 5.9 5.10 5.11 Bus Priority ............................................................................................................................... 200 Bus Timing................................................................................................................................ 201 Cautions .................................................................................................................................... 207 CHAPTER 6 CLOCK GENERATION FUNCTION............................................................................... 208 6.1 6.2 6.3 6.4 Overview ................................................................................................................................... 208 Configuration............................................................................................................................ 209 Registers ................................................................................................................................... 211 Operation .................................................................................................................................. 215 6.4.1 6.4.2 Operation of each clock ............................................................................................................... 215 Clock output function ................................................................................................................... 215 10 User's Manual U16889EJ1V0UD 6.4.3 External clock input function .........................................................................................................215 Overview ......................................................................................................................................216 Register ........................................................................................................................................216 Usage ...........................................................................................................................................217 6.5 PLL Function ............................................................................................................................ 216 6.5.1 6.5.2 6.5.3 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) .................................................................218 7.1 7.2 7.3 7.4 7.5 Overview ................................................................................................................................... 218 Functions .................................................................................................................................. 218 Configuration............................................................................................................................ 219 Registers................................................................................................................................... 221 Operation .................................................................................................................................. 232 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.5.6 7.5.7 7.5.8 Interval timer mode (TP0MD2 to TP0MD0 bits = 000)..................................................................233 External event count mode (TP0MD2 to TP0MD0 bits = 001)......................................................243 External trigger pulse output mode (TP0MD2 to TP0MD0 bits = 010)..........................................251 One-shot pulse output mode (TP0MD2 to TP0MD0 bits = 011) ...................................................263 PWM output mode (TP0MD2 to TP0MD0 bits = 100)...................................................................270 Free-running timer mode (TP0MD2 to TP0MD0 bits = 101) .........................................................279 Pulse width measurement mode (TP0MD2 to TP0MD0 bits = 110) .............................................296 Timer output operations................................................................................................................302 7.6 Eliminating Noise on Capture Trigger Input Pin (TIP0a)...................................................... 303 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0..............................................................................305 8.1 8.2 8.3 8.4 Functions .................................................................................................................................. 305 Configuration............................................................................................................................ 306 Registers................................................................................................................................... 312 Operation .................................................................................................................................. 325 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.4.7 Operation as interval timer ...........................................................................................................325 PPG output operation ...................................................................................................................328 Pulse width measurement ............................................................................................................332 Operation as external event counter.............................................................................................343 Square-wave output operation......................................................................................................346 One-shot pulse output operation ..................................................................................................349 Cautions .......................................................................................................................................355 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5................................................................................360 9.1 9.2 9.3 9.4 Functions .................................................................................................................................. 360 Configuration............................................................................................................................ 361 Registers................................................................................................................................... 364 Operation .................................................................................................................................. 367 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.4.6 9.4.7 Operation as interval timer ...........................................................................................................367 Operation as external event counter.............................................................................................369 Square-wave output operation......................................................................................................370 8-bit PWM output operation ..........................................................................................................372 Operation as interval timer (16 bits)..............................................................................................375 Operation as external event counter (16 bits)...............................................................................377 Square-wave output operation (16-bit resolution).........................................................................378 User's Manual U16889EJ1V0UD 11 9.4.8 Cautions....................................................................................................................................... 379 CHAPTER 10 8-BIT TIMER H ............................................................................................................. 380 10.1 10.2 10.3 10.4 Functions .................................................................................................................................. 380 Configuration............................................................................................................................ 380 Registers ................................................................................................................................... 383 Operation .................................................................................................................................. 387 10.4.1 Operation as interval timer/square wave output........................................................................... 387 10.4.2 PWM output mode operation ....................................................................................................... 390 10.4.3 Carrier generator mode operation................................................................................................ 396 CHAPTER 11 INTERVAL TIMER, WATCH TIMER ........................................................................... 403 11.1 Interval Timer BRG................................................................................................................... 403 11.1.1 Functions ..................................................................................................................................... 403 11.1.2 Configuration ............................................................................................................................... 403 11.1.3 Registers...................................................................................................................................... 405 11.1.4 Operation ..................................................................................................................................... 407 11.2 Watch Timer.............................................................................................................................. 408 11.2.1 Functions ..................................................................................................................................... 408 11.2.2 Configuration ............................................................................................................................... 408 11.2.3 Registers...................................................................................................................................... 409 11.2.4 Operation ..................................................................................................................................... 411 11.3 Cautions .................................................................................................................................... 412 CHAPTER 12 WATCHDOG TIMER FUNCTIONS .............................................................................. 414 12.1 Watchdog Timer 1 .................................................................................................................... 414 12.1.1 Functions ..................................................................................................................................... 414 12.1.2 Configuration ............................................................................................................................... 416 12.1.3 Registers...................................................................................................................................... 416 12.1.4 Operation ..................................................................................................................................... 418 12.2 Watchdog Timer 2 .................................................................................................................... 420 12.2.1 Functions ..................................................................................................................................... 420 12.2.2 Configuration ............................................................................................................................... 421 12.2.3 Registers...................................................................................................................................... 421 12.2.4 Operation ..................................................................................................................................... 423 CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) ................................................................... 424 13.1 13.2 13.3 13.4 13.5 13.6 13.7 Function .................................................................................................................................... 424 Configuration............................................................................................................................ 425 Registers ................................................................................................................................... 426 Operation .................................................................................................................................. 428 Usage......................................................................................................................................... 429 Cautions .................................................................................................................................... 429 Security Function ..................................................................................................................... 430 CHAPTER 14 A/D CONVERTER ......................................................................................................... 432 14.1 12 Function .................................................................................................................................... 432 User's Manual U16889EJ1V0UD 14.2 14.3 14.4 Configuration............................................................................................................................ 433 Registers................................................................................................................................... 435 Operation .................................................................................................................................. 442 14.4.1 Basic operation.............................................................................................................................442 14.4.2 A/D conversion operation .............................................................................................................443 14.4.3 Power fail monitoring function.......................................................................................................443 14.5 14.6 Cautions.................................................................................................................................... 445 How to Read A/D Converter Characteristics Table .............................................................. 450 CHAPTER 15 D/A CONVERTER ..........................................................................................................454 15.1 15.2 15.3 15.4 Functions .................................................................................................................................. 454 Configuration............................................................................................................................ 455 Registers................................................................................................................................... 456 Operation .................................................................................................................................. 457 15.4.1 Operation in normal mode ............................................................................................................457 15.4.2 Operation in real-time output mode ..............................................................................................457 15.4.3 Cautions .......................................................................................................................................458 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) .....................................................459 16.1 16.2 16.3 16.4 16.5 16.6 Selecting UART2 or I2C1 Mode ............................................................................................... 459 Features .................................................................................................................................... 460 Configuration............................................................................................................................ 461 Registers................................................................................................................................... 463 Interrupt Requests ................................................................................................................... 469 Operation .................................................................................................................................. 470 16.6.1 16.6.2 Data format...................................................................................................................................470 Transmit operation........................................................................................................................471 16.6.3 Continuous transmission operation ..............................................................................................473 16.6.4 Receive operation.........................................................................................................................477 16.6.5 Reception error.............................................................................................................................478 16.6.6 Parity types and corresponding operation ....................................................................................480 16.6.7 Receive data noise filter ...............................................................................................................481 16.7 Dedicated Baud Rate Generator n (BRGn)............................................................................ 482 16.7.1 Baud rate generator n (BRGn) configuration ................................................................................482 16.7.2 Serial clock generation .................................................................................................................483 16.7.3 Baud rate setting example ............................................................................................................486 16.7.4 Allowable baud rate range during reception .................................................................................487 16.7.5 Transfer rate during continuous transmission...............................................................................489 16.8 Cautions.................................................................................................................................... 489 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0).................................................................490 17.1 17.2 17.3 17.4 Features .................................................................................................................................... 490 Configuration............................................................................................................................ 491 Registers................................................................................................................................... 494 Operation .................................................................................................................................. 503 17.4.1 Transmission/reception completion interrupt request signal (INTCSI0n)......................................503 17.4.2 Single transfer mode ....................................................................................................................505 User's Manual U16889EJ1V0UD 13 17.4.3 Continuous transfer mode............................................................................................................ 508 17.5 Output Pins ............................................................................................................................... 516 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION ................................................................................ 517 18.1 18.2 18.3 18.4 Functions .................................................................................................................................. 517 Configuration............................................................................................................................ 518 Registers ................................................................................................................................... 520 Operation .................................................................................................................................. 529 18.4.1 3-wire serial I/O mode.................................................................................................................. 529 18.4.2 3-wire serial I/O mode with automatic transmit/receive function .................................................. 533 CHAPTER 19 I2C BUS .......................................................................................................................... 549 19.1 19.2 19.3 19.4 19.5 19.6 Selecting UART2 or I2C1 Mode................................................................................................ 549 Features .................................................................................................................................... 550 Configuration............................................................................................................................ 553 Registers ................................................................................................................................... 555 Functions .................................................................................................................................. 568 19.5.1 Pin configuration .......................................................................................................................... 568 I2C Bus Definitions and Control Methods .............................................................................. 569 19.6.1 Start condition.............................................................................................................................. 569 19.6.2 Addresses.................................................................................................................................... 570 19.6.3 Transfer direction specification .................................................................................................... 571 19.6.4 19.6.6 Acknowledge signal (ACK) .......................................................................................................... 572 Wait signal (WAIT)....................................................................................................................... 574 19.6.5 Stop condition .............................................................................................................................. 573 19.7 I C Interrupt Request Signals (INTIICn).................................................................................. 576 19.7.1 Master device operation............................................................................................................... 576 19.7.2 Slave device operation (when receiving slave address data (match with address)) .................... 579 19.7.3 Slave device operation (when receiving extension code) ............................................................ 583 19.7.4 Operation without communication................................................................................................ 587 19.7.5 Arbitration loss operation (operation as slave after arbitration loss) ............................................ 587 19.7.6 Operation when arbitration loss occurs (no communication after arbitration loss) ....................... 589 2 19.8 19.9 19.10 19.11 19.12 19.13 19.14 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control .......................... 594 Address Match Detection Method .......................................................................................... 595 Error Detection ......................................................................................................................... 595 Extension Code ........................................................................................................................ 596 Arbitration ................................................................................................................................. 597 Wakeup Function ..................................................................................................................... 598 Communication Reservation .................................................................................................. 599 19.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0) ........................... 599 19.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1) .......................... 602 19.15 Cautions .................................................................................................................................... 603 19.16 Communication Operations .................................................................................................... 603 19.16.1 Master operation 1....................................................................................................................... 603 19.16.2 Master operation 2....................................................................................................................... 605 19.16.3 Slave operation............................................................................................................................ 606 14 User's Manual U16889EJ1V0UD 19.17 Timing of Data Communication.............................................................................................. 609 CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION................................................616 20.1 20.2 Overview ................................................................................................................................... 616 20.1.1 Features .......................................................................................................................................616 Non-Maskable Interrupts......................................................................................................... 620 20.2.1 Operation......................................................................................................................................623 20.2.2 20.2.3 Restore .........................................................................................................................................624 NP flag..........................................................................................................................................625 20.3 Maskable Interrupts ................................................................................................................. 626 20.3.1 Operation......................................................................................................................................626 20.3.2 20.3.4 20.3.6 20.3.7 Restore .........................................................................................................................................628 Interrupt control register (xxlCn) ...................................................................................................633 In-service priority register (ISPR)..................................................................................................638 ID flag ...........................................................................................................................................639 20.3.3 Priorities of maskable interrupts ...................................................................................................629 20.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3).............................................................................636 20.3.8 Watchdog timer mode register 1 (WDTM1) ..................................................................................640 20.4 External Interrupt Request Input Pins (NMI, INTP0 to INTP6) ............................................. 641 20.4.1 Noise elimination ..........................................................................................................................641 20.4.2 Edge detection..............................................................................................................................641 20.5 Software Exceptions................................................................................................................ 644 20.5.1 Operation......................................................................................................................................644 20.5.2 20.5.3 Restore .........................................................................................................................................645 EP flag..........................................................................................................................................646 20.6 Exception Trap ......................................................................................................................... 647 20.6.1 Illegal op code ..............................................................................................................................647 20.6.2 Debug trap....................................................................................................................................649 20.7 20.8 20.9 20.10 Multiple Interrupt Servicing Control ...................................................................................... 651 Interrupt Response Time......................................................................................................... 653 Periods in Which Interrupts Are Not Acknowledged by CPU ............................................. 654 Cautions.................................................................................................................................... 654 CHAPTER 21 KEY INTERRUPT FUNCTION ......................................................................................655 21.1 21.2 Function .................................................................................................................................... 655 Register..................................................................................................................................... 656 CHAPTER 22 STANDBY FUNCTION...................................................................................................657 22.1 22.2 22.3 Overview ................................................................................................................................... 657 Registers................................................................................................................................... 660 HALT Mode ............................................................................................................................... 663 22.3.1 Setting and operation status .........................................................................................................663 22.3.2 Releasing HALT mode .................................................................................................................663 22.4 IDLE Mode................................................................................................................................. 665 22.4.1 Setting and operation status .........................................................................................................665 22.4.2 Releasing IDLE mode...................................................................................................................665 22.5 STOP Mode ............................................................................................................................... 667 User's Manual U16889EJ1V0UD 15 22.5.1 Setting and operation status ........................................................................................................ 667 22.5.2 Releasing STOP mode ................................................................................................................ 667 22.5.3 Securing oscillation stabilization time when STOP mode is released .......................................... 669 22.6 Subclock Operation Mode....................................................................................................... 670 22.6.1 Setting and operation status ........................................................................................................ 670 22.6.2 Releasing subclock operation mode ............................................................................................ 670 22.7 Sub-IDLE Mode......................................................................................................................... 672 22.7.1 Setting and operation status ........................................................................................................ 672 22.7.2 Releasing sub-IDLE mode ........................................................................................................... 672 CHAPTER 23 RESET FUNCTION........................................................................................................ 674 23.1 23.2 23.3 Overview ................................................................................................................................... 674 Configuration............................................................................................................................ 674 Operation .................................................................................................................................. 675 CHAPTER 24 REGULATOR ................................................................................................................. 678 24.1 24.2 Overview ................................................................................................................................... 678 Operation .................................................................................................................................. 678 CHAPTER 25 ROM CORRECTION FUNCTION................................................................................. 680 25.1 25.2 25.3 Overview ................................................................................................................................... 680 Registers ................................................................................................................................... 681 ROM Correction Operation and Program Flow ..................................................................... 682 CHAPTER 26 FLASH MEMORY (SINGLE POWER) ........................................................................ 684 26.1 26.2 26.3 26.4 Features .................................................................................................................................... 684 Memory Configuration ............................................................................................................. 685 Functional Outline.................................................................................................................... 686 Rewriting by Dedicated Flash Programmer .......................................................................... 688 26.4.1 26.4.2 26.4.3 26.4.4 26.4.5 26.4.6 Programming environment........................................................................................................... 688 Communication mode .................................................................................................................. 689 Flash memory control .................................................................................................................. 694 Selection of communication mode ............................................................................................... 695 Communication commands ......................................................................................................... 696 Pin connection ............................................................................................................................. 697 Overview...................................................................................................................................... 702 Features....................................................................................................................................... 703 Standard self programming flow .................................................................................................. 704 Flash functions............................................................................................................................. 705 Pin processing ............................................................................................................................. 705 Internal resources used ............................................................................................................... 706 26.5 Rewriting by Self Programming.............................................................................................. 702 26.5.1 26.5.2 26.5.3 26.5.4 26.5.5 26.5.6 CHAPTER 27 FLASH MEMORY (TWO POWER) ............................................................................. 707 27.1 27.2 27.3 16 Features .................................................................................................................................... 707 Writing with Flash Programmer.............................................................................................. 708 Programming Environment..................................................................................................... 711 User's Manual U16889EJ1V0UD 27.4 27.5 Communication Mode ............................................................................................................. 711 Pin Processing ......................................................................................................................... 714 27.5.1 27.5.2 27.5.3 27.5.4 27.5.5 VPP pin ..........................................................................................................................................714 Serial interface pins ......................................................................................................................715 RESET pin....................................................................................................................................717 Port pins .......................................................................................................................................717 Other signal pins...........................................................................................................................717 27.5.6 Power supply ................................................................................................................................717 27.6 Programming Method.............................................................................................................. 718 27.6.1 Controlling flash memory ..............................................................................................................718 27.6.2 Flash memory programming mode...............................................................................................719 27.6.3 Selecting communication mode....................................................................................................719 27.6.4 Communication commands ..........................................................................................................720 CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET)..................................................................................721 CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) ...................................................................................................................768 CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (TARGET)........................................................................................................................815 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (TARGET)........................................................................................................................836 CHAPTER 32 PACKAGE DRAWING ...................................................................................................857 CHAPTER 33 RECOMMENDED SOLDERING CONDITIONS............................................................858 APPENDIX A DEVELOPMENT TOOLS ...............................................................................................860 A.1 A.2 A.3 A.4 Software Package .................................................................................................................... 862 Language Processing Software ............................................................................................. 862 Control Software ...................................................................................................................... 862 Debugging Tools (Hardware).................................................................................................. 863 A.4.1 A.4.2 A.4.3 When using in-circuit emulator IE-V850ES-G1.............................................................................863 When using in-circuit emulator IE-V850ESK1-ET.........................................................................863 When using in-circuit emulator QB-V850ESKX1H........................................................................863 A.5 A.6 A.7 Debugging Tools (Software) ................................................................................................... 864 Embedded Software ................................................................................................................ 865 Flash Memory Writing Tools................................................................................................... 865 APPENDIX B INSTRUCTION SET LIST..............................................................................................866 B.1 B.2 Conventions ............................................................................................................................. 866 Instruction Set (in Alphabetical Order).................................................................................. 869 User's Manual U16889EJ1V0UD 17 APPENDIX C REGISTER INDEX ......................................................................................................... 876 APPENDIX D REVISION HISTORY ..................................................................................................... 884 D.1 Modifications from Document Number U15862EJ4V1UD00 ................................................ 884 18 User's Manual U16889EJ1V0UD CHAPTER 1 INTRODUCTION 1.1 K1 Family Product Lineup 1.1.1 V850ES/Kx1+, V850ES/Kx1 products lineup * 64-pin plastic LQFP (10 x 10 mm, 0.5 mm pitch) * 64-pin plastic TQFP (12 x 12 mm, 0.65 mm pitch) * 64-pin plastic LQFP (14 x 14 mm, 0.8 mm pitch) V850ES/KE1 V850ES/KE1+ PD70F3207HY PD70F3207H Single-power flash: 128 KB, RAM: 4 KB PD703207Y PD703207 Mask ROM: 128 KB, RAM: 4 KB PD70F3302Y PD70F3302 Single-power flash: 128 KB, RAM: 4 KB PD703302Y PD703302 Mask ROM: 128 KB, RAM: 4 KB * 80-pin plastic TQFP (12 x 12 mm, 0.5 mm pitch) * 80-pin plastic QFP (14 x 14 mm, 0.65 mm pitch) V850ES/KF1 V850ES/KF1+ PD70F3211HY PD70F3211H Single-power flash: 256 KB, RAM: 12 KB PD703211Y PD703211 Mask ROM: 256 KB, RAM: 12 KB PD70F3308Y PD70F3308 Single-power flash: 256 KB, RAM: 12 KB PD703308Y PD703308 Mask ROM: 256 KB, RAM: 12 KB PD70F3210HY PD70F3210H Single-power flash: 128 KB, RAM: 6 KB PD70F3210Y PD703210Y PD703210 Mask ROM: 128 KB, RAM: 4 KB PD703209Y PD70F3306Y PD70F3306 Single-power flash: 128 KB, RAM: 6 KB PD70F3210 Two-power flash: 128 KB, RAM: 6 KB PD703209 Mask ROM: 96 KB, RAM: 4 KB PD703208Y PD703208 * 100-pin plastic LQFP (14 x 14 mm, 0.5 mm pitch) * 100-pin plastic QFP (14 x 20 mm, 0.65 mm pitch) V850ES/KG1 Mask ROM: 64 KB, RAM: 4 KB V850ES/KG1+ PD70F3215HY PD70F3215H Single-power flash: 256 KB, RAM: 16 KB PD703215Y PD703215 Mask ROM: 256 KB, RAM: 16 KB PD70F3313Y PD70F3313 Single-power flash: 256 KB, RAM: 16 KB PD703313Y PD703313 Mask ROM: 256 KB, RAM: 16 KB PD70F3214HY PD70F3214H Single-power flash: 128 KB, RAM: 6 KB PD70F3214Y PD703214Y PD703214 Mask ROM: 128 KB, RAM: 6 KB PD703213Y PD70F3311Y PD70F3311 Single-power flash: 128 KB, RAM: 6 KB PD70F3214 Two-power flash: 128 KB, RAM: 6 KB PD703213 Mask ROM: 96 KB, RAM: 4 KB PD703212Y PD703212 Mask ROM: 64 KB, RAM: 4 KB * 144-pin plastic LQFP (20 x 20 mm, 0.5 mm pitch) V850ES/KJ1 V850ES/KJ1+ PD70F3218HY PD70F3218H Single-power flash: 256 KB, RAM: 16 KB PD70F3318Y PD70F3318 Single-power flash: 256 KB, RAM: 16 KB PD70F3217HY PD70F3217H Single-power flash: 128 KB, RAM: 6 KB PD70F3217Y PD703217Y PD703217 Mask ROM: 128 KB, RAM: 6 KB PD703216Y PD70F3316Y PD70F3316 Single-power flash: 128 KB, RAM: 6 KB PD70F3217 Two-power flash: 128 KB, RAM: 6 KB PD703216 Mask ROM: 96 KB, RAM: 4 KB User's Manual U16889EJ1V0UD 19 CHAPTER 1 INTRODUCTION The function list of the V850ES/Kx1+ is shown below. Product Name Number of pins Internal memory (KB) Mask ROM Flash memory RAM 2.7 to 5.5 V 50 ns @20 MHz 2 to 10 MHz 32.768 kHz 240 kHz (TYP.) 8 43 2 1 ch 1 ch 2 ch 2 ch 1 ch 1 ch 1 ch 1 ch 6 bits x 1 ch CSI Automatic transmit/receive 3-wire CSI UART UART supporting LIN-bus IC External bus 2 Note V850ES/KE1+ 64 pins 128 - 4 - 128 - 128 6 V850ES/KF1+ 80 pins 256 - 12 - 256 - V850ES/KG1+ 100 pins 256 - 16 - 256 V850ES/KJ1+ 144 pins - 128 6 - 256 16 128 6 Supply voltage Minimum instruction execution time Clock X1 input Subclock Ring-OSC Port CMOS input CMOS I/O N-ch open-drain I/O Timer 16-bit (TMP) 16-bit (TM0) 8-bit (TM5) 8-bit (TMH) Interval timer Watch WDT1 WDT2 RTO Serial interface 8 59 2 1 ch 2 ch 2 ch 2 ch 1 ch 1 ch 1 ch 1 ch 6 bits x 1 ch 2 ch - 1 ch 8 76 4 1 ch 4 ch 2 ch 2 ch 1 ch 1 ch 1 ch 1 ch 6 bits x 1 ch 2 ch 2 ch 16 112 6 1 ch 6 ch 2 ch 2 ch 1 ch 1 ch 1 ch 1 ch 6 bits x 2 ch 3 ch 2 ch 2 ch 1 ch 1 ch 1 ch - - - - 8 ch - 9 27 8 ch Provided 2.7 V or less fixed 1 ch 1 ch 1 ch 128 KB 16 bits Multiplex only - 8 ch - 9 30 8 ch 2 ch 1 ch 1 ch 3 MB 22 bits Multiplex/separate 4 ch 8 ch 2 ch 9 42 8 ch 2 ch 1 ch 2 ch 15 MB 24 bits Address space Address bus Mode DMA controller 10-bit A/D converter 8-bit D/A converter Interrupt External Internal Key return input Reset RESET pin POC LVI Clock monitor WDT1 WDT2 ROM correction Regulator Standby function Operating ambient temperature 4 ch 16 ch 2 ch 9 48 8 ch 3.1 V/3.3 V 0.15 V or 3.5 V/3.7 V/3.9 V/4.1 V/4.3 V 0.2 V (selectable by software) Provided (monitor by Ring-OSC) Provided Provided 4 None Provided None HALT/IDLE/STOP/sub-IDLE mode TA = -40 to +85C Note Only in products with an I2C bus (Y products) 20 User's Manual U16889EJ1V0UD CHAPTER 1 INTRODUCTION The function list of the V850ES/Kx1 is shown below. Product Name Number of pins Internal memory (KB) Flash memory RAM Supply voltage Minimum instruction execution time Clock X1 input Subclock Ring-OSC Port CMOS input CMOS I/O N-ch open-drain I/O Timer 16-bit (TMP) 16-bit (TM0) 8-bit (TM5) 8-bit (TMH) Interval timer Watch WDT1 WDT2 RTO Serial interface CSI Automatic transmit/receive 3-wire CSI UART UART supporting LIN-bus I2CNote External bus Address space Address bus Mode DMA controller 10-bit A/D converter 8-bit D/A converter Interrupt External Internal Key return input Reset RESET pin POC LVI Clock monitor WDT1 WDT2 ROM correction Regulator Standby function Operating ambient temperature 8 26 8 ch Provided None None None Provided Provided 4 None Provided 8 ch - 8 26 8 ch 29 1 ch - - - - 8 ch - 2 ch - 1 ch 128 KB 16 bits Multiplex only - 8 ch 2 ch 8 31 8 ch 34 2 ch - 1 ch 3 MB 22 bits Multiplex/separate - 16 ch 2 ch 8 40 8 ch 43 - 2 ch - 2 ch 15 MB 24 bits 3 ch - 8 43 2 1 ch 1 ch 2 ch 2 ch 1 ch 1 ch 1 ch 1 ch 6 bits x 1 ch 2 ch - 2 ch 2 ch 2 ch 1 ch 1 ch 1 ch 1 ch 6 bits x 1 ch 2 ch 1 ch 8 59 2 - 1 ch 4 ch 2 ch 2 ch 1 ch 1 ch 1 ch 1 ch 6 bits x 1 ch 2 ch 2 ch 2.7 to 5.5 V 50 ns @20 MHz 2 to 10 MHz 32.768 kHz - 8 76 4 - 1 ch 6 ch 2 ch 2 ch 1 ch 1 ch 1 ch 1 ch 6 bits x 2 ch 3 ch 2 ch 16 112 6 - 1 ch - 4 128 Mask ROM 128 V850ES/KE1 64 pins - V850ES/KF1 80 pins 64/ 128 96 - 4 - 6 128 - 256 12 - 256 - V850ES/KG1 100 pins 64/ 128 96 - 4 - 6 128 - 256 16 - 6 128 256 16 - 256 - 96/128 V850ES/KJ1 144 pins - - HALT/IDLE/STOP/sub-IDLE mode TA = -40 to +85C Note Only in products with an I2C bus (Y products) User's Manual U16889EJ1V0UD 21 CHAPTER 1 INTRODUCTION 1.1.2 78K0/Kx1+, 78K0/Kx1 products lineup 30-pin SSOP (7.62 mm 0.65 mm pitch) 78K0/KB1 PD78F0103 Two-power flash: 24 KB, RAM: 768 B 78K0/KB1+ PD78F0103H Single-power flash: 24 KB, RAM: 768 B PD780103 Mask ROM: 24 KB, RAM: 768 B PD780102 Mask ROM: 16 KB, RAM: 768 B PD780101 Mask ROM: 8 KB, RAM: 512 B PD78F0102H Single-power flash: 16 KB, RAM: 768 B PD78F0101H Single-power flash: 8 KB, RAM: 512 B 44-pin LQFP (10 x 10 mm 0.8 mm pitch) 78K0/KC1 PD78F0114 Two-power flash: 32 KB, RAM: 1 KB 78K0/KC1+ PD78F0114H/HDNote Single-power flash: 32 KB, RAM: 1 KB PD780114 Mask ROM: 32 KB, RAM: 1 KB PD780113 Mask ROM: 24 KB, RAM: 1 KB PD78F0113H Single-power flash: 24 KB, RAM: 1 KB PD780112 Mask ROM: 16 KB, RAM: 512 B PD78F0112H Single-power flash: 16 KB, RAM: 512 B PD780111 Mask ROM: 8 KB, RAM: 512 B 52-pin LQFP (10 x 10 mm 0.65 mm pitch) 78K0/KD1 PD78F0124 Two-power flash: 32 KB, RAM: 1 KB 78K0/KD1+ PD78F0124H/HDNote Single-power flash: 32 KB, RAM: 1 KB PD78F0123H Single-power flash: 24 KB, RAM: 1 KB PD780124 Mask ROM: 32 KB, RAM: 1 KB PD780123 Mask ROM: 24 KB, RAM: 1 KB PD780122 Mask ROM: 16 KB, RAM: 512 B PD780121 Mask ROM: 8 KB, RAM: 512 B PD78F0122H Single-power flash: 16 KB, RAM: 512 B 64-pin LQFP, TQFP (10 x 10 mm 0.5 mm pitch, 12 x 12 mm 0.65 mm pitch, 14 x 14 mm 0.8 mm pitch) 78K0/KE1+ 78K0/KE1 PD78F0138 Flash memory: 60 KB, RAM: 2 KB PD780138 Mask ROM: 60 KB, RAM: 2 KB PD78F0138H/HDNote Single-power flash: 60 KB, RAM: 2 KB PD78F0136H Single-power flash: 48 KB, RAM: 2 KB PD78F0134H Single-power flash: 32 KB, RAM: 1 KB PD780136 Mask ROM: 48 KB, RAM: 2 KB PD78F0134 Flash memory: 32 KB, RAM: 1 KB PD780134 Mask ROM: 32 KB, RAM: 1 KB PD780133 Mask ROM: 24 KB, RAM: 1 KB PD780132 Mask ROM: 16 KB, RAM: 512 B PD78F0133H Single-power flash: 24 KB, RAM: 1 KB PD78F0132H Single-power flash: 16 KB, RAM: 512 B PD780131 Mask ROM: 8 KB, RAM: 512 B 80-pin TQFP, QFP (12 x 12 mm 0.5 mm pitch, 14 x 14 mm 0.65 mm pitch) 78K0/KF1 78K0/KF1+ PD78F0148 Flash memory: 60 KB, RAM: 2 KB PD780148 Mask ROM: 60 KB, RAM: 2 KB PD780146 Mask ROM: 48 KB, RAM: 2 KB PD780144 Mask ROM: 32 KB, RAM: 1 KB PD78F0148H/HDNote Single-power flash: 60 KB, RAM: 2 KB PD780143 Mask ROM: 24 KB, RAM: 1 KB Note Products with an on-chip function 22 User's Manual U16889EJ1V0UD CHAPTER 1 INTRODUCTION The function list of the 78K0/Kx1+ is shown below. Product Name Item Number of pins Internal memory (byte) RAM 512 768 512 512 1K 512 Flash memory 30 pins 8K 16 K/24 K 44 pins 16 K 24 K/32 K 52 pins 16 K 24 K/32 K 64 pins 16 K 24 K/ 32 K 1K 48 K/ 60 K 2K 2K 80 pins 60 K 78K0/KB1+ 78K0/KC1+ 78K0/KD1+ 78K0/KE1+ 78K0/KF1+ Supply voltage Minimum instruction execution time VDD = 2.7 to 5.5 V 0.125 s (16 MHz, when VDD = 4.0 to 5.5 V) 0.24 s (8.38 MHz, when VDD = 3.3 to 5.5 V) 0.4 s (5 MHz, when VDD = 2.7 to 5.5 V) Clock X1 input RC Sub Ring-OSC 2 to 16 MHz 3 to 4 MHz (VDD = 2.7 to 5.5 V) - 240 kHz (TYP.) 17 4 1 - 1 ch 2 ch 1 ch - 1 ch 1 ch - - 1 ch 2 ch 1 ch 2 ch 1 ch 4 2 ch 19 8 26 38 54 32.768 kHz - Port CMOS I/O CMOS input CMOS output N-ch open-drain I/O Timer 16-bit (TM0) 8-bit (TM5) 8-bit (TMH) Watch WDT Serial interface 3-wire CSINote Automatic transmit/ receive 3-wire CSI UARTNote UART supporting LIN-bus 1 ch 10-bit A/D converter Interrupt External Internal Key return input Reset RESET pin POC LVI Clock monitor WDT Clock output/buzzer output External bus interface Multiplier/divider ROM correction Self programming function On-chip debug function Standby function Operating ambient temperature 4 ch 6 11 - Provided 12 8 ch 7 15 4 ch 8 15 8 ch 9 16 19 9 20 2.1 V 0.1 V (detection voltage fixed) 2.35 V/2.6 V/2.85 V/3.1 V/3.3 V 0.15 V/3.5 V/3.7 V/3.9 V/4.1 V/4.3 V 0.2 V (selectable by software) Provided Provided - - - - Provided Function provided only in PD78F0114HD, 78F0124HD, 78F0138HD, and 78F0148HD HALT/STOP mode -40 to +85C Clock output only Provided Provided 16 bits x 16 bits, 32 bits / 16 bits Provided - Note If the pin is an alternate-function pin, either function is selected for use. User's Manual U16889EJ1V0UD 23 CHAPTER 1 INTRODUCTION The function list of the 78K0/Kx1 is shown below. Product Name Item Number of pins Internal memory (byte) Flash memory RAM Supply voltage Minimum instruction execution time 0.2 s (10 MHz, when VDD = 4.0 to 5.5 V) 0.24 s (8.38 MHz, when VDD = 3.3 to 5.5 V) 0.4 s (5 MHz, when VDD = 2.7 to 5.5 V) 512 - Mask ROM 8K 30 pins 16 K/ 24 K 24 K 768 512 - 44 pins 8 K/ 24 K/ 16 K 32 K - 32 K 1K 512 - 52 pins 8 K/ 24 K/ 16 K 32 K - 32 K 1K 512 - 8 K/ 24 K/ 16 K 32 K - 32 K 1K 64 pins - 48 K/ 60 K - 60 K 2K 1K - 80 pins 24 K/ 48 K/ 32 K 60 K - 60 K 2K - 78K0/KB1 78K0/KC1 78K0/KD1 78K0/KE1 78K0/KF1 VDD = 2.7 to 5.5 V Clock X1 input Sub RC Ring-OSC - 2 to 10 MHz 32.768 kHz - 240 kHz (TYP.) 17 4 1 - 1 ch 1 ch 2 ch - 1 ch 1 ch - - 2 ch 1 ch 2 ch 1 ch 1 ch 2 ch 4 2 ch 1 ch 2 ch 19 26 8 38 54 Port CMOS I/O CMOS input CMOS output N-ch open-drain I/O Timer 16-bit (TM0) 8-bit (TM5) 8-bit (TMH) Watch WDT Serial interface 3-wire CSINote Automatic transmit/ receive 3-wire CSI UARTNote UART supporting LIN-bus 1 ch 1 ch 10-bit A/D converter Interrupt External Internal Key return input Reset RESET pin POC LVI Clock monitor WDT Clock output/buzzer output Multiplier/divider ROM correction Standby function Operating ambient temperature 11 4 ch 6 12 - 4 ch Provided 7 15 8 16 8 ch 9 19 8 ch 17 9 20 2.85 V 0.15 V/3.5 V 0.20 V (selectable by a mask option) 3.1 V/3.3 V 0.15 V/3.5 V/3.7 V/3.9 V/4.1 V/4.3 V 0.2 V (selectable by software) Provided Provided - - - HALT/STOP mode Standard products, special grade (A) products: -40 to +85C Special grade (A1) products: -40 to +110C (mask ROM version), -40 to +105C (flash memory version) Special grade (A2) products: -40 to +125C (mask ROM version) Clock output Provided 16 bits x 16 bits, 32 bits / 16 bits Provided - Note If the pin is an alternate-function pin, either function is selected for use. 24 User's Manual U16889EJ1V0UD CHAPTER 1 INTRODUCTION 1.2 Features Minimum instruction execution time: 50 ns (operation at main clock (fXX) = 20 MHz) General-purpose registers: 32 bits x 32 registers CPU features: Signed multiplication (16 x 16 32): 1 to 2 clocks (Instructions without creating register hazards can be continuously executed in parallel) Saturated operations (overflow and underflow detection functions are included) 32-bit shift instruction: 1 clock Bit manipulation instructions Load/store instructions with long/short format Memory space: 64 MB of linear address space Memory block division function: 2 MB, 2 MB, 4 MB, 8 MB (Total of 4 blocks) * Internal memory PD703216, 703216Y (Mask ROM: 96 KB/RAM: 6 KB) PD703217, 703217Y (Mask ROM: 128 KB/RAM: 6 KB) PD70F3217, 70F3217Y, 70F3217H, 70F3217HY (Flash memory: 128 KB/RAM: 6 KB) PD70F3218H, 70F3218HY (Flash memory: 256 KB/RAM: 16 KB) * External bus interface Separate bus/multiplex bus output selectable 8-/16-bit data bus sizing function Wait function * Programmable wait function * External wait function Idle state function Bus hold function Interrupts and exceptions Non-maskable interrupts: 3 sources Maskable interrupts: 43 sources (PD703216, 703217, 70F3217, 70F3217H) 45 sources (PD703216Y, 703217Y, 70F3217Y, 70F3217HY) 46 sources (PD70F3218H) 48 sources (PD70F3218HY) Software exceptions: Exception trap: I/O lines: Timer function 16-bit timer/event counter P: 1 channel (PD70F3218H, 70F3218HY only) 16-bit timer/event counter 0: 6 channels 8-bit timer/event counter 5: 8-bit timer H: 8-bit interval timer BRG: Watch timer/interval timer: Watchdog timers Watchdog timer 1 (also usable as oscillation stabilization timer): 1 channel Watchdog timer 2: 1 channel 2 channels 2 channels 1 channel 1 channel Total: 128 Key interrupt function 32 sources 1 source User's Manual U16889EJ1V0UD 25 CHAPTER 1 INTRODUCTION Serial interface Asynchronous serial interface (UART): 3-wire serial I/O (CSI0): I2C bus interface (I2C): (PD703216Y, 703217Y, 70F3217Y, 70F3217HY, 70F3218HY) A/D converter: 10-bit resolution x 16 channels D/A converter: 8-bit resolution x 2 channels Real-time output port: 6 bits x 2 channels Standby functions: HALT/IDLE/STOP modes, subclock/sub-IDLE modes ROM correction: 4 correction addresses specifiable Clock generator Main clock oscillation (fX)/subclock oscillation (fXT) CPU clock (fCPU) 7 steps (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT) Clock-through mode/PLL mode selectable Reset * Reset by RESET pin * Reset by overflow of watchdog timer 1 (WDTRES1) * Reset by overflow of watchdog timer 2 (WDTRES2) Package: 144-pin plastic LQFP (fine pitch) (20 x 20) 3 channels 3 channels 2 channels 3-wire serial I/O (with automatic transmit/receive function) (CSIA): 2 channels 1.3 Applications Automotive * System control of body electrical system (power windows, keyless entry reception, etc.) * Submicrocontroller of control system Home audio, car audio AV equipment PC peripheral devices (keyboards, etc.) Household appliances * Outdoor units of air conditioners * Microwave ovens, rice cookers Industrial devices * Pumps * Vending machines * FA 26 User's Manual U16889EJ1V0UD CHAPTER 1 INTRODUCTION 1.4 Ordering Information Part Number Package 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) Quality Grade Standard Standard Standard Standard Standard Standard Standard Standard Standard Standard Special Special Special Special Special Special Special Special Special Special Special Special Special Special PD703216GJ-xxx-UEN PD703216YGJ-xxx-UEN PD703217GJ-xxx-UEN PD703217YGJ-xxx-UEN PD70F3217GJ-UEN PD70F3217YGJ-UEN PD70F3217HGJ-UENNote PD70F3217HYGJ-UENNote PD70F3218HGJ-UENNote PD70F3218HYGJ-UENNote PD703216GJ(A)-xxx-UEN PD703216YGJ(A)-xxx-UEN PD703217GJ(A)-xxx-UEN PD703217YGJ(A)-xxx-UEN PD70F3217GJ(A)-UENNote PD70F3217YGJ(A)-UENNote PD703216GJ(A1)-xxx-UENNote PD703216YGJ(A1)-xxx-UENNote PD703217GJ(A1)-xxx-UENNote PD703217YGJ(A1)-xxx-UENNote PD703216GJ(A2)-xxx-UENNote PD703216YGJ(A2)-xxx-UENNote PD703217GJ(A2)-xxx-UENNote PD703217YGJ(A2)-xxx-UENNote Note Under development Remark xxx indicates ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Electronics Corporation to know the specification of the quality grade on the device and its recommended applications. User's Manual U16889EJ1V0UD 27 CHAPTER 1 INTRODUCTION 1.5 Pin Configuration (Top View) 144-pin plastic LQFP (fine pitch) (20 x 20) PD703216GJ-xxx-UEN PD703216YGJ-xxx-UEN PD703217GJ-xxx-UEN PD703217YGJ-xxx-UEN PD70F3217GJ-UEN PD70F3217YGJ-UEN PD70F3217HGJ-UEN PD70F3217HYGJ-UEN PD70F3218HGJ-UEN PD70F3218HYGJ-UEN PD703216GJ(A)-xxx-UEN PD703216YGJ(A)-xxx-UEN PD703217GJ(A)-xxx-UEN PD703217YGJ(A)-xxx-UEN PD70F3217GJ(A)-UEN PD70F3217YGJ(A)-UEN PD703216GJ(A1)-xxx-UEN PD703216YGJ(A1)-xxx-UEN PD703217GJ(A1)-xxx-UEN PD703217YGJ(A1)-xxx-UEN PD703216GJ(A2)-xxx-UEN PD703216YGJ(A2)-xxx-UEN PD703217GJ(A2)-xxx-UEN PD703217YGJ(A2)-xxx-UEN 28 User's Manual U16889EJ1V0UD CHAPTER 1 INTRODUCTION AVREF0 AVSS P10/ANO0 P11/ANO1 AVREF1 P00/TOH0 P01/TOH1 VPPNote 1/ICNote 1/FLMD0Note 1 VDD REGCNote 2 VSS X1 X2 RESET XT1 XT2 P02/NMI P03/INTP0 P04/INTP1 P05Note 3/INTP2 P06/INTP3 P40/SI00 P41/SO00 P42/SCK00 P30/TXD0 P31/RXD0 P32/ASCK0 P33/TI000/TO00/TIP00Note 4/TOP00Note 4 P34/TI001/TIP01Note 4/TOP01Note 4 P35/TI010/TO01 P36 P37 EVSS EVDD P38/SDA0Note 5 P39/SCL0Note 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 P76/ANI6 P77/ANI7 P78/ANI8 P79/ANI9 P710/ANI10 P711/ANI11 P712/ANI12 P713/ANI13 P714/ANI14 P715/ANI15 PDH7/A23 PDH6/A22 PDH5/A21 PDH4/A20 PDH3/A19 PDH2/A18 PDH1/A17 PDH0/A16 PDL15/AD15 PDL14/AD14 PDL13/AD13 PDL12/AD12 PDL11/AD11 PDL10/AD10 PDL9/AD9 PDL8/AD8 PDL7/AD7 PDL6/AD6 PDL5/AD5/FLMD1Note 1 PDL4/AD4 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PDL3/AD3 PDL2/AD2 PDL1/AD1 PDL0/AD0 BVDD BVSS PCT7 PCT6/ASTB PCT5 PCT4/RD PCT3 PCT2 PCT1/WR1 PCT0/WR0 PCS7 PCS6 PCS5 PCS4 PCM5 PCM4 PCM3/HLDRQ PCM2/HLDAK PCM1/CLKOUT PCM0/WAIT PCS3/CS3 PCS2/CS2 PCS1/CS1 PCS0/CS0 PCD3 PCD2 PCD1 PCD0 P915/A15/INTP6 P914/A14/INTP5 P913/A13/INTP4 P912/A12/SCKA1 Notes 1. IC pin: VPP pin: Connect directly to VSS (PD703216, 703216Y, 703217, 703217Y). Connect to VSS in normal operation mode (PD70F3217, 70F3217Y). 70F3218HY). FLMD0 pin: Connect to VSS in normal operation mode (PD70F3217H, 70F3217HY, 70F3218H, FLMD1 pin: Used only in the PD70F3217H, 70F3217HY, 70F3218H, and 70F3218HY. 2. When using a regulator, connect the REGC pin to VSS via a 10 F capacitor. When not using a regulator, connect the REGC pin directly to VDD. 3. In the PD70F3218H and 70F3218HY, care must be exercised in processing the P05 pin when reset is released. For details, refer to 4.3.1 (5) Cautions. 4. The TIP00, TOP00, TIP01, and TOP01 pins can be used only in the PD70F3218H, and 70F3218HY. 5. The SCL0, SDA0, SCL1, and SDA1 pins can be used only in the PD703216Y, 703217Y, 70F3217Y, 70F3217HY, and 70F3218HY. Caution Make EVDD the same potential as VDD. BVDD can be used when VDD = EVDD BVDD. User's Manual U16889EJ1V0UD P50/TI011/RTP00/KR0 P51/TI50/RTP01/KR1 P52/TO50/RTP02/KR2 P53/SIA0/RTP03/KR3 P54/SOA0/RTP04/KR4 P55/SCKA0/RTP05/KR5 P60/RTP10 P61/RTP11 P62/RTP12 P63/RTP13 P64/RTP14 P65/RTP15 P66/SI02 P67/SO02 P68/SCK02 P69/TI040 P610/TI041 P611/TO04 P612/TI050 P613/TI051/TO05 P614 P615 P80/RXD2/SDA1Note 5 P81/TXD2/SCL1Note 5 P90/A0/TXD1/KR6 P91/A1/RXD1/KR7 P92/A2/TI020/TO02 P93/A3/TI021 P94/A4/TI030/TO03 P95/A5/TI031 P96/A6/TI51/TO51 P97/A7/SI01 P98/A8/SO01 P99/A9/SCK01 P910/A10/SIA1 P911/A11/SOA1 29 CHAPTER 1 INTRODUCTION Pin identification A0 to A23: AD0 to AD15: ANI0 to ANI15: ANO0, ANO1: ASCK0: ASTB: AVREF0, AVREF1: AVSS: BVDD: BVSS: CLKOUT: CS0 to CS3: EVDD: EVSS: FLMD0, FLMD1 HLDAK: HLDRQ: IC: INTP0 to INTP6: KR0 to KR7: NMI: P00 to P06: P10, P11: P30 to P39: P40 to P42: P50 to P55: P60 to P615: P70 to P715: P80, P81: P90 to P915: PCD0 to PCD3: PCM0 to PCM5: PCS0 to PCS7: PCT0 to PCT7: PDH0 to PDH7: PDL0 to PDL15: Address bus Address/data bus Analog input Analog output Asynchronous serial clock Address strobe Analog reference voltage Ground for analog Power supply for bus interface Ground for bus interface Clock output Chip select Power supply for port Ground for port Flash programming mode Hold acknowledge Hold request Internally connected External interrupt input Key return Non-maskable interrupt request Port 0 Port 1 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port CD Port CM Port CS Port CT Port DH Port DL RD: REGC: RESET: RTP00 to RTP05, RTP10 to RTP15: RXD0 to RXD2: SCK00 to SCK02, SCKA0, SCKA1: SCL0, SCL1: SDA0, SDA1: SI00 to SI02, SIA0, SIA1: SO00 to SO02, SOA0, SOA1: TI000, TI001, TI010, TI011, TI020, TI021, TI030, TI031, TI040, TI041, TI050, TI051, TI50, TI51, TIP00, TIP01: TO00 to TO05, TO50, TO51, TOH0, TOH1, TOP00, TOP01: TXD0 to TXD2: VDD: VPP: VSS: WAIT: WR0: WR1: X1, X2: XT1, XT2: Timer output Transmit data Power supply Programming power supply Ground Wait Lower byte write strobe Upper byte write strobe Crystal for main clock Crystal for subclock Timer input Serial output Serial input Serial clock Serial clock Serial data Real-time output port Receive data Read strobe Regulator control Reset 30 User's Manual U16889EJ1V0UD CHAPTER 1 INTRODUCTION 1.6 Function Block Configuration (1) Internal block diagram NMI INTP0 to INTP6 TI000, TI001, TI010, TI011, TI020, TI021, TI030, TI031, TI040, TI041, TI050, TI051 TO00 to TO05 TIP00, TIP01Note 3 TOP00, TOP01Note 3 TI50, TI51 TO50, TO51 INTC ROM 16-bit timer/event counter 0: 6 ch 16-bit timer/ event counter PNote 3: 1 ch 8-bit timer/event counter 5: 2 ch 8-bit timer H: 2 ch Note 1 PC 32-bit barrel shifter System registers General-purpose registers 32 bits x 32 CPU Instruction queue Multiplier 16 x 16 32 BCU ALU HLDRQ HLDAK ASTB RD WAIT WR0, WR1 CS0 to CS3 A0 to A23 AD0 to AD15 RAM Note 2 ROM correction TOH0, TOH1 SO00 to SO02 SI00 to SI02 SCK00 to SCK02 SOA0, SOA1 SIA0, SIA1 SCKA0, SCKA1 SDA0, SDA1Note 4 SCL0, SCL1Note 4 TXD0 to TXD2 RXD0 to RXD2 ASCK0 CSI0: 3 ch Port D/A converter A/D converter CLKOUT PLL CG X1 X2 XT1 XT2 RESET PDL0 to PDL15 PDH0 to PDH7 PCT0 to PCT7 PCS0 to PCS7 PCM0 to PCM5 PCD0 to PCD3 P90 to P915 P80, P81 P70 to P715 P60 to P615 P50 to P55 P40 to P42 P30 to P39 P10, P11 P00 to P06 CSIA: 2 ch IC 2 Note 4 : 2 ch UART: 3 ch Regulator REGC Watchdog timer: 2 ch RTP00 to RTP05, RTP10 to RTP15 Key interrupt function Watch timer KR0 to KR7 RTO: 2 ch Notes 1. PD703216, 703216Y: 96 KB (mask ROM) 2. 3. 4. 5. PD703217, 703217Y: 128 KB (mask ROM) PD70F3217, 70F3217Y, 70F3217H, 70F3217HY: 128 KB (flash memory) PD70F3218H, 70F3218HY: 256 KB (flash memory) PD703216, 703216Y, 703217, 703217Y, 70F3217, 70F3217Y, 70F3217H, 70F3217HY: 6 KB PD70F3218H, 70F3218HY: 16 KB Only in the PD70F3218H, 70F3218HY Only in the PD703216Y, 703217Y, 70F3217Y, 70F3217HY, 70F3218HY IC: PD703216, 703216Y, 703217, 703217Y VPP: PD70F3217, 70F3217Y FLMD0, FLMD1: PD70F3217H, 70F3217HY, 70F3218H, 70F3218HY AVREF0 AVSS ANI0 to ANI15 VDD FLMD1Note 5 BVDD BVSS EVDD EVSS VSS ANO0, ANO1 AVREF1 VPPNote 5/ICNote 5/FLMD0Note 5 User's Manual U16889EJ1V0UD 31 CHAPTER 1 INTRODUCTION (2) Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other types of instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits x 16 bits 32 bits) and a barrel shifter (32 bits) help accelerate complex processing. (b) Bus control unit (BCU) The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an internal instruction queue. (c) ROM This consists of a 256 KB, 128 KB, or 96 KB mask ROM or flash memory mapped to the address spaces from 0000000H to 003FFFFH, 0000000H to 001FFFFH, or 0000000H to 0017FFFH, respectively. ROM can be accessed by the CPU in one clock cycle during instruction fetch. (d) RAM This consists of a 16 KB or 6 KB RAM mapped to the address spaces from 3FFB000H to 3FFEFFFH or 3FFD800H to 3FFEFFFH. RAM can be accessed by the CPU in one clock cycle during data access. (e) Interrupt controller (INTC) This controller handles hardware interrupt requests (NMI, INTP0 to INTP6) from on-chip peripheral hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed servicing control can be performed. (f) Clock generator (CG) A main clock oscillator and subclock oscillator are provided and generate the main clock oscillation frequency (fX) and subclock frequency (fXT), respectively. There are two modes: In the clock-through mode, fX is used as the main clock frequency (fXX) as is. In the PLL mode, fX is used multiplied by 4. The CPU clock frequency (fCPU) can be selected from among fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, and fXT. (g) Timer/counter Six 16-bit timer/event counter 0 channels, one 16-bit timer/event counter P channelNote, and two 8-bit timer/event counter 5 channels are incorporated, enabling measurement of pulse intervals and frequency as well as programmable pulse output. Two 8-bit timer/event counter 5 channels can be connected in cascade to configure a 16-bit timer. Two 8-bit timer H channels enabling programmable pulse output are provided on chip. Note PD70F3218H, 70F3218HY only 32 User's Manual U16889EJ1V0UD CHAPTER 1 INTRODUCTION (h) Watch timer This timer counts the reference time (0.5 seconds) for counting the clock from the subclock (32.768 kHz) or fBRG (32.768 kHz) from the clock generator. At the same time, the watch timer can be used as an interval timer. (i) Watchdog timer Two watchdog timer channels are provided on chip to detect program loops and system abnormalities. Watchdog timer 1 can be used as an interval timer. When used as a watchdog timer, it generates a nonmaskable interrupt request signal (INTWDT1) or system reset signal (WDTRES1) after an overflow occurs. When used as an interval timer, it generates a maskable interrupt request signal (INTWDTM1) after an overflow occurs. Watchdog timer 2 operates by default following reset release. It generates a non-maskable interrupt request signal (INTWDT2) or system reset signal (WDTRES2) after an overflow occurs. (j) Serial interface (SIO) The V850ES/KJ1 includes four kinds of serial interfaces: an asynchronous serial interface (UARTn), a clocked serial interface (CSI0n), a clocked serial interface with an automatic transmit/receive function (CSIAm), and an I2C bus interface (I2Cm). The PD703216, 703217, 70F3217, 70F3217H, and 70F3218H can simultaneously use up to eight channels, and the PD703216Y, 703217Y, 70F3217Y, 70F3217HY, and 70F3218HY up to nine channels. For UARTn, data is transferred via the TXDn and RXDn pins. For CSI0n, data is transferred via the SO0n, SI0n, and SCK0n pins. For CSIAm, data is transferred via the SOAm, SIAm, and SCKAm pins. For I2Cm, data is transferred via the SDAm and SCLm pins. I2Cm is provided only in the PD703216Y, 703217Y, 70F3217Y, 70F3217HY, and 70F3218HY. Remark n = 0 to 2 m = 0, 1 (k) A/D converter This high-speed, high-resolution 10-bit A/D converter includes 16 analog input pins. performed using the successive approximation method. (l) D/A converter Two 8-bit resolution D/A converter channels are included on chip. The D/A converter uses the R-2R ladder method. (m) ROM correction This function is used to replace part of a program in the mask ROM with that contained in the internal RAM. Up to four correction addresses can be specified. (n) Key interrupt function A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input pins. Conversion is User's Manual U16889EJ1V0UD 33 CHAPTER 1 INTRODUCTION (o) Real-time output function This function transfers 6-bit data set beforehand to output latches upon occurrence of a timer compare register match signal. A 2-channel 6-bit data real-time output function is provided on chip. (p) Ports As shown below, the following ports have general-purpose port functions and control pin functions. Port P0 P1 P3 P4 P5 P6 P7 P8 P9 PCD PCM PCS PCT PDH PDL I/O 7-bit I/O 2-bit I/O 10-bit I/O 3-bit I/O 6-bit I/O 16-bit I/O 16-bit input 2-bit I/O 16-bit I/O 4-bit I/O 6-bit I/O 8-bit I/O 8-bit I/O 8-bit I/O 16-bit I/O External bus control signal Chip select output External bus control signal External address bus External address/data bus Alternate Function NMI, external interrupt, timer output D/A converter analog output Serial interface, timer I/O Serial interface Serial interface, timer I/O, key interrupt function, real-time output function Serial interface, timer I/O, real-time output function A/D converter analog input Serial interface External address bus, serial interface, timer I/O, external interrupt, key interrupt function - 34 User's Manual U16889EJ1V0UD CHAPTER 1 INTRODUCTION 1.7 Overview of Functions Part Number Internal memory ROM PD703216/ PD703216Y 96 KB PD703217/ PD703217Y 128 KB PD70F3217/ PD70F3217Y 128 KB (two-power flash memory) 6 KB 64 bytes 64 MB 15 MB PD70F3217H/ PD70F3217HY 128 KB (single-power flash memory) PD70F3218H/ PD70F3218HY 256 KB (single-power flash memory) 16 KB High-speed RAM Buffer RAM Memory space Logical space External memory area External bus interface Address bus: 24 bits Data bus: 8/16 bits Multiplex bus mode/separate bus mode 32 bits x 32 registers Ceramic/crystal/external clock When PLL not used When PLL used REGC pin connected directly to VDD 2 to 10 MHzNote 1: 2.7 to 5.5 V Standard products, (A) grade products: 2 to 5 MHz: 4.5 to 5.5 V, 2 to 4 MHz: 4.0 to 5.5 V, 2 to 2.5 MHz: 2.7 to 5.5 V (A1) grade products: 2 to 5 MHz: 4.5 to 5.5 V, 2 to 4 MHz: 4.0 to 5.5 V, 2 to 3 MHz: 3.5 to 5.5 V (A2) grade products: 2 to 4 MHz: 4.0 to 5.5 V, 2 to 3 MHz: 3.5 to 5.5 V Standard products, (A) grade products, (A1) grade products, (A2) grade products: 2 to 4 MHz: 4.0 to 5.5 V Crystal/external clock (32.768 kHz) 50 ns (When main clock operated at (fXX) = 20 MHz) 32 x 32 = 64: 200 to 250 ns (at 20 MHz) 32 x 32 + 32 = 32: 300 ns (at 20 MHz) 16 x 16 = 32: 50 to 100 ns (at 20 MHz) 16 x 16 + 32 = 32: 150 ns (at 20 MHz) 128 * Input: 16 * I/O: 112 (among these, N-ch open-drain output selectable: 6, fixed to N-ch open-drain output: 12) 16-bit timer/event counter 0: 6 channels 8-bit timer/event counter 5: 2 channels (16-bit timer/event counter: usable as 1 channel) 8-bit timer H: 2 channels Watch timer: 1 channel 8-bit interval timer: 1 channel Watchdog timer: 2 channels 2 channels: 4 bits x 1, 2 bits x 1, or 6 bits x 1 10-bit resolution x 16 channels 8-bit resolution x 2 channels CSI: 3 channels CSIA (with automatic transmit/receive function): 2 channels UART: 3 channels/2 channelsNote 2 UART/I2C bus: 1 channelNote 2 I2C bus: 1 channelNote 2 Dedicated baud rate generator: 3 channels External: 9 (9)Note 3, internal: 38/40Note 2 STOP/IDLE/HALT Standard products, (A) grade products: 4.5 to 5.5 V (at 20 MHz)/4.0 to 5.5 V (at 16 MHz)/2.7 to 5.5 V (at 10 MHz) (A1) grade products (mask version only): 4.5 to 5.5 V (at 20 MHz)/4.0 to 5.5 V (at 16 MHz)/3.5 to 5.5 V (at 12 MHz) (A2) grade products (mask version only): 4.0 to 5.5 V (at 16 MHz)/3.5 to 5.5 V (at 12 MHz) 144-pin plastic LQFP (fine pitch) (20 x 20 mm) External: 9 (9)Note 3, internal: 41/43Note 2 16-bit timer/event counter P: 1 channel General-purpose registers Main clock (oscillation frequency) 10 F capacitor connected to REGC pin Subclock (oscillation frequency) Minimum instruction execution time DSP function I/O ports Timer Real-time output port A/D converter D/A converter Serial interface Interrupt sources Power save function Operating supply voltage Package Notes 1. In the PD70F3217H, 70F3217HY, 70F3218H, 70F3218HY: 2 to 8 MHz (these values may change after evaluation) 2. Only in products with an I2C bus (Y products). 3. The figure in parentheses indicates the number of external interrupts for which STOP mode can be released. User's Manual U16889EJ1V0UD 35 CHAPTER 2 PIN FUNCTIONS The names and functions of the pins of the V850ES/KJ1 are described below, divided into port pins and non-port pins. The pin I/O buffer power supplies are divided into three systems; AVREF0/AVREF1, BVDD, and EVDD. The relationship between these power supplies and the pins is shown below. Table 2-1. Pin I/O Buffer Power Supplies Power Supply AVREF0 AVREF1 BVDD EVDD Port 7 Port 1 Ports CD, CM, CS, CT, DH, DL RESET, ports 0, 3 to 6, 8, 9 Corresponding Pins 2.1 List of Pin Functions (1) Port pins (1/4) Pin Name Pin No. P00 P01 P02 P03 P04 P05 P06 P10 P11 P30 P31 P32 P33 Note 1 I/O I/O Pull-up Resistor Yes Port 0 I/O port Function TOH0 TOH1 NMI INTP0 INTP1 INTP2 INTP3 Alternate Function 6 7 17 18 19 20 21 3 4 25 26 27 28 Input/output can be specified in 1-bit units. I/O Yes Port 1 I/O port Input/output can be specified in 1-bit units. ANO0 ANO1 TXD0 RXD0 ASCK0 TI000/TO00/TIP00 TOP00 Note 3 Note 3 Note 3 I/O Yes Port 3 I/O port Input/output can be specified in 1-bit units. P36 to P39 are fixed to N-ch open-drain output. / Note 3 P34 P35 P36 P37 P38 P39 29 30 31 32 35 36 No Note 2 TI001/TIP01 TI010/TO01 /TOP01 - - SDA0 SCL0 Note 4 Note 4 Notes 1. In the PD70F3218H and 70F3218HY, care must be exercised in processing the P05 pin when reset is released. For details, refer to 4.3.1 (5) Cautions. 2. An on-chip pull-up resistor can be provided by a mask option (only in the mask ROM versions). 3. Only in the PD70F3218H, 70F3218HY 4. Only in products with an I2C bus (Y products) 36 User's Manual U16889EJ1V0UD CHAPTER 2 PIN FUNCTIONS (2/4) Pin Name Pin No. P40 P41 P42 P50 P51 P52 P53 P54 P55 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P610 P611 P612 P613 P614 P615 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P710 P711 P712 22 23 24 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 144 143 142 141 140 139 138 137 136 135 134 133 132 Input No Port 7 Input port ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 ANI12 No Note I/O I/O Pull-up Resistor Yes Port 4 I/O port Function SI00 SO00 Alternate Function Input/output can be specified in 1-bit units. P41 and P42 can be specified as N-ch opendrain output in 1-bit units. I/O Yes Port 5 I/O port Input/output can be specified in 1-bit units. P54 and P55 can be specified as N-ch opendrain output in 1-bit units. SCK00 TI011/RTP00/KR0 TI50/RTP01/KR1 TO50/RTP02/KR2 SIA0/RTP03/KR3 SOA0/RTP04/KR4 SCKA0/RTP05/KR5 I/O Yes Port 6 I/O port Input/output can be specified in 1-bit units. P67 and P68 can be specified as N-ch opendrain output in 1-bit units. P614 and P615 are fixed to N-ch open-drain output. RTP10 RTP11 RTP12 RTP13 RTP14 RTP15 SI02 SO02 SCK02 TI040 TI041 TO04 TI050 TI051/TO05 - - Note An on-chip pull-up resistor can be provided by a mask option (only in the mask ROM versions). User's Manual U16889EJ1V0UD 37 CHAPTER 2 PIN FUNCTIONS (3/4) Pin Name Pin No. P713 P714 P715 P80 P81 131 130 129 59 60 I/O Yes Port 8 I/O port Input/output can be specified in 1-bit units. N-ch open-drain output can be specified in 1bit units. Port 9 I/O port Input/output can be specified in 1-bit units. P98, P99, P911, and P912 can be specified as N-ch open-drain output in 1-bit units. I/O Input Pull-up Resistor No Port 7 Input port Function ANI13 ANI14 ANI15 RXD2/SDA1 TXD2/SCL1 Note Alternate Function Note P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P910 P911 P912 P913 P914 P915 PCD0 PCD1 PCD2 PCD3 PCM0 PCM1 PCM2 PCM3 PCM4 PCM5 PCS0 PCS1 PCS2 PCS3 PCS4 PCS5 PCS6 PCS7 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 85 86 87 88 89 90 81 82 83 84 91 92 93 94 I/O Yes A0/TXD1/KR6 A1/RXD1/KR7 A2/TI020/TO02 A3/TI021 A4/TI030/TO03 A5/TI031 A6/TI51/TO51 A7/SI01 A8/SO01 A9/SCK01 A10/SIA1 A11/SOA1 A12/SCKA1 A13/INTP4 A14/INTP5 A15/INTP6 I/O No Port CD I/O port Input/output can be specified in 1-bit units. - - - - I/O No Port CM I/O port Input/output can be specified in 1-bit units. WAIT CLKOUT HLDAK HLDRQ - - I/O No Port CS I/O port Input/output can be specified in 1-bit units. CS0 CS1 CS2 CS3 - - - - Note Only in products with an I C bus (Y products) 2 38 User's Manual U16889EJ1V0UD CHAPTER 2 PIN FUNCTIONS (4/4) Pin Name Pin No. PCT0 PCT1 PCT2 PCT3 PCT4 PCT5 PCT6 PCT7 PDH0 PDH1 PDH2 PDH3 PDH4 PDH5 PDH6 PDH7 PDL0 PDL1 PDL2 PDL3 PDL4 PDL5 PDL6 PDL7 PDL8 PDL9 PDL10 PDL11 PDL12 PDL13 PDL14 PDL15 95 96 97 98 99 100 101 102 121 122 123 124 125 126 127 128 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 I/O No Port DL I/O port Input/output can be specified in 1-bit units. I/O No Port DH I/O port Input/output can be specified in 1-bit units. A16 A17 A18 A19 A20 A21 A22 A23 AD0 AD1 AD2 AD3 AD4 AD5/FLMD1 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 Note I/O I/O Pull-up Resistor No Port CT Function WR0 WR1 I/O port Input/output can be specified in 1-bit units. Alternate Function - - RD - ASTB - Note Only in the PD70F3217H, 70F3217HY, 70F3218H, 70F3218HY User's Manual U16889EJ1V0UD 39 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/5) Pin Name Pin No. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 121 122 123 124 125 126 127 128 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 I/O No Address/data bus for external memory Output No Address bus for external memory I/O Output Pull-up Resistor Yes Function Address bus for external memory (when using a separate bus) Alternate Function P90/TXD1/KR6 P91/RXD1/KR7 P92/TI020/TO02 P93/TI021 P94/TI030/TO03 P95/TI031 P96/TI51/TO51 P97/SI01 P98/SO01 P99/SCK01 P910/SIA1 P911/SOA1 P912/SCKA1 P913/INTP4 P914/INTP5 P915/INTP6 PDH0 PDH1 PDH2 PDH3 PDH4 PDH5 PDH6 PDH7 PDL0 PDL1 PDL2 PDL3 PDL4 PDL5/FLMD1 PDL6 PDL7 PDL8 PDL9 PDL10 PDL11 PDL12 PDL13 PDL14 PDL15 Note Note Only in the PD70F3217H, 70F3217HY, 70F3218H, 70F3218HY 40 User's Manual U16889EJ1V0UD CHAPTER 2 PIN FUNCTIONS (2/5) Pin Name Pin No. ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 ANI12 ANI13 ANI14 ANI15 ANO0 ANO1 ASCK0 ASTB 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 3 4 27 101 Input Output Yes No UART0 serial clock input Address strobe signal output for external memory AVREF0 1 - - Reference voltage for A/D converter and alternate-function ports Reference voltage for D/A converter Ground potential for A/D and D/A converters Positive power supply for bus interface and alternate-function ports Ground potential for bus interface and alternate-function ports Internal system clock output Chip select output PCM1 PCS0 PCS1 PCS2 PCS3 - - - - - - Positive power supply for external Ground potential for external Flash programming mode setting pin PDL5/AD5 Output Input - No No - Bus hold acknowledge output Bus hold request input Internally connected PCM2 PCM3 - - - - - Output Yes Analog voltage output for D/A converter I/O Input Pull-up Resistor No Function Analog voltage input for A/D converter P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P710 P711 P712 P713 P714 P715 P10 P11 P32 PCT6 Alternate Function AVREF1 AVSS BVDD 5 2 104 - - - - - - - - - BVSS 103 - - - CLKOUT CS0 CS1 CS2 CS3 EVDD EVSS FLMD0 FLMD1 Note 1 86 81 82 83 84 34 33 8 110 87 88 8 Output Output No No Note 1 HLDAK HLDRQ IC Note 2 Notes 1. Only in the PD70F3217H, 70F3217HY, 70F3218H, 70F3218HY 2. Only in the mask ROM versions User's Manual U16889EJ1V0UD 41 CHAPTER 2 PIN FUNCTIONS (3/5) Pin Name Pin No. INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 KR0 KR1 KR2 KR3 KR4 KR5 KR6 KR7 NMI 18 19 20 21 74 75 76 37 38 39 40 41 42 61 62 17 Input Yes External interrupt input (non-maskable, analog noise elimination) RD REGC 99 10 Output - No - Read strobe signal output for external memory Connecting capacitor for regulator output stabilization RESET RTP00 RTP01 RTP02 RTP03 RTP04 RTP05 RTP10 RTP11 RTP12 RTP13 RTP14 RTP15 RXD0 RXD1 RXD2 14 37 38 39 40 41 42 43 44 45 46 47 48 26 62 59 Input Yes Serial receive data input for UART0 Serial receive data input for UART1 Serial receive data input for UART2 Input Output Yes - System reset input Real-time output port - P50/TI011/KR0 P51/TI50/KR1 P52/TO50/KR2 P53/SIA0/KR3 P54/SOA0/KR4 P55/SCKA0/KR5 P60 P61 P62 P63 P64 P65 P31 P91/A1/KR7 P80/SDA1 Note I/O Input Pull-up Resistor Yes Function External interrupt request input (maskable, analog noise elimination) P03 P04 P05 P06 Alternate Function P913/A13 P914/A14 P915/A15 Input Yes Key return input P50/TI011/RTP00 P51/TI50/RTP01 P52/TO50/RTP02 P53/SIA0/RTP03 P54/SOA0/RTP04 P55/SCKA0/RTP05 P90/A0/TXD1 P91/A1/RXD1 P02 PCT4 - Note Only in products with an I2C bus (Y products) 42 User's Manual U16889EJ1V0UD CHAPTER 2 PIN FUNCTIONS (4/5) Pin Name Pin No. SCK00 SCK01 SCK02 SCKA0 SCKA1 SCL0 Note 1 I/O I/O Pull-up Resistor Yes Function Serial clock I/O for CSI00 to CSI02, CSIA0, CSIA1 N-ch open-drain output can be specified in 1bit units. P42 Alternate Function 24 70 51 42 73 36 P99/A9 P68 P55/RTP05/KR5 P912/A12 I/O No Note 2 Serial clock I/O for I C0 Fixed to N-ch open-drain output 2 2 P39 SCL1 Note 1 60 Yes Note 2 Serial clock I/O for I C1 N-ch open-drain output can be specified 2 P81/TXD2 SDA0 Note 1 35 I/O No Serial transmit/receive data I/O for I C0 Fixed to N-ch open-drain output 2 P38 SDA1 Note 1 59 Yes Serial transmit/receive data I/O for I C1 N-ch open-drain output can be specified P80/RXD2 SI00 SI01 SI02 SIA0 SIA1 SO00 SO01 SO02 SOA0 SOA1 TI000 TI001 TI010 TI011 TI020 TI021 TI030 TI031 TI040 TI041 TI050 TI051 TI50 TI51 TIP00 Note 3 22 68 49 40 71 23 69 50 41 72 28 29 30 37 63 64 65 66 52 53 55 56 38 67 28 Input Yes Serial receive data input for CSI00 Serial receive data input for CSI01 Serial receive data input for CSI02 Serial receive data input for CSIA0 Serial receive data input for CSIA1 P40 P97/A7 P66 P53/RTP03/KR3 P910/A10 P41 P98/A8 P67 P54/RTP04/KR4 P911/A11 Output Yes Serial transmit data output for CSI00 to CSI02, CSIA0, CSIA1 N-ch open-drain output can be specified in 1bit units. Input Yes Capture trigger input/external event input for TM00 P33/TO00/TIP00 Capture trigger input for TM00 P34/TIP01 Note 3 Note 3 /TOP00 Note 3 Note 3 /TOP01 Capture trigger input/external event input for TM01 P35/TO01 Capture trigger input for TM01 P50/RTP00/KR0 Capture trigger input/external event input for TM02 P92/A2/TO02 Capture trigger input for TM02 P93/A3 Capture trigger input/external event input for TM03 P94/A4/TO03 Capture trigger input for TM03 P95/A5 Capture trigger input/external event input for TM04 P69 Capture trigger input for TM04 P610 Capture trigger input/external event input for TM05 P612 Capture trigger input for TM05 External event input for TM50 External event input for TM51 Capture trigger input/external event input/external clock input for TMP0 P613/TO05 P51/RTP01/KR1 P96/A6/TO51 P33/TI000/TO00/TOP00 Note 3 Note 3 TIP01 Note 3 29 Capture trigger input P34/TI001/TOP01 Notes 1. Only in products with an I2C bus (Y products) 2. An on-chip pull-up resistor can be provided by a mask option (only in the mask ROM versions). 3. Only in the PD70F3218H, 70F3218HY User's Manual U16889EJ1V0UD 43 CHAPTER 2 PIN FUNCTIONS (5/5) Pin Name Pin No. TO00 TO01 TO02 TO03 TO04 TO05 TO50 TO51 TOH0 TOH1 TOP00 TOP01 TXD0 TXD1 TXD2 VDD VPP Note 3 Note 1 I/O Output Pull-up Resistor Yes Function Timer output for TM00 Timer output for TM01 Timer output for TM02 Timer output for TM03 Timer output for TM04 Timer output for TM05 Timer output for TM50 Timer output for TM51 Timer output for TMH0 Timer output for TMH1 Timer output for TMP0 Alternate Function P33/TI000/TIP00 P35/TI010 P92/A2/TI020 P94/A4/TI030 P611 P613/TI051 P52/RTP02/KR2 P96/A6/TI51 P00 P01 P33/TI000/TO00/TIP00 P34/TI001/TIP01 Note 1 Note 1 Note 1 28 30 63 65 54 56 39 67 6 7 28 29 25 61 60 9 8 /TOP00 Note 1 Note 1 Output Yes Serial transmit data output for UART0 Serial transmit data output for UART1 Serial transmit data output for UART2 P30 P90/A0/KR6 P81/SCL1 Note 2 - - - - Positive power supply pin for internal High-voltage application pin for program write/verify - - VSS WAIT WR0 WR1 X1 X2 XT1 XT2 11 85 95 96 12 13 15 16 - Input Output No No - Ground potential for internal External wait input Write strobe for external memory (lower 8 bits) Write strobe for external memory (higher 8 bits) PCM0 PCT0 PCT1 - Input - Input - No No No No Connecting resonator for main clock - - Connecting resonator for subclock - - Notes 1. Only in the PD70F3218H, 70F3218HY 2. Only in products with an I C bus (Y products) 3. Only in the PD70F3217, 70F3217Y 2 44 User's Manual U16889EJ1V0UD CHAPTER 2 PIN FUNCTIONS 2.2 Pin Status The address bus becomes undefined during accesses to the internal RAM and ROM. The data bus goes into the high-impedance state without data output. The external bus control signal becomes inactive. During peripheral I/O access, the address bus outputs the addresses of the on-chip peripheral I/Os that are accessed. The data bus goes into the high-impedance state without data output. The external bus control signal becomes inactive. Table 2-2. Pin Operation Status in Operation Modes Operating Status Pin AD0 to AD15 (PDL0 to PDL15) A0 to A15 (P90 to P915) A16 to A23 (PDH0 to PDH7) WAIT (PCM0) CLKOUT (PCM1) CS0 to CS3 (PCS0 to PCS3) WR0, WR1 (PCT0, PCT1) RD (PCT4) ASTB (PCT6) HLDAK (PCM2) HLDRQ (PCM3) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Note 3 Undefined Note 4 Reset Note 1 HALT Mode IDLE Mode/ STOP Mode Hi-Z Hi-Z Hi-Z - L H H H H H - Idle State Note 2 Bus Hold Held Held Held - Operating Held H H H H - Hi-Z Hi-Z Hi-Z - Operating Hi-Z Hi-Z Hi-Z Hi-Z L Operating Undefined - Operating H H H H Operating Operating Notes 1. Since the bus control pin is also used as a port pin, it is initialized to the port mode (input) after reset. 2. The pin statuses in the idle state inserted after the T3 state in the multiplex bus mode and after the T2 state in the separate bus mode are listed. 3. In separate bus mode: Hi-Z In multiplex bus mode: Undefined 4. Only in separate bus mode Remark Hi-Z: High impedance H: L: -: High-level output Low-level output Input without sampling (input acknowledgment not possible) User's Manual U16889EJ1V0UD 45 CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins (1/3) Pin P00 P01 P02 P03 to P06 P10 P11 P30 P31 P32 P33 P34 P35 P36, P37 P38 P39 P40 P41 P42 P50 P51 P52 P53 P54 P55 P60 to P65 P66 P67 P68 P69 P610 P611 P612 P613 P614, P615 P70 to P715 ANI0 to ANI15 SDA0 SCL0 SI00 SO00 SCK00 TI011/RTP00/KR0 TI50/RTP01/KR1 TO50/RTP02/KR2 SIA0/RTP03/KR3 SOA0/RTP04/KR4 SCKA0/RTP05/KR5 RTP10 to RTP15 SI02 SO02 SCK02 TI040 TI041 TO04 TI050 TI051/TO05 - Note 2 Alternate Function TOH0 TOH1 NMI INTP0 to INTP3 ANO0 ANO1 TXD0 RXD0 ASCK0 TI000/TO00/TIP00 TI001/TIP01 TI010/TO01 - Note 1 Note 1 Pin No. 6 7 17 18 to 21 3 4 25 26 27 I/O Circuit Type 5-A Recommended Connection Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. 5-W 12-B Input: Independently connect to AVREF1 or AVSS via a resistor. Output: Leave open. 5-A 5-W Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open /TOP00 Note 1 Note 1 28 29 30 31, 32 35 36 22 23 24 37 38 39 40 41 42 43 to 48 49 50 51 52 53 54 55 56 57, 58 114 to 129 13-AH 9-C Connect to AVREF0 or AVSS. 5-A 5-W 5-A 5-W 10-E 10-F 5-W 10-A 5-W 10-E 10-F 8-A 13-AH 13-AE /TOP01 Note 2 Notes 1. Only in the PD70F3218H, 70F3218HY 2. Only in products with an I2C bus (Y products) 46 User's Manual U16889EJ1V0UD CHAPTER 2 PIN FUNCTIONS (2/3) Pin P80 P81 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P910 P911 P912 P913 P914, P915 PCD0 to PCD3 PCM0 PCM1 PCM2 PCM3 PCM4,PCM5 PCS0, PCS1 PCS2, PCS3 PCS4 to PCS7 PCT0 PCT1 PCT2, PCT3 PCT4 PCT5 PCT6 PCT7 PDL0 to PDL4 PDL5 AD0 to AD4 AD5/FLMD1 Note Alternate Function RXD2/SDA1 TXD2/SCL1 Note Pin No. 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75, 76 77 to 80 85 86 87 88 I/O Circuit Type 10-F Recommended Connection Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open. Note A0/TXD1/KR6 A1/RXD1/KR7 A2/TI020/TO02 A3/TI021 A4/TI030/TO03 A5/TI031 A6/TI51/TO51 A7/SI01 A8/SO01 A9/SCK01 A10/SIA1 A11/SOA1 A12/SCKA1 A13/INTP4 A14/INTP5, A15/INTP6 - WAIT CLKOUT HLDAK HLDRQ - CS0, CS1 CS2, CS3 - WR0 WR1 - RD - ASTB - 8-A 5-W 8-A 5-W 8-A 5-W 10-E 10-F 5-W 10-E 10-F 5-W 5 5 Input: Independently connect to BVDD or BVSS via a resistor. Output: Leave open. 89, 90 81, 82 83, 84 91 to 94 95 96 97, 98 99 100 101 102 105 to 109 110 111 to 120 121 to 128 5 - - - Directly connect to VDD. Directly connect to VDD. - 5 5 5 PDL6 to PDL15 AD6 to AD15 PDH0 to PDH7 AVREF0 AVREF1 AVSS A16 to A23 - - - 1 5 2 Note Only in the PD70F3217H, 70F3217HY, 70F3218H, 70F3218HY User's Manual U16889EJ1V0UD 47 CHAPTER 2 PIN FUNCTIONS (3/3) Pin BVDD BVSS EVDD EVSS FLMD0 IC Note 2 Note 1 Alternate Function - - - - - - Pin No. 104 103 34 33 8 8 I/O Circuit Type - - - - - - Recommended Connection - - - - Connect to VSS in normal operation mode. Directly connect to EVSS or VSS or pull down with a 10 k resistor. RESET VPP Note 3 - - 14 8 2 - - Directly connect to EVSS or VSS or pull down with a 10 k resistor. VDD VSS X1 X2 XT1 XT2 - - - - - - 9 11 12 13 15 16 - - - - 16 16 - - - - Directly connect to VSS Leave open. Note 4 . Notes 1. Only in the PD70F3217H, 70F3217HY, 70F3218H, 70F3218HY 2. Only in the PD703216, 703216Y, 703217, 703217Y 3. Only in the PD70F3217, 70F3217Y 4. Be sure to set the PSMR.XTSTP bit to 1 when this pin is not used. 48 User's Manual U16889EJ1V0UD CHAPTER 2 PIN FUNCTIONS 2.4 Pin I/O Circuits (1/2) Type 2 Type 8-A Pull-up enable VDD IN Data P-ch IN/OUT Schmitt-triggered input with hysteresis characteristics Output disable N-ch VDD P-ch Type 5 VDD Data Type 9-C P-ch P-ch IN/OUT IN N-ch + - Comparator Output disable N-ch AVREF0 (threshold voltage) Input enable Input enable Type 5-A VDD Type 10-A Pull-up enable VDD Data IN/OUT P-ch VDD P-ch Pull-up enable Data P-ch VDD P-ch Output disable Input enable Type 5-W Pull-up enable N-ch Open drain Output disable IN/OUT N-ch VDD P-ch VDD Type 10-E Pull-up enable VDD Data P-ch VDD P-ch Data P-ch IN/OUT Open drain Output disable IN/OUT N-ch Output disable N-ch Input enable Input enable User's Manual U16889EJ1V0UD 49 CHAPTER 2 PIN FUNCTIONS (2/2) Type 10-F Pull-up enable VDD Data Open drain Output disable P-ch IN/OUT N-ch RD P-ch VDD P-ch Data Output disable VSS VDD Type 13-AH Mask option IN/OUT N-ch VDD Input enable Type 12-B Pull-up enable AVREF1 Data Output disable P-ch IN/OUT N-ch AVSS AVREF1 P-ch Type 16 Port read Medium-voltage input buffer Feedback cut-off P-ch Input enable P-ch Analog output voltage N-ch XT1 XT2 Type 13-AE VDD Mask option Data Output disable N-ch VSS Input enable IN/OUT Remark Read VDD as EVDD or BVDD. Also, read VSS as EVSS or BVSS. 50 User's Manual U16889EJ1V0UD CHAPTER 3 CPU FUNCTIONS The CPU of the V850ES/KJ1 is based on the RISC architecture and executes most instructions in one clock cycle by using 5-stage pipeline control. 3.1 Features Number of instructions: 83 4.5 to 5.5 V, not using regulator) 4.0 to 5.5 V, using regulator) 2.7 to 5.5 V, not using regulator) 62.5 ns (@ 16 MHz operation: 125 nsNote 2 (@ 8 MHz operation: Memory space Program (physical address) space: 64 MB linear Data (logical address) space: General-purpose registers: 32 bits x 32 Internal 32-bit architecture 5-stage pipeline control Multiply/divide instructions Saturated operation instructions 32-bit shift instruction: 1 clock Load/store instruction with long/short format Four types of bit manipulation instructions * SET1 * CLR1 * NOT1 * TST1 Notes 1. Only in the PD703216, 703216Y, 703217, 703217Y, 70F3217, 70F3217Y 2. Only in the PD70F3217H, 70F3217HY, 70F3218H, 70F3218HY (these values may change after evaluation) 4 GB linear * Memory block division function: 2 MB, 2 MB, 4 MB, 8 MB/Total of 4 blocks Minimum instruction execution time: 50.0 ns (@ 20 MHz operation: 100 nsNote 1 (@ 10 MHz operation: 2.7 to 5.5 V, not using regulator) User's Manual U16889EJ1V0UD 51 CHAPTER 3 CPU FUNCTIONS 3.2 CPU Register Set The CPU registers of the V850ES/KJ1 can be classified into two categories: a general-purpose program register set and a dedicated system register set. All the registers have 32-bit width. For details, refer to the V850ES Architecture User's Manual. (1) Program register set 31 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 (Element pointer (EP)) (Link pointer (LP)) CTBP DBPC DBPSW CTPC CTPSW PSW (Stack pointer (SP)) (Global pointer (GP)) (Text pointer (TP)) ECR FEPC FEPSW (2) System register set 0 31 EIPC EIPSW (Interrupt status saving register) (Interrupt status saving register) 0 (Zero register) (Assembler-reserved register) (NMI status saving register) (NMI status saving register) (Interrupt source register) (Program status word) (CALLT execution status saving register) (CALLT execution status saving register) (Exception/debug trap status saving register) (Exception/debug trap status saving register) (CALLT base pointer) 31 PC (Program counter) 0 52 User's Manual U16889EJ1V0UD CHAPTER 3 CPU FUNCTIONS 3.2.1 Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers, r0 to r31, are available. All of these registers can be used as a data variable or address variable. However, r0 and r30 are implicitly used by instructions and care must be exercised when using these registers. r0 always holds 0 and is used for operations that use 0 and offset 0 addressing. r30 is used as a base pointer when performing memory access with the SLD and SST instructions. Also, r1, r3 to r5, and r31 are implicitly used by the assembler and C compiler. Therefore, before using these registers, their contents must be saved so that they are not lost, and they must be restored to the registers after the registers have been used. There are cases when r2 is used by the real-time OS. If r2 is not used by the real-time OS, r2 can be used as a variable register. Table 3-1. Program Registers Name r0 r1 r2 r3 r4 r5 r6 to r29 r30 r31 PC Usage Zero register Assembler-reserved register Always holds 0 Working register for generating 32-bit immediate Operation Address/data variable register (when r2 is not used by the real-time OS to be used) Stack pointer Global pointer Text pointer Address/data variable register Element pointer Link pointer Program counter Base pointer when memory is accessed Used by compiler when calling function Holds instruction address during program execution Used to generate stack frame when function is called Used to access global variable in data area Register to indicate the start of the text area (area for placing program code) (2) Program counter (PC) This register holds the address of the instruction under execution. The lower 26 bits of this register are valid, and bits 31 to 26 are fixed to 0. If a carry occurs from bit 25 to bit 26, it is ignored. Bit 0 is fixed to 0, and branching to an odd address cannot be performed. 31 PC Fixed to 0 26 25 Instruction address under execution 10 0 After reset 00000000H User's Manual U16889EJ1V0UD 53 CHAPTER 3 CPU FUNCTIONS 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. Read from and write to system registers are performed by setting the system register numbers shown below with the system register load/store instructions (LDSR, STSR instructions). Table 3-2. System Register Numbers System Register No. System Register Name Operand Specification Enabled LDSR Instruction 0 1 2 3 4 5 6 to 15 Interrupt status saving register (EIPC) Note 1 STSR Instruction Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes No Yes No Interrupt status saving register (EIPSW) NMI status saving register (FEPC) Note 1 Note 1 NMI status saving register (FEPSW) Interrupt source register (ECR) Program status word (PSW) Note 1 Reserved numbers for future function expansion (The operation is not guaranteed if accessed.) 16 17 18 19 20 21 to 31 CALLT execution status saving register (CTPC) CALLT execution status saving register (CTPSW) Exception/debug trap status saving register (DBPC) Exception/debug trap status saving register (DBPSW) CALLT base pointer (CTBP) Reserved numbers for future function expansion (The operation is not guaranteed if accessed.) Yes Yes Yes Note 2 Yes Yes Yes Yes Yes No Yes Note 2 Yes No Notes 1. Since only one set of these registers is available, the contents of this register must be saved by the program when multiple interrupt servicing is enabled. 2. Can be accessed only during the period from the DBTRAP instruction to the DBRET instruction. Caution Even if bit 0 of EIPC, FEPC, or CTPC is set (1) by the LDSR instruction, bit 0 is ignored during return with the RETI instruction following interrupt servicing (because bit 0 of PC is fixed to 0). When setting a value to EIPC, FEPC, and CTPC, set an even number (bit 0 = 0). 54 User's Manual U16889EJ1V0UD CHAPTER 3 CPU FUNCTIONS (1) Interrupt status saving registers (EIPC, EIPSW) There are two interrupt status saving registers, EIPC and EIPSW. Upon occurrence of a software exception or a maskable interrupt, the contents of the program counter (PC) are saved to EIPC and the contents of the program status word (PSW) are saved to EIPSW (upon occurrence of a non-maskable interrupt (NMI), the contents are saved to the NMI status saving registers (FEPC, FEPSW)). The address of the next instruction following the instruction executed when a software exception or maskable interrupt occurs is saved to EIPC, except for some instructions (refer to 20.9 Period in Which Interrupts Are Not Acknowledged by CPU). The current PSW contents are saved to EIPSW. Since there is only one set of interrupt status saving registers, the contents of these registers must be saved by the program when multiple interrupt servicing is enabled. Bits 31 to 26 of EIPC and bits 31 to 8 of EIPSW are reserved (fixed to 0) for future function expansion. When the RETI instruction is executed, the values in EIPC and EIPSW are restored to the PC and PSW, respectively. 31 EIPC 26 25 (PC contents saved) 0 After reset 0xxxxxxxH (x: Undefined) 87 0 After reset 000000xxH (x: Undefined) 000000 31 EIPSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PSW contents saved) User's Manual U16889EJ1V0UD 55 CHAPTER 3 CPU FUNCTIONS (2) NMI status saving registers (FEPC, FEPSW) There are two NMI status saving registers, FEPC and FEPSW. Upon occurrence of a non-maskable interrupt (NMI), the contents of the program counter (PC) are saved to FEPC and the contents of the program status word (PSW) are saved to FEPSW. The address of the next instruction following the instruction executed when a non-maskable interrupt occurs is saved to FEPC, except for some instructions. The current PSW contents are saved to FEPSW. Since there is only one set of NMI status saving registers, the contents of these registers must be saved by the program when multiple interrupt servicing is performed. Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved (fixed to 0) for future function expansion. 31 FEPC 26 25 (PC contents saved) 0 After reset 0xxxxxxxH (x: Undefined) 87 0 After reset 000000xxH (x: Undefined) 000000 31 FEPSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PSW contents saved) (3) Interrupt source register (ECR) Upon occurrence of an interrupt or an exception, the interrupt source register (ECR) holds the source of an interrupt or an exception. The value held by ECR is the exception code coded for each interrupt source. This register is a read-only register, and thus data cannot be written to it using the LDSR instruction. 31 ECR FECC 16 15 EICC 0 After reset 00000000H Bit position 31 to 16 15 to 0 Bit name FECC EICC Description Non-maskable interrupt (NMI) exception code Exception, maskable interrupt exception code 56 User's Manual U16889EJ1V0UD CHAPTER 3 CPU FUNCTIONS (4) Program status word (PSW) The program status word (PSW) is a collection of flags that indicate the program status (instruction execution result) and the CPU status. When the contents of this register are changed using the LDSR instruction, the new contents become valid immediately following completion of LDSR instruction execution. Interrupt request acknowledgment is held pending while a write to the PSW is being executed by the LDSR instruction. Bits 31 to 8 are reserved (fixed to 0) for future function expansion. (1/2) 31 PSW RFU 876543210 NP EP ID SAT CY OV S Z After reset 00000020H Bit position 31 to 8 7 Flag name RFU NP Reserved field. Fixed to 0. Description Indicates that non-maskable interrupt (NMI) servicing is in progress. This flag is set to 1 when an NMI request is acknowledged, and disables multiple interrupts. 0: NMI servicing not in progress 1: NMI servicing in progress 6 EP Indicates that exception processing is in progress. This flag is set to 1 when an exception occurs. Moreover, interrupt requests can be acknowledged even when this bit is set. 0: Exception processing not in progress 1: Exception processing in progress 5 ID Indicates whether maskable interrupt request acknowledgment is enabled. 0: Interrupt enabled 1: Interrupt disabled Note 4 SAT Indicates that the result of executing a saturated operation instruction has overflowed and that the calculation result is saturated. Since this is a cumulative flag, it is set to 1 when the result of a saturated operation instruction becomes saturated, and it is not cleared to 0 even if the operation results of successive instructions do not become saturated. This flag is neither set nor cleared when arithmetic operation instructions are executed. 0: Not saturated 1: Saturated 3 CY Indicates whether carry or borrow occurred as the result of an operation. 0: No carry or borrow occurred 1: Carry or borrow occurred Note 2 OV Indicates whether overflow occurred during an operation. 0: No overflow occurred 1: Overflow occurred. 1 S Note Indicates whether the result of an operation is negative. 0: Operation result is positive or 0. 1: Operation result is negative. 0 Z Indicates whether operation result is 0. 0: Operation result is not 0. 1: Operation result is 0. Remark Note is explained on the following page. User's Manual U16889EJ1V0UD 57 CHAPTER 3 CPU FUNCTIONS (2/2) Note During saturated operation, the saturated operation results are determined by the contents of the OV flag and S flag. The SAT flag is set (to 1) only when the OV flag is set (to 1) during saturated operation. Operation result status SAT Maximum positive value exceeded Maximum negative value exceeded Positive (maximum value not exceeded) Negative (maximum value not exceeded) 1 1 Holds value before operation 1 1 0 Flag status OV 0 1 0 1 S Saturated operation result 7FFFFFFFH 80000000H Actual operation result (5) CALLT execution status saving registers (CTPC, CTPSW) There are two CALLT execution status saving registers, CTPC and CTPSW. When the CALLT instruction is executed, the contents of the program counter (PC) are saved to CTPC, and the program status word (PSW) contents are saved to CTPSW. The contents saved to CTPC consist of the address of the next instruction after the CALLT instruction. The current PSW contents are saved to CTPSW. Bits 31 to 26 CTPC and bits 31 to 8 of CTPSW are reserved (fixed to 0) for future function expansion. 31 CTPC 26 25 (PC contents saved) 0 After reset 0xxxxxxxH (x: Undefined) 87 0 After reset 000000xxH (x: Undefined) 000000 31 CTPSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PSW contents saved) 58 User's Manual U16889EJ1V0UD CHAPTER 3 CPU FUNCTIONS (6) Exception/debug trap status saving registers (DBPC, DBPSW) There are two exception/debug trap status saving registers, DBPC and DBPSW. Upon occurrence of an exception trap or debug trap, the contents of the program counter (PC) are saved to DBPC, and the program status word (PSW) contents are saved to DBPSW. The contents saved to DBPC consist of the address of the next instruction after the instruction executed when an exception trap or debug trap occurs. The current PSW contents are saved to DBPSW. Bits 31 to 26 of DBPC and bits 31 to 8 of DBPSW are reserved (fixed to 0) for future function expansion. 31 DBPC 26 25 (PC contents saved) 0 After reset 0xxxxxxxH (x: Undefined) 87 0 After reset 000000xxH (x: Undefined) 000000 31 DBPSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PSW contents saved) (7) CALLT base pointer (CTBP) The CALLT base pointer (CTBP) is used to specify table addresses and generate target addresses (bit 0 is fixed to 0). Bits 31 to 26 are reserved (fixed to 0) for future function expansion. 31 CTBP 26 25 (Base address) 0 0 After reset 0xxxxxxxH (x: Undefined) 000000 User's Manual U16889EJ1V0UD 59 CHAPTER 3 CPU FUNCTIONS 3.3 Operating Modes The V850ES/KJ1 has the following operating modes. (1) Normal operating mode After the system has been released from the reset state, the pins related to the bus interface are set to the port mode, execution branches to the reset entry address of the internal ROM, and instruction processing is started. (2) Flash memory programming mode This mode is valid only in flash memory versions (PD70F3217, 70F3217Y, 70F3217H, 70F3217HY, 70F3218H, and 70F3218HY). When this mode is specified, the internal flash memory can be programmed by using a flash programmer. (a) Specifying operating mode (i) PD70F3217, 70F3217Y The internal flash memory can be written or erased when 10 V 0.3 V is applied to the VPP pin. VPP 0 10 V 0.3 V VDD Operating Mode Normal operating mode Flash memory programming mode Setting prohibited (ii) PD70F3217H, 70F3217HY, 70F3218H, 70F3218HY The operating mode is specified according to the status (input level) of the FLMD0 and FLMD1 pins. In the normal operating mode, input a low level to the FLMD0 pin during the reset period. A high level is input to the FLMD0 pin by the flash programmer in the flash memory programming mode if a flash programmer is connected. In the self-programming mode, input a high level to this pin from an external circuit. Fix the specification of these pins in the application system and do not change the setting of these pins during operation. FLMD0 L H H FLMD1 x L H Operating Mode Normal operating mode Flash memory programming mode Setting prohibited Remark H: High level L: Low level x: don't care 60 User's Manual U16889EJ1V0UD CHAPTER 3 CPU FUNCTIONS 3.4 Address Space 3.4.1 CPU address space Up to 64 MB of external memory area in a linear address space (program area) of up to 16 MB, internal ROM area, and internal RAM area are supported for instruction address addressing. During operand addressing (data access), up to 4 GB of linear address space (data space) is supported. However, the 4 GB address space is viewed as 64 images of a 64 MB physical address space. In other words, the same 64 MB physical address space is accessed regardless of the value of bits 31 to 26. Figure 3-1. Address Space Image Image 63 4 GB * * * Data space On-chip peripheral I/O area Image 1 Program space Reserved area Internal RAM area Internal RAM area Access-prohibited area 64 MB Access-prohibited area 64 MB Image 0 External memory area External memory area 16 MB Internal ROM area (external memory) Internal ROM area (external memory) User's Manual U16889EJ1V0UD 61 CHAPTER 3 CPU FUNCTIONS 3.4.2 Wraparound of CPU address space (1) Program space Of the 32 bits of the program counter (PC), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. Even if a carry or borrow occurs from bit 25 to bit 26 as a result of branch address calculation, the higher 6 bits ignore this and remain 0. Therefore, the lower-limit address of the program space, 00000000H, and the upper-limit address, 03FFFFFFH, are contiguous addresses, and the program space is wrapped around at the boundary of these addresses. Caution No instructions can be fetched from the 4 KB area of 03FFF000H to 03FFFFFFH because this area is an on-chip peripheral I/O area. Therefore, do not execute any branch operation instructions in which the destination address will reside in any part of this area. 00000001H 00000000H Program space (+) direction 03FFFFFFH 03FFFFFEH Program space (-) direction (2) Data space The result of an operand address calculation that exceeds 32 bits is ignored. Therefore, the lower-limit address of the data space, address 00000000H, and the upper-limit address, FFFFFFFFH, are contiguous addresses, and the data space is wrapped around at the boundary of these addresses. 00000001H 00000000H Data space (+) direction FFFFFFFFH FFFFFFFEH Data space (-) direction 62 User's Manual U16889EJ1V0UD CHAPTER 3 CPU FUNCTIONS 3.4.3 Memory map The V850ES/KJ1 has reserved areas as shown below. Figure 3-2. Data Memory Map (Physical Addresses) 3FFFFFFH (80 KB) 3FEC000H 3FEBFFFH On-chip peripheral I/O area (4 KB) 3FFFFFFH 3FFF000H 3FFEFFFH Internal RAM area (60 KB) Access-prohibited area 3FFF000H 3FFEFFFH Access-prohibited area 1000000H 0FFFFFFH 3FEC000H External memory area (8 MB) CS3 0800000H 07FFFFFH External memory area (4 MB) 0400000H 03FFFFFH 0200000H 01FFFFFH 0000000H External memory area (2 MB) CS2 01FFFFFH CS1 External memory area (1 MB) Internal ROM areaNote (1 MB) 0000000H 0100000H 00FFFFFH (2 MB) CS0 Note Fetch access and read access to addresses 0000000H to 00FFFFFH is performed for the internal ROM area, but in the case of data write access, it is performed for an external memory area. User's Manual U16889EJ1V0UD 63 CHAPTER 3 CPU FUNCTIONS Figure 3-3. Program Memory Map 03FFFFFFH 03FFF000H 03FFEFFFH Access-prohibited area (Program fetch disabled area) Internal RAM area (60 KB) 03FF0000H 03FEFFFFH Access-prohibited area (Program fetch disabled area) 01000000H 00FFFFFFH External memory area (8 MB) CS3 00800000H 007FFFFFH External memory area (4 MB) 00400000H 003FFFFFH 00200000H 001FFFFFH 00100000H 000FFFFFH 00000000H CS2 External memory area (2 MB) External memory area (1 MB) Internal ROM area (1 MB) CS1 CS0 64 User's Manual U16889EJ1V0UD CHAPTER 3 CPU FUNCTIONS 3.4.4 Areas (1) Internal ROM area An area of 1 MB from 0000000H to 00FFFFFH is reserved for the internal ROM area. (a) Internal ROM (256 KB) A 256 KB area from 0000000H to 003FFFFH is provided in the following products. Addresses 0040000H to 00FFFFFH are an access-prohibited area. * PD70F3218H, 70F3218HY Figure 3-4. Internal ROM Area (256 KB) 00FFFFFH Access-prohibited area 0040000H 003FFFFH Internal ROM area (256 KB) 0000000H User's Manual U16889EJ1V0UD 65 CHAPTER 3 CPU FUNCTIONS (b) Internal ROM (128 KB) A 128 KB area from 0000000H to 001FFFFH is provided in the following products. Addresses 0020000H to 00FFFFFH are an access-prohibited area. * PD703217, 703217Y, 70F3217, 70F3217Y, 70F3217H, 70F3217HY Figure 3-5. Internal ROM Area (128 KB) 00FFFFFH Access-prohibited area 0020000H 001FFFFH Internal ROM area (128 KB) 0000000H (c) Internal ROM (96 KB) A 96 KB area from 0000000H to 0017FFFH is provided in the following products. Addresses 0018000H to 00FFFFFH are an access-prohibited area. * PD703216, 703216Y Figure 3-6. Internal ROM Area (96 KB) 00FFFFFH Access-prohibited area 0018000H 0017FFFH Internal ROM area (96 KB) 0000000H 66 User's Manual U16889EJ1V0UD CHAPTER 3 CPU FUNCTIONS (2) Internal RAM area An area of 60 KB maximum from 3FF0000H to 3FFEFFFH is reserved for the internal RAM area. (a) Internal RAM (16 KB) A 16 KB area from 3FFB000H to 3FFEFFFH is provided as physical internal RAM. Addresses 3FF0000H to 3FFAFFFH are an access-prohibited area. * PD70F3218H, 70F3218HY Figure 3-7. Internal RAM Area (16 KB) Physical address space 3FFEFFFH Logical address space FFFEFFFH Internal RAM area (16 KB) 3FFB000H 3FFAFFFH FFFB000H FFFAFFFH Access-prohibited area 3FF0000H FFF0000H User's Manual U16889EJ1V0UD 67 CHAPTER 3 CPU FUNCTIONS (b) Internal RAM (6 KB) A 6 KB area from 3FFD800H to 3FFEFFFH is provided as physical internal RAM. Addresses 3FF0000H to 3FFD7FFH are an access-prohibited area. * PD703216, 703216Y, 703217, 703217Y, 70F3217, 70F3217Y, 70F3217H, 70F3217HY Figure 3-8. Internal RAM Area (6 KB) Physical address space 3FFEFFFH Internal RAM area (6 KB) 3FFD800H 3FFD7FFH Logical address space FFFEFFFH FFFD800H FFFD7FFH Access-prohibited area 3FF0000H FFF0000H 68 User's Manual U16889EJ1V0UD CHAPTER 3 CPU FUNCTIONS (3) On-chip peripheral I/O area A 4 KB area from 3FFF000H to 3FFFFFFH is reserved as the on-chip peripheral I/O area. Figure 3-9. On-Chip Peripheral I/O Area Physical address space 3FFFFFFH Logical address space FFFFFFFH On-chip peripheral I/O area (4 KB) 3FFF000H FFFF000H Peripheral I/O registers assigned with functions such as on-chip peripheral I/O operation mode specification and state monitoring are mapped to the on-chip peripheral I/O area. Program fetches are not allowed in this area. Cautions 1. If word access of a register is attempted, halfword access to the word area is performed twice, first for the lower bits, then for the higher bits, ignoring the lower 2 address bits. 2. If a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits become undefined if the access is a read operation. If a write access is performed, only the data in the lower 8 bits is written to the register. 3. Addresses that are not defined as registers are reserved for future expansion. If these addresses are accessed, the operation is undefined and not guaranteed. (4) External memory area 15 MB (0100000H to 0FFFFFFH) are provided as the external memory area. For details, refer to CHAPTER 5 BUS CONTROL FUNCTION. User's Manual U16889EJ1V0UD 69 CHAPTER 3 CPU FUNCTIONS 3.4.5 Recommended use of address space The architecture of the V850ES/KJ1 requires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. The address stored in this pointer 32 KB can be directly accessed by an instruction for operand data. Because the number of general-purpose registers that can be used as a pointer is limited, however, by keeping the performance from dropping during address calculation when a pointer value is changed, as many general-purpose registers as possible can be secured for variables, and the program size can be reduced. (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. Regarding the program space, therefore, a 64 MB space of contiguous addresses starting from 00000000H unconditionally corresponds to the memory map. To use the internal RAM area as the program space, access following addresses. RAM Size 6 KB 16 KB Access Address 3FFD800H to 3FFEFFFH 3FFB000H to 3FFEFFFH (2) Data space With the V850ES/KJ1, it seems that there are sixty-four 64 MB address spaces on the 4 GB CPU address space. Therefore, the least significant bit (bit 25) of a 26-bit address is sign-extended to 32 bits and allocated as an address. 70 User's Manual U16889EJ1V0UD CHAPTER 3 CPU FUNCTIONS (a) Application example of wraparound If R = r0 (zero register) is specified for the LD/ST disp16 [R] instruction, a range of addresses 00000000H 32 KB can be addressed by sign-extended disp16. All the resources, including the internal hardware, can be addressed by one pointer. The zero register (r0) is a register fixed to 0 by hardware, and practically eliminates the need for registers dedicated to pointers. Example: PD703217, 703217Y 0001FFFFH 00007FFFH Internal ROM area 32 KB (R = ) 0 0 0 0 0 0 0 0 H FFFFF000H FFFFEFFFH FFFFD800H FFFFD7FFH On-chip peripheral I/O area Internal RAM area 4 KB 6 KB 28 KB Access-prohibited area FFFF8000H User's Manual U16889EJ1V0UD 71 CHAPTER 3 CPU FUNCTIONS Figure 3-10. Recommended Memory Map Program space FFFFFFFFH Data space On-chip peripheral I/O FFFFF000H FFFFEFFFH Internal RAM xFFFFFFFH FFFEC000H FFFEBFFFH On-chip peripheral I/O xFFFF000H xFFFEFFFH Internal RAM xFFFD800H xFFFD7FFH xFFEC000H xFFEBFFFH On-chip peripheral I/ONote Internal RAM 04000000H 03FFFFFFH 03FFF000H 03FFEFFFH 03FFD800H 03FFD7FFH 03FEC000H 03FEBFFFH Use prohibited Use prohibited Program space 64 MB External memory 01000000H 00FFFFFFH External memory 00100000H 000FFFFFH 00020000H 0001FFFFH Internal ROM 00000000H Internal ROM Internal ROM x0000000H x0100000H x00FFFFFH Note Access to this area is prohibited. To access the on-chip peripheral I/O in this area, specify addresses FFFF000H to FFFFFFFH. Remarks 1. indicates the recommended area. 2. This figure is the recommended memory map of the PD703217 and 703217Y. 72 User's Manual U16889EJ1V0UD CHAPTER 3 CPU FUNCTIONS 3.4.6 Peripheral I/O registers (1/12) Address Function Register Name Symbol R/W Operable Bit Unit After Reset 1 FFFFF004H FFFFF004H FFFFF005H FFFFF006H FFFFF008H FFFFF00AH FFFFF00CH FFFFF00EH FFFFF024H FFFFF024H FFFFF025H FFFFF026H FFFFF028H FFFFF02AH FFFFF02CH FFFFF02EH FFFFF044H FFFFF044H FFFFF045H FFFFF046H FFFFF048H FFFFF04AH FFFFF04CH FFFFF066H FFFFF06EH FFFFF100H FFFFF100H FFFFF101H FFFFF102H FFFFF102H FFFFF103H FFFFF104H FFFFF104H FFFFF105H FFFFF106H FFFFF106H FFFFF110H FFFFF112H Port DL register Port DL register L Port DL register H Port DH register Port CS register Port CT register Port CM register Port CD register Port DL mode register Port DL mode register L Port DL mode register H Port DH mode register Port CS mode register Port CT mode register Port CM mode register Port CD mode register Port DL mode control register Port DL mode control register L P ort DL mode control register H Port DH mode control register Port CS mode control register Port CT mode control register Port CM mode control register Bus size configuration register System wait control register Interrupt mask register 0 Interrupt mask register 0L Interrupt mask register 0H Interrupt mask register 1 Interrupt mask register 1L Interrupt mask register 1H Interrupt mask register 2 Interrupt mask register 2L Interrupt mask register 2H Interrupt mask register 3 Interrupt mask register 3L Interrupt control register Interrupt control register PDL PDLL PDLH PDH PCS PCT PCM PCD PMDL PMDLL PMDLH PMDH PMCS PMCT PMCM PMCD PMCDL PMCDLL PMCDLH PMCDH PMCCS PMCCT PMCCM BSC VSWC IMR0 IMR0L IMR0H IMR1 IMR1L IMR1H IMR2 IMR2L IMR2H IMR3 Note 2 8 16 0000H 00H 00H 00H 00H 00H 00H 00H Note 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 FFFFH FFH FFH FFH FFH FFH FFH FFH 0000H 00H 00H 00H 00H 00H 00H 5555H 77H FFFFH FFH FFH FFFFH FFH FFH FFFFH FFH FFH FFFFH FFH 47H 47H IMR3L Note 2 WDT1IC PIC0 Notes 1. The output latch is 00H or 0000H. When input, the pin status is read. 2. Only in the PD70F3218H, 70F3218HY User's Manual U16889EJ1V0UD 73 CHAPTER 3 CPU FUNCTIONS (2/12) Address Function Register Name Symbol R/W Operable Bit Unit After Reset 1 FFFFF114H FFFFF116H FFFFF118H FFFFF11AH FFFFF11CH FFFFF11EH FFFFF120H FFFFF122H FFFFF124H FFFFF126H FFFFF128H FFFFF12AH FFFFF12CH FFFFF12EH FFFFF130H FFFFF132H FFFFF134H FFFFF136H FFFFF138H FFFFF13AH FFFFF13CH FFFFF13EH FFFFF140H FFFFF142H FFFFF144H FFFFF146H FFFFF148H FFFFF14AH FFFFF14CH FFFFF14EH FFFFF150H FFFFF152H FFFFF154H FFFFF156H FFFFF158H FFFFF15AH FFFFF15CH FFFFF15EH FFFFF160H FFFFF162H FFFFF164H Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register 2 8 16 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 TM0IC00 TM0IC01 TM0IC10 TM0IC11 TM5IC0 TM5IC1 CSI0IC0 CSI0IC1 SREIC0 SRIC0 STIC0 SREIC1 SRIC1 STIC1 TMHIC0 TMHIC1 CSIAIC0 IICIC0 ADIC KRIC WTIIC WTIC BRGIC TM0IC20 TM0IC21 TM0IC30 TM0IC31 CSIAIC1 TM0IC40 TM0IC41 TM0IC50 TM0IC51 CSI0IC2 SREIC2 SRIC2 Note R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note Only in products with an I C bus (Y products) 74 User's Manual U16889EJ1V0UD CHAPTER 3 CPU FUNCTIONS (3/12) Address Function Register Name Symbol R/W Operable Bit Unit After Reset 1 FFFFF166H FFFFF168H FFFFF174H FFFFF176H FFFFF178H FFFFF1FAH FFFFF1FCH FFFFF1FEH FFFFF200H FFFFF201H FFFFF202H FFFFF203H FFFFF204H FFFFF205H FFFFF280H FFFFF282H FFFFF284H FFFFF300H FFFFF400H FFFFF402H FFFFF406H FFFFF406H FFFFF407H FFFFF408H FFFFF40AH FFFFF40CH FFFFF40CH FFFFF40DH FFFFF40EH FFFFF40EH FFFFF40FH FFFFF410H FFFFF412H FFFFF412H FFFFF413H FFFFF420H FFFFF422H FFFFF426H FFFFF426H FFFFF427H Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register In-service priority register Command register Power save control register A/D converter mode register Analog input channel specification register Power fail comparison mode register Power fail comparison threshold register A/D conversion result register A/D conversion result register H D/A conversion value setting register 0 D/A conversion value setting register 1 D/A converter mode register Key return mode register Port 0 register Port 1 register Port 3 register Port 3 register L Port 3 register H Port 4 register Port 5 register Port 6 register Port 6 register L Port 6 register H Port 7 register Port 7 register L Port 7 register H Port 8 register Port 9 register Port 9 register L Port 9 register H Port 0 mode register Port 1 mode register Port 3 mode register Port 3 mode register L Port 3 mode register H 2 8 16 47H 47H 47H 47H 47H 00H Undefined 00H 00H 00H 00H 00H Undefined Undefined 00H 00H 00H 00H 00H 00H Note 3 STIC2 IICIC1 Note 1 R/W R/W R/W R/W R/W R W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W TP0OVIC Note 2 TP0CCIC0 TP0CCIC1 ISPR PRCMD PSC ADM ADS PFM PFT ADCR ADCRH DACS0 DACS1 DAM KRM P0 P1 P3 P3L P3H P4 P5 P6 P6L P6H P7 P7L P7H P8 P9 P9L P9H PM0 PM1 PM3 PM3L PM3H Note 2 Note 2 Note 3 0000H 00H 00H 00H 00H Note 3 Note 3 Note 3 Note 3 Note 3 0000H 00H 00H Note 3 Note 3 Note 3 Undefined Undefined Undefined 00H Note 3 0000H 00H 00H Note 3 Note 3 Note 3 FFH FFH FFFFH FFH FFH Notes 1. Only in products with an I C bus (Y products) 2. Only in the PD70F3218H, 70F3218HY 3. The output latch is 00H or 0000H. When input, the pin status is read. User's Manual U16889EJ1V0UD 75 CHAPTER 3 CPU FUNCTIONS (4/12) Address Function Register Name Symbol R/W Operable Bit Unit After Reset 1 FFFFF428H FFFFF42AH FFFF42CH FFFFF42CH FFFFF42DH FFFFF430H FFFFF432H FFFFF432H FFFFF433H FFFFF440H FFFFF446H FFFFF446H FFFFF447H FFFFF448H FFFFF44AH FFFFF44CH FFFFF44CH FFFFF44DH FFFFF450H FFFFF452H FFFFF452H FFFFF453H FFFFF466H FFFFF46AH FFFFF46DH FFFFF470H FFFFF472H FFFFF472H FFFFF473H FFFFF484H FFFFF488H FFFFF48AH FFFFF580H FFFFF581H FFFFF582H FFFFF583H FFFFF590H FFFFF591H FFFFF592H FFFFF593H Port 4 mode register Port 5 mode register Port 6 mode register Port 6 mode register L Port 6 mode register H Port 8 mode register Port 9 mode register Port 9 mode register L Port 9 mode register H Port 0 mode control register Port 3 mode control register Port 3 mode control register L Port 3 mode control register H Port 4 mode control register Port 5 mode control register Port 6 mode control register Port 6 mode control register L Port 6 mode control register H Port 8 mode control register Port 9 mode control register Port 9 mode control register L Port 9 mode control register H Port 3 function control register Port 5 function control register Port 6 function control register Port 8 function control register Port 9 function control register Port 9 function control register L Port 9 function control register H Data wait control register 0 Address wait control register Bus cycle control register 8-bit timer H mode register 0 8-bit timer H carrier control register 0 8-bit timer H compare register 00 8-bit timer H compare register 01 8-bit timer H mode register 1 8-bit timer H carrier control register 1 8-bit timer H compare register 10 8-bit timer H compare register 11 PM4 PM5 PM6 PM6L PM6H PM8 PM9 PM9L PM9H PMC0 PMC3 PMC3L PMC3H PMC4 PMC5 PMC6 PMC6L PMC6H PMC8 PMC9 PMC9L PMC9H PFC3 PFC5 PFC6H PFC8 PFC9 PFC9L PFC9H DWC0 AWC BCC TMHMD0 TMCYC0 CMP00 CMP01 TMHMD1 TMCYC1 CMP10 CMP11 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 16 FFH FFH FFFFH FFH FFH FFH FFFFH FFH FFH 00H 0000H 00H 00H 00H 00H 0000H 00H 00H 00H 0000H 00H 00H 00H 00H 00H 00H 0000H 00H 00H 7777H FFFFH AAAAH 00H 00H 00H 00H 00H 00H 00H 00H 76 User's Manual U16889EJ1V0UD CHAPTER 3 CPU FUNCTIONS (5/12) Address Function Register Name Symbol R/W Operable Bit Unit After Reset 1 FFFFF5A0H FFFFF5A1H FFFFF5A2H FFFFF5A3H FFFFF5A4H FFFFF5A5H FFFFF5A6H FFFFF5A8H FFFFF5AAH FFFFF5C0H FFFFF5C0H FFFFF5C1H FFFFF5C2H FFFFF5C2H FFFFF5C3H FFFFF5C4H FFFFF5C4H FFFFF5C5H FFFFF5C6H FFFFF5C6H FFFFF5C7H FFFFF600H FFFFF602H FFFFF604H FFFFF606H FFFFF607H FFFFF608H FFFFF609H FFFFF610H FFFFF612H FFFFF614H FFFFF616H FFFFF617H FFFFF618H FFFFF619H FFFFF620H FFFFF622H FFFFF624H FFFFF626H FFFFF627H FFFFF628H TMP0 control register 0 TMP0 control register 1 TMP0 I/O control register 0 TMP0 I/O control register 1 TMP0 I/O control register 2 TMP0 option register 0 TMP0 capture/compare register 0 TMP0 capture/compare register 1 TMP0 counter read buffer register 16-bit timer counter 5 8-bit timer counter 50 8-bit timer counter 51 16-bit timer compare register 5 8-bit timer compare register 50 8-bit timer compare register 51 Timer clock selection register 5 Timer clock selection register 50 Timer clock selection register 51 16-bit timer mode control register 5 8-bit timer mode control register 50 8-bit timer mode control register 51 16-bit timer counter 00 16-bit timer capture/compare register 000 16-bit timer capture/compare register 001 16-bit timer mode control register 00 Prescaler mode register 00 Capture/compare control register 00 16-bit timer output control register 00 16-bit timer counter 01 16-bit timer capture/compare register 010 16-bit timer capture/compare register 011 16-bit timer mode control register 01 Prescaler mode register 01 Capture/compare control register 01 16-bit timer output control register 01 16-bit timer counter 02 16-bit timer capture/compare register 020 16-bit timer capture/compare register 021 16-bit timer mode control register 02 Prescaler mode register 02 Capture/compare control register 02 TP0CTL0 TP0CTL1 TP0IOC0 TP0IOC1 TP0IOC2 Note 8 16 00H 00H 00H 00H 00H 00H 0000H 0000H 0000H 0000H 00H 00H 0000H 00H 00H 0000H 00H 00H 0000H 00H 00H 0000H 0000H 0000H 00H 00H 00H 00H 0000H 0000H 0000H 00H 00H 00H 00H 0000H 0000H 0000H 00H 00H 00H R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W Note Note Note Note TP0OPT0 Note TP0CCR0 TP0CCR1 TP0CNT TM5 TM50 TM51 CR5 CR50 CR51 TCL5 TCL50 TCL51 TMC5 TMC50 TMC51 TM00 CR000 CR001 TMC00 PRM00 CRC00 TOC00 TM01 CR010 CR011 TMC01 PRM01 CRC01 TOC01 TM02 CR020 CR021 TMC02 PRM02 CRC02 Note Note Note Note Only in the PD70F3218H, 70F3218HY User's Manual U16889EJ1V0UD 77 CHAPTER 3 CPU FUNCTIONS (6/12) Address Function Register Name Symbol R/W Operable Bit Unit 1 FFFFF629H FFFFF630H FFFFF632H FFFFF634H FFFFF636H FFFFF637H FFFFF638H FFFFF639H FFFFF640H FFFFF642H FFFFF644H FFFFF646H FFFFF647H FFFFF648H FFFFF649H FFFFF650H FFFFF652H FFFFF654H FFFFF656H FFFFF657H FFFFF658H FFFFF659H FFFFF680H FFFFF6C0H FFFFF6C1H FFFFF6C2H FFFFF6D0H FFFFF6D1H FFFFF6E0H FFFFF6E2H FFFFF6E4H FFFFF6E5H FFFFF6F0H FFFFF6F2H FFFFF6F4H FFFFF6F5H FFFFF706H FFFFF802H FFFFF806H FFFFF820H FFFFF828H 16-bit timer output control register 02 16-bit timer counter 03 16-bit timer capture/compare register 030 16-bit timer capture/compare register 031 16-bit timer mode control register 03 Prescaler mode register 03 Capture/compare control register 03 16-bit timer output control register 03 16-bit timer counter 04 16-bit timer capture/compare register 040 16-bit timer capture/compare register 041 16-bit timer mode control register 04 Prescaler mode register 04 Capture/compare control register 04 16-bit timer output control register 04 16-bit timer counter 05 16-bit timer capture/compare register 050 16-bit timer capture/compare register 051 16-bit timer mode control register 05 Prescaler mode register 05 Capture/compare control register 05 16-bit timer output control register 05 Watch timer operation mode register Oscillation stabilization time select register Watchdog timer clock selection register Watchdog timer mode register 1 Watchdog timer mode register 2 Watchdog timer enable register Real-time output buffer register L0 Real-time output buffer register H0 Real-time output port mode register 0 Real-time output port control register 0 Real-time output buffer register L1 Real-time output buffer register H1 Real-time output port mode register 1 Real-time output port control register 1 Port 3 function control expansion register System status register PLL control register Power save mode register Processor clock control register TOC02 TM03 CR030 CR031 TMC03 PRM03 CRC03 TOC03 TM04 CR040 CR041 TMC04 PRM04 CRC04 TOC04 TM05 CR050 CR051 TMC05 PRM05 CRC05 TOC05 WTM OSTS WDCS WDTM1 WDTM2 WDTE RTBL0 RTBH0 RTPM0 RTPC0 RTBL1 RTBH1 RTPM1 RTPC1 PFCE3 SYS PLLCTL PSMR PCC Note After Reset 8 16 32 00H R/W R R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0000H 0000H 0000H 00H 00H 00H 00H 0000H 0000H 0000H 00H 00H 00H 00H 0000H 0000H 0000H 00H 00H 00H 00H 00H 01H 00H 00H 67H 9AH 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 01H 00H 03H Note Only in the PD70F3218H, 70F3218HY User's Manual U16889EJ1V0UD 78 CHAPTER 3 CPU FUNCTIONS (7/12) Address Function Register Name Symbol R/W Operable Bit Unit 1 FFFFF840H FFFFF840H FFFFF842H FFFFF844H FFFFF844H FFFFF846H FFFFF848H FFFFF848H FFFFF84AH FFFFF84CH FFFFF84CH FFFFF84EH FFFFF880H FFFFF8B0H FFFFF8B1H FFFFF9FCH FFFFFA00H FFFFFA02H FFFFFA03H FFFFFA04H FFFFFA05H FFFFFA06H FFFFFA07H FFFFFA10H FFFFFA12H FFFFFA13H FFFFFA14H FFFFFA15H FFFFFA16H FFFFFA17H FFFFFA20H FFFFFA22H FFFFFA23H FFFFFA24H FFFFFA25H FFFFFA26H FFFFFA27H FFFFFB00H Correction address register 0 Correction address register 0L Correction address register 0H Correction address register 1 Correction address register 1L Correction address register 1H Correction address register 2 Correction address register 2L Correction address register 2H Correction address register 3 Correction address register 3L Correction address register 3H Correction control register Interval timer BRG mode register Interval timer BRG compare register On-chip debug mode register Asynchronous serial interface mode register 0 Receive buffer register 0 Asynchronous serial interface status register 0 Transmit buffer register 0 Asynchronous serial interface transmission status register 0 Clock selection register 0 Baud rate generator control register 0 Asynchronous serial interface mode register 1 Receive buffer register 1 Asynchronous serial interface status register 1 Transmit buffer register 1 Asynchronous serial interface transmission status register 1 Clock selection register 1 Baud rate generator control register 1 Asynchronous serial interface mode register 2 Receive buffer register 2 Asynchronous serial interface status register 2 Transmit buffer register 2 Asynchronous serial interface transmission status register 2 Clock selection register 2 Baud rate generator control register 2 TIP00 noise elimination control register CORAD0 CORAD0L CORAD0H CORAD1 CORAD1L CORAD1H CORAD2 CORAD2L CORAD2H CORAD3 CORAD3L CORAD3H CORCN PRSM PRSCM OCDM ASIM0 RXB0 ASIS0 TXB0 ASIF0 CKSR0 BRGC0 ASIM1 RXB1 ASIS1 TXB1 ASIF1 CKSR1 BRGC1 ASIM2 RXB2 ASIS2 TXB2 ASIF2 CKSR2 BRGC2 P0NFC Note Note After Reset 8 16 32 00000000H 0000H 0000H 00000000H 0000H 0000H 00000000H 0000H 0000H 00000000H 0000H 0000H 00H 00H 00H 01H 01H FFH 00H FFH 00H 00H FFH 01H FFH 00H FFH 00H 00H FFH 01H FFH 00H FFH 00H 00H FFH 00H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R R/W R/W R/W R R R/W R R/W R/W R/W R R R/W R R/W R/W R/W Note Only in the PD70F3218H, 70F3218HY User's Manual U16889EJ1V0UD 79 CHAPTER 3 CPU FUNCTIONS (8/12) Address Function Register Name Symbol R/W Operable Bit Unit After Reset 1 FFFFFB04H FFFFFC00H FFFFFC13H FFFFFC20H FFFFFC33H FFFFFC40H FFFFFC42H FFFFFC46H FFFFFC48H FFFFFC4AH FFFFFC4CH TIP01 noise elimination control register External interrupt falling edge specification register 0 External interrupt falling edge specification register 9H External interrupt rising edge specification register 0 External interrupt rising edge specification register 9H Pull-up resistor option register 0 Pull-up resistor option register 1 Pull-up resistor option register 3 Pull-up resistor option register 4 Pull-up resistor option register 5 Pull-up resistor option register 6 P1NFC INTF0 INTF9H INTR0 INTR9H PU0 PU1 PU3 PU4 PU5 PU6 PU6L PU6H PU8 PU9 PU9L PU9H PF3H PF4 PF5 PF6 PF6L PF6H PF8 PF9H CSIM00 CSIC0 SIRB0 SIRB0L SOTB0 SOTB0L SIRBE0 SIRBE0L SOTBF0 Note 8 16 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 0000H 00H 00H 00H 0000H 00H 00H 00H 00H 00H 0000H 00H 00H 00H 00H 00H 00H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R R R/W R/W R/W R/W R/W R/W R R FFFFFC4CH Pull-up resistor option register 6L FFFFFC4DH Pull-up resistor option register 6H FFFFFC50H FFFFFC52H FFFFFC52H FFFFFC53H FFFFFC67H FFFFFC68H FFFFFC6AH FFFFFC6CH Pull-up resistor option register 8 Pull-up resistor option register 9 Pull-up resistor option register 9L Pull-up resistor option register 9H Port 3 function register H Port 4 function register Port 5 function register Port 6 function register FFFFFC6CH Port 6 function register L FFFFFC6DH Port 6 function register H FFFFFC70H FFFFFC73H FFFFFD00H FFFFFD01H FFFFFD02H FFFFFD02H FFFFFD04H FFFFFD04H FFFFFD06H FFFFFD06H FFFFFD08H FFFFFD08H FFFFFD0AH FFFFFD0AH FFFFFD10H FFFFFD11H FFFFFD12H FFFFFD12H Port 8 function register Port 9 function register H Clocked serial interface mode register 00 Clocked serial interface clock selection register 0 Clocked serial interface receive buffer register 0 Clocked serial interface receive buffer register 0L Clocked serial interface transmit buffer register 0 Clocked serial interface transmit buffer register 0L Clocked serial interface read-only receive buffer register 0 Clocked serial interface read-only receive buffer register 0L Clocked serial interface first-stage transmit buffer register 0 0000H 00H 0000H 00H 0000H 00H 0000H 00H 00H 0000H 00H 00H Clocked serial interface first-stage transmit buffer register 0L SOTBF0L Serial I/O shift register 0 Serial I/O shift register 0L Clocked serial interface mode register 01 Clocked serial interface clock selection register 1 Clocked serial interface receive buffer register 1 Clocked serial interface receive buffer register 1L SIO00 SIO00L CSIM01 CSIC1 SIRB1 SIRB1L 0000H 00H Note Only in the PD70F3218H, 70F3218HY 80 User's Manual U16889EJ1V0UD CHAPTER 3 CPU FUNCTIONS (9/12) Address Function Register Name Symbol R/W Operable Bit Unit After Reset 1 FFFFFD14H FFFFFD14H FFFFFD16H FFFFFD16H FFFFFD18H FFFFFD18H FFFFFD1AH FFFFFD1AH FFFFFD20H FFFFFD21H FFFFFD22H FFFFFD22H FFFFFD24H FFFFFD24H FFFFFD26H FFFFFD26H FFFFFD28H FFFFFD28H FFFFFD2AH FFFFFD2AH FFFFFD40H FFFFFD41H FFFFFD42H FFFFFD43H FFFFFD44H FFFFFD45H FFFFFD46H FFFFFD47H FFFFFD50H FFFFFD51H FFFFFD52H FFFFFD53H FFFFFD54H FFFFFD55H FFFFFD56H FFFFFD57H FFFFFD80H FFFFFD82H FFFFFD83H FFFFFD84H FFFFFD85H Clocked serial interface transmit buffer register 1 Clocked serial interface transmit buffer register 1L Clocked serial interface read-only receive buffer register 1 Clocked serial interface read-only receive buffer register 1L Clocked serial interface first-stage transmit buffer register 1 Clocked serial interface first-stage transmit buffer register 1L Serial I/O shift register 1 Serial I/O shift register 1L Clocked serial interface mode register 02 Clocked serial interface clock selection register 2 Clocked serial interface receive buffer register 2 Clocked serial interface receive buffer register 2L Clocked serial interface transmit buffer register 2 Clocked serial interface transmit buffer register 2L Clocked serial interface read-only receive buffer register 2 Clocked serial interface read-only receive buffer register 2L Clocked serial interface first-stage transmit buffer register 2 Clocked serial interface first-stage transmit buffer register 2L Serial I/O shift register 2 Serial I/O shift register 2L Serial operation mode specification register 0 Serial status register 0 Serial trigger register 0 Division value selection register 0 SOTB1 SOTB1L SIRBE1 SIRBE1L SOTBF1 SOTBF1L SIO01 SIO1L CSIM02 CSIC2 SIRB2 SIRB2L SOTB2 SOTB2L SIRBE2 SIRBE2L SOTBF2 SOTBF2L SIO02 SIO02L CSIMA0 CSIS0 CSIT0 BRGCA0 R/W R/W R R R/W R/W R/W R/W R/W R/W R R R/W R/W R R R/W R/W 8 16 0000H 00H 0000H 00H 0000H 00H 00H 0000H 00H 00H 0000H 00H 0000H 00H 0000H 00H 0000H 00H R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R R/W R/W R/W R/W R R/W R/W R/W R/W R/W 00H 0000H 00H 00H 00H 03H 00H 00H 00H 00H 00H 00H 00H 03H 00H 00H 00H 00H 00H 00H 00H 00H 00H Automatic data transfer address point specification register 0 ADTP0 Automatic data transfer interval specification register 0 Serial I/O shift register A0 Automatic data transfer address count register 0 Serial operation mode specification register 1 Serial status register 1 Serial trigger register 1 Division value selection register 1 ADTI0 SIOA0 ADTC0 CSIMA1 CSIS1 CSIT1 BRGCA1 Automatic data transfer address point specification register 1 ADTP1 Automatic data transfer interval specification register 1 Serial I/O shift register A1 Automatic data transfer address count register 1 IIC shift register 0 IIC control register 0 Slave address register 0 IIC clock selection register 0 IIC function expansion register 0 2 ADTI1 SIOA1 ADTC1 IIC0 Note IICC0 Note SVA0 Note IICCL0 IICX0 Note Note Note Only in products with an I C bus (Y products) User's Manual U16889EJ1V0UD 81 CHAPTER 3 CPU FUNCTIONS (10/12) Address Function Register Name Symbol R/W Operable Bit Unit After Reset 1 FFFFFD86H FFFFFD8AH FFFFFD90H FFFFFD92H FFFFFD93H FFFFFD94H FFFFFD95H FFFFFD96H FFFFFD9AH FFFFFE00H FFFFFE00H FFFFFE01H FFFFFE02H FFFFFE02H FFFFFE03H FFFFFE04H FFFFFE04H FFFFFE05H FFFFFE06H FFFFFE06H FFFFFE07H FFFFFE08H FFFFFE08H FFFFFE09H FFFFFE0AH FFFFFE0AH FFFFFE0BH FFFFFE0CH FFFFFE0CH FFFFFE0DH FFFFFE0EH FFFFFE0EH FFFFFE0FH FFFFFE10H FFFFFE10H FFFFFE11H FFFFFE12H FFFFFE12H FFFFFE13H IIC status register 0 IIC flag register 0 IIC shift register 1 IIC control register 1 Slave address register 1 IIC clock selection register 1 IIC function expansion register 1 IIC status register 1 IIC flag register 1 CSIA0 buffer RAM 0 CSIA0 buffer RAM 0L CSIA0 buffer RAM 0H CSIA0 buffer RAM 1 CSIA0 buffer RAM 1L CSIA0 buffer RAM 1H CSIA0 buffer RAM 2 CSIA0 buffer RAM 2L CSIA0 buffer RAM 2H CSIA0 buffer RAM 3 CSIA0 buffer RAM 3L CSIA0 buffer RAM 3H CSIA0 buffer RAM 4 CSIA0 buffer RAM 4L CSIA0 buffer RAM 4H CSIA0 buffer RAM 5 CSIA0 buffer RAM 5L CSIA0 buffer RAM 5H CSIA0 buffer RAM 6 CSIA0 buffer RAM 6L CSIA0 buffer RAM 6H CSIA0 buffer RAM 7 CSIA0 buffer RAM 7L CSIA0 buffer RAM 7H CSIA0 buffer RAM 8 CSIA0 buffer RAM 8L CSIA0 buffer RAM 8H CSIA0 buffer RAM 9 CSIA0 buffer RAM 9L CSIA0 buffer RAM 9H 2 8 16 00H 00H 00H 00H 00H 00H 00H 00H 00H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined IICS0 IICF0 IIC1 Note R R/W R/W Note Note IICC01 Note R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W SVA01 Note IICCL01 IICX1 Note Note IICS01 IICF1 Note Note CSIA0B0 CSIA0B0L CSIA0B0H CSIA0B1 CSIA0B1L CSIA0B1H CSIA0B2 CSIA0B2L CSIA0B2H CSIA0B3 CSIA0B3L CSIA0B3H CSIA0B4 CSIA0B4L CSIA0B4H CSIA0B5 CSIA0B5L CSIA0B5H CSIA0B6 CSIA0B6L CSIA0B6H CSIA0B7 CSIA0B7L CSIA0B7H CSIA0B8 CSIA0B8L CSIA0B8H CSIA0B9 CSIA0B9L CSIA0B9H Note Only in products with an I C bus (Y products) 82 User's Manual U16889EJ1V0UD CHAPTER 3 CPU FUNCTIONS (11/12) Address Function Register Name Symbol R/W Operable Bit Unit After Reset 1 FFFFFE14H FFFFFE14H FFFFFE15H FFFFFE16H FFFFFE16H FFFFFE17H FFFFFE18H FFFFFE18H FFFFFE19H FFFFFE1AH FFFFFE1AH FFFFFE1BH FFFFFE1CH FFFFFE1CH FFFFFE1DH FFFFFE1EH FFFFFE1EH FFFFFE1FH FFFFFE20H FFFFFE20H FFFFFE21H FFFFFE22H FFFFFE22H FFFFFE23H FFFFFE24H FFFFFE24H FFFFFE25H FFFFFE26H FFFFFE26H FFFFFE27H FFFFFE28H FFFFFE28H FFFFFE29H FFFFFE2AH FFFFFE2AH FFFFFE2BH FFFFFE2CH FFFFFE2CH FFFFFE2DH FFFFFE2EH FFFFFE2EH FFFFFE2FH CSIA0 buffer RAM A CSIA0 buffer RAM AL CSIA0 buffer RAM AH CSIA0 buffer RAM B CSIA0 buffer RAM BL CSIA0 buffer RAM BH CSIA0 buffer RAM C CSIA0 buffer RAM CL CSIA0 buffer RAM CH CSIA0 buffer RAM D CSIA0 buffer RAM DL CSIA0 buffer RAM DH CSIA0 buffer RAM E CSIA0 buffer RAM EL CSIA0 buffer RAM EH CSIA0 buffer RAM F CSIA0 buffer RAM FL CSIA0 buffer RAM FH CSIA1 buffer RAM 0 CSIA1 buffer RAM 0L CSIA1 buffer RAM 0H CSIA1 buffer RAM 1 CSIA1 buffer RAM 1L CSIA1 buffer RAM 1H CSIA1 buffer RAM 2 CSIA1 buffer RAM 2L CSIA1 buffer RAM 2H CSIA1 buffer RAM 3 CSIA1 buffer RAM 3L CSIA1 buffer RAM 3H CSIA1 buffer RAM 4 CSIA1 buffer RAM 4L CSIA1 buffer RAM 4H CSIA1 buffer RAM 5 CSIA1 buffer RAM 5L CSIA1 buffer RAM 5H CSIA1 buffer RAM 6 CSIA1 buffer RAM 6L CSIA1 buffer RAM 6H CSIA1 buffer RAM 7 CSIA1 buffer RAM 7L CSIA1 buffer RAM 7H CSIA0BA CSIA0BAL CSIA0BAH CSIA0BB CSIA0BBL CSIA0BBH CSIA0BC CSIA0BCL CSIA0BCH CSIA0BD CSIA0BDL CSIA0BDH CSIA0BE CSIA0BEL CSIA0BEH CSIA0BF CSIA0BFL CSIA0BFH CSIA1B0 CSIA1B0L CSIA1B0H CSIA1B1 CSIA1B1L CSIA1B1H CSIA1B2 CSIA1B2L CSIA1B2H CSIA1B3 CSIA1B3L CSIA1B3H CSIA1B4 CSIA1B4L CSIA1B4H CSIA1B5 CSIA1B5L CSIA1B5H CSIA1B6 CSIA1B6L CSIA1B6H CSIA1B7 CSIA1B7L CSIA1B7H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 16 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined User's Manual U16889EJ1V0UD 83 CHAPTER 3 CPU FUNCTIONS (12/12) Address Function Register Name Symbol R/W Operable Bit Unit After Reset 1 FFFFFE30H FFFFFE30H FFFFFE31H FFFFFE32H FFFFFE32H FFFFFE33H FFFFFE34H FFFFFE34H FFFFFE35H FFFFFE36H FFFFFE36H FFFFFE37H FFFFFE38H FFFFFE38H FFFFFE39H FFFFFE3AH FFFFFE3AH FFFFFE3BH FFFFFE3CH FFFFFE3CH FFFFFE3DH FFFFFE3EH FFFFFE3EH FFFFFE3FH FFFFFFBEH CSIA1 buffer RAM 8 CSIA1 buffer RAM 8L CSIA1 buffer RAM 8H CSIA1 buffer RAM 9 CSIA1 buffer RAM 9L CSIA1 buffer RAM 9H CSIA1 buffer RAM A CSIA1 buffer RAM AL CSIA1 buffer RAM AH CSIA1 buffer RAM B CSIA1 buffer RAM BL CSIA1 buffer RAM BH CSIA1 buffer RAM C CSIA1 buffer RAM CL CSIA1 buffer RAM CH CSIA1 buffer RAM D CSIA1 buffer RAM DL CSIA1 buffer RAM DH CSIA1 buffer RAM E CSIA1 buffer RAM EL CSIA1 buffer RAM EH CSIA1 buffer RAM F CSIA1 buffer RAM FL CSIA1 buffer RAM FH External bus interface mode control register CSIA1B8 CSIA1B8L CSIA1B8H CSIA1B9 CSIA1B9L CSIA1B9H CSIA1BA CSIA1BAL CSIA1BAH CSIA1BB CSIA1BBL CSIA1BBH CSIA1BC CSIA1BCL CSIA1BCH CSIA1BD CSIA1BDL CSIA1BDH CSIA1BE CSIA1BEL CSIA1BEH CSIA1BF CSIA1BFL CSIA1BFH EXIMC R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 16 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 00H 84 User's Manual U16889EJ1V0UD CHAPTER 3 CPU FUNCTIONS 3.4.7 Special registers Special registers are registers that prevent invalid data from being written when an inadvertent program loop occurs. The V850ES/KJ1 has the following three special registers. * Power save control register (PSC) * Processor clock control register (PCC) * Watchdog timer mode register (WDTM1) Moreover, there is also the PRCMD register, which is a protection register for write operations to the special registers that prevents the application system from unexpectedly stopping due to an inadvertent program loop. Write access to the special registers is performed with a special sequence and illegal store operations are notified to the SYS register. (1) Setting data to special registers Setting data to a special registers is done in the following sequence. <1> <2> <3> Prepare the data to be set to the special register in a general-purpose register. Write the data prepared in step <1> to the PRCMD register. Write the setting data to the special register (using following instructions). * Store instruction (ST/SST instruction) * Bit manipulation instruction (SET1/CLR1/NOT1 instruction) <4> to <8> Insert NOP instructions (5 instructions)Note. [Description Example] When using PSC register (standby mode setting) ST.B r11,PSMR[r0] <1> MOV 0x02,r10 <2> ST.B r10,PRCMD[r0] <3> ST.B r10,PSC[r0] <4> NOPNote <5> NOPNote <6> NOP <8> NOP Note ; PSMR register setting (IDLE, STOP mode setting) ; PRCMD register write ; PSC register setting ; Dummy instruction ; Dummy instruction ; Dummy instruction ; Dummy instruction ; Dummy instruction <7> NOPNote Note (next instruction) No special sequence is required to read special registers. Note When switching to the IDLE mode or the STOP mode (PSC.STP bit = 1), 5 NOP instructions must be inserted immediately after switching is performed. Cautions 1. Interrupts are not acknowledged for the store instruction for the PRCMD register. This is because continuous execution of store instructions by the program in steps <2> and <3> above is assumed. If another instruction is placed between step <2> and <3>, the above sequence may not be realized when an interrupt is acknowledged for that instruction, which may cause malfunction. 2. The data written to the PRCMD register is dummy data, but use the same register as the general-purpose register used for setting data to the special register (step <3>) when writing to the PRCMD register (step <2>). The same applies to when using a generalpurpose register for addressing. User's Manual U16889EJ1V0UD 85 CHAPTER 3 CPU FUNCTIONS (2) Command register (PRCMD) The PRCMD register is an 8-bit register used to prevent data from being written to registers that may have a large influence on the system, possibly causing the application system to unexpectedly stop, when an inadvertent program loop occurs. Only the first write operation to the special register following the execution of a previously executed write operation to the PRCMD register, is valid. As a result, register values can be overwritten only using a preset sequence, preventing invalid write operations. This register can only be written in 8-bit units (if it is read, an undefined value is returned). After reset: Undefined 7 PRCMD REG7 6 W Address: FFFFF1FCH 5 REG5 4 REG4 3 REG3 2 REG2 1 REG1 0 REG0 REG6 (3) System status register (SYS) This register is allocated with status flags showing the operating state of the entire system. This register can be read or written in 8-bit or 1-bit units. After reset: 00H R/W Address: FFFFF802H <> SYS 0 0 0 0 0 0 0 PRERR PRERR 0 1 Detection of protection error Protection error has not occurred Protection error has occurred 86 User's Manual U16889EJ1V0UD CHAPTER 3 CPU FUNCTIONS The operation conditions of the PRERR flag are described below. (a) Set conditions (PRERR = 1) (i) When a write operation to the special register takes place without write operation being performed to the PRCMD register (when step <3> is performed without performing step <2> as described in 3.4.7 (1) Setting data to special registers). (ii) When a write operation (including bit manipulation instruction) to an on-chip peripheral I/O register other than a special register is performed following write to the PRCMD register (when <3> in 3.4.7 (1) Setting data to special registers is not a special register). Remark Regarding the special registers other than the WDTM register (PCC and PSC registers), even if on-chip peripheral I/O register read (except bit manipulation instruction) (internal RAM access, etc.) is performed in between write to the PRCMD register and write to a special register, the PRERR flag is not set and setting data can be written to the special register. (b) Clear conditions (PRERR = 0) (i) When 0 is written to the PRERR flag (ii) When system reset is performed Cautions 1. If 0 is written to the PRERR bit of the SYS register that is not a special register immediately following write to the PRCMD register, the PRERR bit becomes 0 (write priority). 2. If data is written to the PRCMD register that is not a special register immediately following write to the PRCMD register, the PRERR bit becomes 1. User's Manual U16889EJ1V0UD 87 CHAPTER 3 CPU FUNCTIONS 3.4.8 Cautions Be sure to set the following register before using the V850ES/KJ1. * System wait control register (VSWC) After setting the VSWC register, set the other registers as required. When using an external bus, set the VSWC register and then set the various pins to the control mode by setting the port-related registers. (1) System wait control register (VSWC) The VSWC register controls the bus access wait time for the on-chip peripheral I/O registers. Access to the on-chip peripheral I/O register lasts 3 clocks (during no wait), but in the V850ES/KJ1, waits are required according to the internal system clock frequency. Set the values shown below to the VSWC register according to the internal system clock frequency that is used. This register can be read or written in 8-bit units (Address: FFFFF06EH, After reset: 77H). Operation Conditions Internal System Clock Frequency (fCLK) REGC = VDD = 5 V10%, In PLL mode (fX = 2 to 5 MHz) REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V REGC = VDD = 2.7 to 4.0 V 32 kHz fCLK < 16.6 MHz 16.6 MHz fCLK 20 MHz 32 kHz fCPU 16 MHz 32 kHz fCLK < 8 MHz 32 kHz fCLK 8 MHz 00H 01H 00H 00H 00H VSWC Register Setting Remark fX: Main clock oscillation frequency (2) Access to special on-chip peripheral I/O register This product has two types of internal system buses. One type is for the CPU bus and the other is for the peripheral bus to interface with low-speed peripheral hardware. Since the CPU bus clock and peripheral bus clock are asynchronous, if a conflict occurs during access between the CPU and peripheral hardware, illegal data may be passed unexpectedly. Therefore, when accessing peripheral hardware that may cause a conflict, the number of access cycles is changed so that the data is received/passed correctly in the CPU. As a result, the CPU does not shift to the next instruction processing and enters the wait status. When this wait status occurs, the number of execution clocks of the instruction is increased by the number of wait clocks. Note this with caution when performing real-time processing. When accessing a special on-chip peripheral I/O register, additional waits may be required further to the waits set by the VSWC register. The access conditions at that time and the method to calculate the number of waits to be inserted (number of CPU clocks) are shown below. 88 User's Manual U16889EJ1V0UD CHAPTER 3 CPU FUNCTIONS Peripheral Function Watchdog timer 1 (WDT1) Register Name WDTM1 {(1/fX) x 2/((2 + m)/fCPU)} + 1 fX: Main clock oscillation frequency Write Access 1 to 5 k Watchdog timer 2 (WDT2) 16-bit timer/event counter P0 (TMP0) Note 1 WDTM2 TP0CCR0, TP0CCR1, TP0CNT Write Read 3 (fixed) 1 Note 2 Write 0 to 2 TMC00 to TMC05 Read-modify-write Note 2 1 (fixed) A wait occurs during write CSIA0B0 to CSIA0BF, CSIA1B0 to CSIA1BF Write 0 to 18 (when performing continuous write via write instruction) 0 to 20 (when conflict occurs between write instruction and write via receive operation) 2 Note 3 2 Note 3 , I C1 IICS0, IICS1 ASIS0 to ASIS2 Read Read 1 (fixed) 1 (fixed) Asynchronous serial interfaces 0 to 2 (UART0 to UART2) Real-time output functions 0 and 1 (RTO0, RTO1) A/D converter RTBL0, RTBL1, RTBH0, RTBH1 ADM, ADS, PFM, PFT ADCR, ADCRH Write (when RTPCn.RTPOEn bit = 0) Write Read Note 4 1 1 to 2 1 to 2 Number of waits to be added = (2 + m) x k [clocks] User's Manual U16889EJ1V0UD 89 CHAPTER 3 CPU FUNCTIONS Notes 1. Only in the PD70F3218H, 70F3218HY 2. If fetched from the on-chip RAM, the number of waits is as shown above. If fetched from the external memory, the number of waits may be fewer than the number shown above. The effect of the external memory access cycle differs depending on the wait settings, etc. However, the number of waits above is the maximum value. 3. I2C0 and I2C1 are available only in the products with I2C bus (Y products). 4. In the PD70F3217H, 70F3217HY, 70F3218H, and 70F3218HY, the calculation is shown below. {(1/fXX) x 2/[(2 + m)/fCPU]} + 1 Caution When the CPU operates on the subclock and no clock is input to the X1 pin, do not access a register in which a wait occurs using an access method that causes a wait. If a wait occurs, it can only be released by a reset. Remarks 1. In the calculation for the number of waits: fCPU: CPU clock frequency m: Set value of bits 2 to 0 of the VSWC register fCLK: Internal system clock When fCLK < 16.6 MHz: m = 0 When fCLK 16.6 MHz: m = 1 2. n = 0, 1 The digits below the decimal point are truncated if less than (1/fCPU)/(2 + m) or rounded up if larger than (1/fCPU)/(2 + m) when multiplied by (1/fCPU). 90 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS 4.1 Features Input-only ports: 16 pins I/O ports: 112 pins * Fixed to N-ch open-drain output: 6 (medium: 4) * Switchable to N-ch open-drain output: 12 Input/output can be specified in 1-bit units 4.2 Basic Port Configuration The V850ES/KJ1 incorporates a total of 128 I/O port pins consisting of ports 0, 1, 3 to 9, CD, CM, CS, CT, DH, and DL (including 16 input-only port pins). The port configuration is shown below. P00 Port 0 P90 Port 9 P06 Port 1 P915 PCD0 Port CD P10 P11 P30 Port 3 PCD3 PCM0 Port CM P39 P40 Port 4 PCM5 PCS0 Port CS P42 P50 Port 5 PCS7 PCT0 Port CT P55 P60 Port 6 PCT7 PDH0 Port DH P615 P70 Port 7 PDH7 PDL0 Port DL P715 Port 8 P80 P81 PDL15 Table 4-1. Pin I/O Buffer Power Supplies Power Supply AVREF0 AVREF1 BVDD EVDD Port 7 Port 1 Port CD, port CM, port CS, port CT, port DH, port DL RESET, port 0, port 3 to port 6, port 8, port 9 Corresponding Pins User's Manual U16889EJ1V0UD 91 CHAPTER 4 PORT FUNCTIONS 4.3 Port Configuration Table 4-2. Port Configuration Item Control registers Configuration Port n register (Pn: n = 0, 1, 3 to 9, CD, CM, CS, CT, DL, DH) Port n mode register (PMn: n = 0, 1, 3 to 6, 8, 9, CD, CM, CS, CT, DL, DH) Port n mode control register (PMCn: n = 0, 3 to 6, 8, 9, CM, CS, CT, DL, DH) Port n function control register (PFCn: n = 3, 5, 6, 8, 9) Port n function register (PFn: n = 3 to 6, 8, 9) Pull-up resistor option register (PUn: n = 0, 1, 3 to 6, 8, 9) Ports Input only: 16 I/O: 112 Pull-up resistors Software control: 56 (1) Port n register (Pn) Data I/O with external devices is performed by writing to and reading from the Pn register. The Pn register is configured of a port latch that retains the output data and a circuit that reads the pin status. Each bit of the Pn register corresponds to one pin of port n and can be read or written in 1-bit units. After reset: 00HNote (output latch) 7 6 5 R/W 7 3 2 1 0 Pn Pn7 Pn6 Pn5 Pn4 Pn3 Pn2 Pn1 Pn0 Pnm 0 1 0 is output 1 is output Control of output data (in output mode) Note Input-only port pins are undefined. Writing to and reading from the Pn register is executed as follows independent of the setting of the PMCn register. Table 4-3. Reading to/Writing from Pn Register Setting of PMn Register Output mode (PMnm bit = 0) Writing to Pn Register Write to the output latch Note Reading from Pn Register The value of the output latch is read. . In the port mode (PMCnm bit = 0), the contents of the output latch are output from the pin. Input mode (PMnm bit = 1) Write to the output latch. The status of the pin is not affected Note The pin status is read. . Note The value written to the output latch is retained until a value is next written to the output latch. 92 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS (2) Port n mode register (PMn) PMn specifies the input mode/output mode of the port. Each bit of the PMn register corresponds to one pin of port n and can be specified in 1-bit units. After reset: FFH R/W PMn PMn7 PMn6 PMn5 PMn4 PMn3 PMn2 PMn1 PMn0 PMnm 0 1 Output mode Input mode Control of I/O mode (3) Port n mode control register (PMCn) PMCn specifies the port mode/alternate function. Each bit of the PMCn register corresponds to one pin of port n and can be specified in 1-bit units. After reset: 00H R/W PMCn PMCn7 PMCn6 PMCn5 PMCn4 PMCn3 PMCn2 PMCn1 PMCn0 PMCnm 0 1 Port mode Specification of operation mode Alternate function mode (4) Port n function control register (PFCn) PFCn is a register that specifies the alternate function to be used when one pin has two or more alternate functions. Each bit of the PFCn register corresponds to one pin of port n and can be specified in 1-bit units. After reset: 00H R/W PFCn PFCn7 PFCn6 PFCn5 PFCn4 PFCn3 PFCn2 PFCn1 PFCn0 PFCnm 0 1 Alternate function 1 Alternate function 2 Specification of alternate function User's Manual U16889EJ1V0UD 93 CHAPTER 4 PORT FUNCTIONS (5) Port n function control expansion register (PFCEn) PFCEn is a register that specifies the alternate function to be used when one pin has three or more alternate functions. Each bit of the PFCEn register corresponds to one pin of port n and can be specified in 1-bit units. After reset: 00H R/W PFCEn PFCEn7 PFCEn6 PFCEn5 PFCEn4 PFCEn3 PFCEn2 PFCEn1 PFCEn0 PFCn PFCn7 PFCn6 PFCn5 PFCn4 PFCn3 PFCn2 PFCn1 PFCn0 PFCEnm 0 0 1 1 PFCnm 0 1 0 1 Specification of alternate-function Alternate function 1 Alternate function 2 Alternate function 3 Alternate function 4 (6) Port n function register (PFn) PFn is a register that specifies normal output/N-ch open-drain output. Each bit of the PFn register corresponds to one pin of port n and can be specified in 1-bit units. After reset: 00H R/W PFn PFn7 PFn6 PFn5 PFn4 PFn3 PFn2 PFn1 PFn0 PFnmNote 0 1 Control of normal output/N-ch open-drain output Normal output (CMOS output) N-ch open-drain output Note The PFnm bit is valid only when the PMn.PMnm bit is 0 (output mode) regardless of the setting of the PMCn register. When the PMnm bit is 1 (input mode), the set value in the PFn register is invalid. Example <1> When the value of the PFn register is valid PFnm bit = 1 ... N-ch open-drain output is specified. PMnm bit = 0 ... Output mode is specified. PMCnm bit = 0 or 1 <2> When the value of the PFn register is invalid PFnm bit = 0 ... N-ch open-drain output is specified. PMnm bit = 1 ... Input mode is specified. PMCnm bit = 0 or 1 94 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS (7) Pull-up resistor option register (PUn) PUn is a register that specifies the connection of an on-chip pull-up resistor. Each bit of the PUn register corresponds to one pin of port n and can be specified in 1-bit units. After reset: 00H R/W PUn PUn7 PUn6 PUn5 PUn4 PUn3 PUn2 PUn1 PUn0 PUnm 0 1 Not connected Connected Control of on-chip pull-up resistor connection User's Manual U16889EJ1V0UD 95 CHAPTER 4 PORT FUNCTIONS (8) Port settings Set the ports as follows. Figure 4-1. Register Settings and Pin Functions Port mode Output mode Input mode "0" PMn register "1" Alternate function (when two alternate functions are available) "0" "0" PFCn register PMCn register Alternate function 1 Alternate function 2 "1" Alternate function (when three or more alternate functions are available) "1" Alternate function 1 Alternate function 2 Alternate function 3 (a) (b) (c) PFCEn register (d) (a) (b) (c) (d) PFCn register PFCEnm 0 0 1 1 PFCnm 0 1 0 1 Alternate function 4 Remark Switch to the alternate function using the following procedure. <1> Set the PFCn and PFCEn registers. <2> Set the PMCn register. <3> Set the INTRn or INTFn register (to specify an external interrupt pin). If the PMCn register is set first, an unintended function may be set while the PFCn and PFCEn registers are being set. 96 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS 4.3.1 Port 0 Port 0 is a 7-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 0 includes the following alternate functions. Table 4-4. Alternate-Function Pins of Port 0 Pin Name P00 P01 P02 P03 P04 P05 P06 Note 2 Pin No. 6 7 17 18 19 20 21 Alternate Function TOH0 TOH1 NMI INTP0 INTP1 INTP2 INTP3 I/O Output Output Input Input Input Input Input PULL Yes Note 1 Remark - Block Type D-2 D-2 Analog noise elimination H-1 H-1 H-1 H-1 H-1 Notes 1. Software pull-up function 2. In the PD70F3218H and 70F3218HY, care must be exercised in processing the P05 pin when reset is released. For details, refer to 4.3.1 (5) Cautions. Caution P02 to P06 have hysteresis characteristics when the alternate function is input, but not in the port mode. (1) Port 0 register (P0) After reset: 00H (output latch) R/W Address: FFFFF400H P0 0 P06 P05Note P04 P03 P02 P01 P00 P0n 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0 to 6) Note In the PD70F3218H and 70F3218HY, care must be exercised in processing the P05 pin when reset is released. For details, refer to 4.3.1 (5) Cautions. (2) Port 0 mode register (PM0) After reset: FFH R/W Address: FFFFF420H PM0 1 PM06 PM05Note PM04 PM03 PM02 PM01 PM00 PM0n 0 1 Output mode Input mode Control of I/O mode (n = 0 to 6) Note In the PD70F3218H and 70F3218HY, care must be exercised in processing the P05 pin when reset is released. For details, refer to 4.3.1 (5) Cautions. User's Manual U16889EJ1V0UD 97 CHAPTER 4 PORT FUNCTIONS (3) Port 0 mode control register (PMC0) After reset: 00H R/W Address: FFFFF440H PMC0 0 PMC06 PMC05Note PMC04 PMC03 PMC02 PMC01 PMC00 PMC06 0 1 PMC05 0 1 PMC04 0 1 PMC03 0 1 PMC02 0 1 PMC01 0 1 PMC00 0 1 I/O port TOH0 output I/O port TOH1 output I/O port NMI input I/O port INTP0 input I/O port INTP1 input I/O port INTP2 input I/O port INTP3 input Specification of P06 pin operation mode Specification of P05 pin operation mode Specification of P04 pin operation mode Specification of P03 pin operation mode Specification of P02 pin operation mode Specification of P01 pin operation mode Specification of P00 pin operation mode Note In the PD70F3218H and 70F3218HY, care must be exercised in processing the P05 pin when reset is released. For details, refer to 4.3.1 (5) Cautions. (4) Pull-up resistor option register 0 (PU0) After reset: 00H R/W Address: FFFFFC40H PU0 0 PU06 PU05Note PU04 PU03 PU02 PU01 PU00 PU0n 0 1 Control of on-chip pull-up resistor connection (n = 0 to 6) Not connected Connected Note In the PD70F3218H and 70F3218HY, care must be exercised in processing the P05 pin when reset is released. For details, refer to 4.3.1 (5) Cautions. 98 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS (5) Cautions In the PD70F3218H and 70F3218HY, perform the following operations before starting operation after reset is released. If the following operations are not performed, a normal operation is not executed. <1> Input a low level to the P05/INTP2 pin. <2> Clear the OCDM.OCDM0 bitNote to 0. Fix the P05/INTP2 pin to low-level input until the processing of <2> is completed. Note The OCDM register is as follows. After reset: 01HNote R/W Address: FFFFF9FCH <> OCDM 0 0 0 0 0 0 0 OCDM0 OCDM0 0 Operation mode Selects normal operation mode and disconnects the on-chip pull-down resistor of the P05/INTP2 pin. When P05 pin is low: Normal operation mode When P05 pin is high: RFU 1 Note RESET input sets this register to 01H. After reset by the WDTRES1 and WDTRES2 signals, however, the value of the OCDM register is retained. Caution The P05 pin of the PD70F3218H and 70F3218HY has an on-chip pull-down resistor. This resistor is disconnected when the OCDM0 flag is cleared to 0. P05 OCDM0 flag (1: Pull-down ON, 0: Pull-down OFF) 10 to 100 k (30 k (TYP.)) User's Manual U16889EJ1V0UD 99 CHAPTER 4 PORT FUNCTIONS 4.3.2 Port 1 Port 1 is a 2-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 1 includes the following alternate functions. Table 4-5. Alternate-Function Pins of Port 1 Pin Name P10 P11 3 4 Pin No. Alternate Function ANO0 ANO1 I/O Output Output PULL Yes Note Remark - Block Type A-2 A-2 Note Software pull-up function (1) Port 1 register (P1) After reset: 00H (output latch) R/W Address: FFFFF402H P1 0 0 0 0 0 0 P11 P10 P1n 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0, 1) (2) Port 1 mode register (PM1) Caution When used as the ANO0 and ANO1 pins, set PM1 = FFH all together. After reset: FFH R/W Address: FFFFF422H PM1 1 1 1 1 1 1 PM11 PM10 PM1n 0 1 Output mode Input mode Control of I/O mode (n = 0, 1) 100 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS (3) Pull-up resistor option register 1 (PU1) After reset: 00H R/W Address: FFFFFC42H PU1 0 0 0 0 0 0 PU11 PU10 PU1n 0 1 Control of on-chip pull-up resistor connection (n = 0, 1) Not connected Connected User's Manual U16889EJ1V0UD 101 CHAPTER 4 PORT FUNCTIONS 4.3.3 Port 3 Port 3 is a 10-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 3 includes the following alternate functions. Table 4-6. Alternate-Function Pins of Port 3 Pin Name P30 P31 P32 P33 Pin No. 25 26 27 28 Alternate Function TXD0 RXD0 ASCK0 TI000/TO00/TIP00 TOP00 P34 29 Note 2 Note 2 Note 2 I/O Output Input Input PULL Yes Note 1 Remark - Block Type D-2 D-1-1 D-1-2 E-6 Note 3 / I/O / G-7-1 / I/O D-1-2 Note 2 TI001/TIP01 TOP01 Note 2 Note 3 / G-7-2 I/O - - - - I/O I/O No Note 4 Note 2 P35 P36 P37 P38 P39 30 31 32 35 36 TI010/TO01 E-6 N-ch open-drain output J J K K SDA0 SCL0 Note 5 Note 5 Notes 1. Software pull-up function 2. Only in the PD70F3218H, 70F3218HY 3. Only in the PD703216, 703216Y, 703217, 703217Y, 70F3217, 70F3217Y, 70F3217H, 70F3217HY 4. An on-chip pull-up resistor can be provided by a mask option (only in the mask ROM versions). 5. Only in products with an I2C bus (Y products) Caution P31 to P35, P38, and P39 have hysteresis characteristics when the alternate function is input, but not in the port mode. 102 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS (1) Port 3 register (P3) After reset: 00H (output latch) R/W Address: P3 FFFFF406H, P3L FFFFF406H, P3H FFFFF407H 12 11 10 9 8 15 14 13 P3 (P3HNote) 0 0 0 0 0 0 P39 P38 (P3L) P37 P36 P35 P34 P33 P32 P31 P30 P3n 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0 to 9) Note When reading from or writing to bits 8 to 15 of the P3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the P3H register. Remark The P3 register can be read or written in 16-bit units. However, when the higher 8 bits and the lower 8 bits of the P3 register are used as the P3H register and as the P3L register, respectively, this register can be read or written in 8-bit or 1-bit units. (2) Port 3 mode register (PM3) After reset: FFFFH R/W Address: PM3 FFFFF426H, PM3L FFFFF426H, PM3H FFFFF427H 13 12 11 10 9 8 15 14 PM3 (PM3H Note ) 1 1 1 1 1 1 PM39 PM38 (PM3L) PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 PM3n 0 1 Output mode Input mode Control of I/O mode (n = 0 to 9) Note When reading from or writing to bits 8 to 15 of the PM3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PM3H register. Remark The PM3 register can be read or written in 16-bit units. When the higher 8 bits and the lower 8 bits of the PM3 register are used as the PM3H register and as the PM3L register, respectively, this register can be read or written in 8-bit or 1-bit units. User's Manual U16889EJ1V0UD 103 CHAPTER 4 PORT FUNCTIONS (3) Port 3 mode control register (PMC3) After reset: 0000H R/W Address: PMC3 FFFFF446H, PMC3L FFFFF446H, PMC3H FFFFF447H 13 12 11 10 9 8 15 14 PMC3 (PMC3HNote 1) 0 0 0 0 0 0 PMC39Note 2 PMC38Note 2 (PMC3L) 0 0 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 PMC39 0 1 PMC38 0 1 PMC35 0 1 PMC34 0 1 PMC33 0 1 PMC32 0 1 PMC31 0 1 PMC30 0 1 I/O port TXD0 output I/O port RXD0 input I/O port ASCK0 input I/O port I/O port I/O port I/O port SDA0 I/O I/O port SCL0 I/O Specification of P39 pin operation mode Specification of P38 pin operation mode Specification of P35 pin operation mode TI010 input/TO01 output Specification of P34 pin operation mode TI001 input/TIP01 inputNote 3/TOP01 outputNote 3 Specification of P33 pin operation mode TI000 input/TO00 output/TIP00 inputNote 3/TOP00 outputNote 3 Specification of P32 pin operation mode Specification of P31 pin operation mode Specification of P30 pin operation mode Notes 1. When reading from or writing to bits 8 to 15 of the PMC3 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PMC3H register. 2. Valid only in products with an I2C bus (Y products). In all other products, set this bit to 0. 3. Only in the PD70F3218H, 70F3218HY Remark The PMC3 register can be read or written in 16-bit units. When the higher 8 bits and the lower 8 bits of the PMC3 register are used as the PMC3H register and as the PMC3L register, respectively, this register can be read or written in 8-bit or 1-bit units. 104 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS (4) Port 3 function register H (PF3H) After reset: 00H R/W Address: FFFFFC67H PF3H 0 0 0 0 0 0 PF39 PF38 PF3n 0 1 Specification of normal port/alternate function (n = 8, 9) When used as normal port (N-ch open-drain output) When used as alternate-function (N-ch open-drain output) Caution When using P38 and P39 as N-ch open-drain-output alternate-function pins, set in the following sequence. Be sure to set the port latch to 1 before setting the pin to N-ch open-drain output. P3n bit = 1 PF3n bit = 1 PMC3n bit = 1 (5) Port 3 function control register (PFC3) (a) PD703216, 703216Y, 703217, 703217Y, 70F3217, 70F3217Y, 70F3217H, 70F3217HY After reset: 00H R/W Address: FFFFF466H PFC3 0 0 PFC35 0 PFC33 0 0 0 PFC35 0 1 PFC33 0 1 TI000 input TO00 output TI010 input TO01 output Specification of alternate-function pin of P35 pin Specification of alternate-function pin of P33 pin Caution Always clear bits 0 to 2, 4, 6, and 7 of the PFC3 register to 0. (b) PD70F3218H, 70F3218HY After reset: 00H R/W Address: FFFFF466H PFC3 0 0 PFC35 PFC34 PFC33 0 0 0 Caution Always clear bits 0 to 2, 6, and 7 of the PFC3 register to 0. Remark For details of specification of alternate-function pins, refer to 4.3.3 (8) Specifying alternate-function pins of port 3. User's Manual U16889EJ1V0UD 105 CHAPTER 4 PORT FUNCTIONS (6) Port 3 function control expansion register (PFCE3)Note Note Only in the PD70F3218H, 70F3218HY After reset: 00H R/W Address: FFFFF706H PFCE3 0 0 0 PFCE34 PFCE33 0 0 0 Remark For details of specification of alternate-function pins, refer to 4.3.3 (8) Specifying alternate-function pins of port 3. (7) Pull-up resistor option register 3 (PU3) After reset: 00H R/W Address: FFFFFC46H PU3 0 0 PU35 PU34 PU33 PU32 PU31 PU30 PU3n 0 1 Control of on-chip pull-up resistor connection (n = 0 to 5) Not connected Connected Caution An on-chip pull-up resistor can be provided for P36 to P39 by a mask option (only in the mask ROM versions). (8) Specifying alternate-function pins of port 3Note Note Only in the PD70F3218H, 70F3218HY PFC35 0 1 TI010 input TO01 output Specification of Alternate-Function Pin of P35 Pin PFCE34 0 0 1 1 PFC34 0 1 0 1 Specification of Alternate-Function Pin of P34 Pin TI001 input Setting prohibited TIP01 input TOP01 output PFCE33 0 0 1 1 PFC33 0 1 0 1 Specification of Alternate-Function Pin of P33 Pin TI000 input TO00 output TIP00 input TOP00 output 106 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS 4.3.4 Port 4 Port 4 is a 3-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 4 includes the following alternate functions. Table 4-7. Alternate-Function Pins of Port 4 Pin Name P40 P41 P42 Pin No. 22 23 24 Alternate Function SI00 SO00 SCK00 I/O Input Output I/O PULL Yes Note Remark - N-ch open-drain output can be selected. Block Type D-1-2 F-1 F-2 Note Software pull-up function Caution P40 and P42 have hysteresis characteristics when the alternate function is input, but not in the port mode. (1) Port 4 register (P4) After reset: 00H (output latch) R/W Address: FFFFF408H P4 0 0 0 0 0 P42 P41 P40 P4n 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0 to 2) (2) Port 4 mode register (PM4) After reset: FFH R/W Address: FFFFF428H PM4 1 1 1 1 1 PM42 PM41 PM40 PM4n 0 1 Output mode Input mode Control of I/O mode (n = 0 to 2) User's Manual U16889EJ1V0UD 107 CHAPTER 4 PORT FUNCTIONS (3) Port 4 mode control register (PMC4) After reset: 00H R/W Address: FFFFF448H PMC4 0 0 0 0 0 PMC42 PMC41 PMC40 PMC42 0 1 PMC41 0 1 PMC40 0 1 I/O port SI00 input I/O port SO00 output I/O port SCK00 I/O Specification of P42 pin operation mode Specification of P41 pin operation mode Specification of P40 pin operation mode (4) Port 4 function register (PF4) After reset: 00H R/W Address: FFFFFC68H PF4 0 0 0 0 0 PF42 PF41 0 PF4n 0 1 Control of normal output/N-ch open-drain output Normal output N-ch open-drain output Caution When using P41 and P42 as N-ch open-drain-output alternate-function pins, set in the following sequence. Be sure to set the port latch to 1 before setting the pin to N-ch open-drain output. P4n bit = 1 PF4n bit = 1 PMC4n bit = 1 (5) Pull-up resistor option register 4 (PU4) After reset: 00H R/W Address: FFFFFC48H PU4 0 0 0 0 0 PU42 PU41 PU40 PU4n 0 1 Control of on-chip pull-up resistor connection (n = 0 to 2) Not connected Connected 108 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS 4.3.5 Port 5 Port 5 is a 6-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 5 includes the following alternate functions. Table 4-8. Alternate-Function Pins of Port 5 Pin Name P50 P51 P52 P53 P54 P55 Pin No. 37 38 39 40 41 42 Alternate Function TI011/RTP00/KR0 TI50/RTP01/KR1 TO50/RTP02/KR2 SIA0/RTP03/KR3 SOA0/RTP04/KR4 SCKA0/RTP05/KR5 I/O I/O I/O I/O I/O I/O N-ch open-drain output can be selected. I/O PULL Yes Note Remark - Block Type E-5 E-5 E-4 E-5 G-1 G-2 Note Software pull-up function (1) Port 5 register (P5) After reset: 00H (output latch) R/W Address: FFFFF40AH P5 0 0 P55 P54 P53 P52 P51 P50 P5n 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0 to 5) (2) Port 5 mode register (PM5) After reset: FFH R/W Address: FFFFF42AH PM5 1 1 PM55 PM54 PM53 PM52 PM51 PM50 PM5n 0 1 Output mode Input mode Control of I/O mode (n = 0 to 5) User's Manual U16889EJ1V0UD 109 CHAPTER 4 PORT FUNCTIONS (3) Port 5 mode control register (PMC5) After reset: 00H R/W Address: FFFFF44AH PMC5 0 0 PMC55 PMC54 PMC53 PMC52 PMC51 PMC50 PMC55 0 1 PMC54 0 1 PMC53 0 1 PMC52 0 1 PMC51 0 1 PMC50 0 1 Specification of P55 pin operation mode I/O port/KR5 input SCKA0 I/O/RTP05 output Specification of P54 pin operation mode I/O port/KR4 input SOA0 output/RTP04 output Specification of P53 pin operation mode I/O port/KR3 input SIA0 input/RTP03 output Specification of P52 pin operation mode I/O port/KR2 input TO50 output/RTP02 output Specification of P51 pin operation mode I/O port/KR1 input TI50 input/RTP01 output Specification of P50 pin operation mode I/O port/KR0 input TI011 input/RTP00 output (4) Port 5 function register 5 (PF5) After reset: 00H R/W Address: FFFFFC6AH PF5 0 0 PF55 PF54 0 0 0 0 PF5n 0 1 Control of normal output/N-ch open-drain output (n = 4, 5) Normal output N-ch open-drain output Cautions 1. Always set bits 0 to 3, 6, and 7 of the PF5 register to 0. 2. When using P54 and P55 as N-ch open-drain-output alternate-function pins, set in the following sequence. Be sure to set the port latch to 1 before setting the pin to N-ch open-drain output. P5n bit = 1 PF5n bit = 1 PMC5n bit = 1 110 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS (5) Port 5 function control register (PFC5) After reset: 00H R/W Address: FFFFF46AH PFC5 0 0 PFC55 PFC54 PFC53 PFC52 PFC51 PFC50 PFC55 0 1 PFC54 0 1 PFC53 0 1 PFC52 0 1 PFC51 0 1 PFC50 0 1 TI011 input TI50 input TO50 output SIA0 input SOA0 output SCKA0 I/O Specification of alternate-function pin of P55 pin RTP05 output Specification of alternate-function pin of P54 pin RTP04 output Specification of alternate-function pin of P53 pin RTP03 output Specification of alternate-function pin of P52 pin RTP02 output Specification of alternate-function pin of P51 pin RTP01 output Specification of alternate-function pin of P50 pin RTP00 output (6) Pull-up resistor option register 5 (PU5) After reset: 00H R/W Address: FFFFFC4AH PU5 0 0 PU55 PU54 PU53 PU52 PU51 PU50 PU5n 0 1 Control of on-chip pull-up resistor connection (n = 0 to 5) Not connected Connected User's Manual U16889EJ1V0UD 111 CHAPTER 4 PORT FUNCTIONS 4.3.6 Port 6 Port 6 is a 16-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 6 includes the following alternate functions. Table 4-9. Alternate-Function Pins of Port 6 Pin Name P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P610 P611 P612 P613 P614 P615 Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Alternate Function RTP10 RTP11 RTP12 RTP13 RTP14 RTP15 SI02 SO02 SCK02 TI040 TI041 TO04 TI050 TI051/TO05 - - I/O Output Output Output Output Output Output Input Output I/O Input Input Output Input I/O - - No Note 2 PULL Yes Note 1 Remark - Block Type D-2 D-2 D-2 D-2 D-2 D-2 D-1-2 N-ch open-drain output F-1 F-2 - D-1-2 D-1-2 D-2 D-1-2 E-6 J J Notes 1. Software pull-up function 2. An on-chip pull-up resistor can be provided by a mask option (only in the mask ROM versions). Caution P66, P68, P69, P610, P612, and P613 have hysteresis characteristics when the alternate function is input, but not in the port mode. 112 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS (1) Port 6 register (P6) After reset: 00H (output latch) R/W Address: P6 FFFFF40CH, P6L FFFFF40CH, P6H FFFFF40DH 12 11 10 9 8 15 14 13 P6 (P6H Note ) P615 P614 P613 P612 P611 P610 P69 P68 (P6L) P67 P66 P65 P64 P63 P62 P61 P60 P6n 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0 to 15) Note When reading from or writing to bits 8 to 15 of the P6 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the P6H register. Remark The P6 register can be read or written in 16-bit units. However, when the higher 8 bits and the lower 8 bits of the P6 register are used as the P6H register and as the P6L register, respectively, this register can be read or written in 8-bit or 1-bit units. (2) Port 6 mode register (PM6) After reset: FFFFH R/W Address: PM6 FFFFF42CH, PM6L FFFFF42CH, PM6H FFFFF42DH 13 12 11 10 9 8 15 14 PM6 (PM6HNote) PM615 PM614 PM613 PM612 PM611 PM610 PM69 PM68 (PM6L) PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60 PM6n 0 1 Output mode Input mode Control of I/O mode (n = 0 to 15) Note When reading from or writing to bits 8 to 15 of the PM6 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PM6H register. Remark The PM6 register can be read or written in 16-bit units. However, when the higher 8 bits and the lower 8 bits of the PM6 register are used as the PM6H register and as the PM6L register, respectively, this register can be read or written in 8-bit or 1-bit units. User's Manual U16889EJ1V0UD 113 CHAPTER 4 PORT FUNCTIONS (3) Port 6 mode control register (PMC6) After reset: 0000H R/W Address: PMC6 FFFFF44CH, PMC6L FFFFF44CH, PMC6H FFFFF44DH 13 12 11 10 9 8 15 14 PMC6 (PMC6H Note ) 0 0 PMC613 PMC612 PMC611 PMC610 PMC69 PMC68 (PMC6L) PMC67 PMC66 PMC65 PMC64 PMC63 PMC62 PMC61 PMC60 PMC613 0 1 PMC612 0 1 PMC611 0 1 PMC610 0 1 PMC69 0 1 PMC68 0 1 PMC67 0 1 PMC66 0 1 PMC6n 0 1 I/O port RTP1n output I/O port SI02 input I/O port SO02 output I/O port SCK02 I/O I/O port TI040 input I/O port TI041 input I/O port TO04 output I/O port TI050 input I/O port Specification of P613 pin operation mode TI051 input/TO05 output Specification of P612 pin operation mode Specification of P611 pin operation mode Specification of P610 pin operation mode Specification of P69 pin operation mode Specification of P68 pin operation mode Specification of P67 pin operation mode Specification of P66 pin operation mode Specification of P6n pin operation mode (n = 0 to 5) Note When reading from or writing to bits 8 to 15 of the PMC6 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PMC6H register. Remark The PMC6 register can be read or written in 16-bit units. However, when the higher 8 bits and the lower 8 bits of the PMC6 register are used as the PMC6H register and as the PMC6L register, respectively, this register can be read or written in 8-bit or 1-bit units. 114 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS (4) Port 6 function register (PF6) After reset: 0000H R/W Address: PF6 FFFFFC6CH, PF6L FFFFFC6CH, PF6H FFFFFC6DH 13 12 11 10 9 8 15 14 PF6 (PF6H Note ) 0 0 0 0 0 0 0 PF68 (PF6L) PF67 0 0 0 0 0 0 0 PF6n 0 1 Control of normal output/N-ch open-drain output (n = 7, 8) Normal output N-ch open-drain output Note When reading from or writing to bits 8 to 15 of the PF6 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PF6H register. Caution Always set PF6 register bits 0 to 6 and 9 to 15 to 0. Remark The PF6 register can be read or written in 16-bit units. However, when the higher 8 bits and the lower 8 bits of the PF6 register are used as the PF6H register and as the PF6L register, respectively, this register can be read or written in 8-bit or 1-bit units. (5) Port 6 function control register (PFC6H) After reset: 00H R/W Address: FFFFF46DH PFC6H 0 0 PFC613 0 0 0 0 0 PFC613 0 1 TI051 input TO05 output Specification of alternate-function pin of P613 pin User's Manual U16889EJ1V0UD 115 CHAPTER 4 PORT FUNCTIONS (6) Pull-up resistor option register 6 (PU6) After reset: 0000H R/W Address: PU6 FFFFFC4CH, PU6L FFFFFC4CH, PU6H FFFFFC4DH 15 14 13 12 11 10 9 8 PU6 (PU6H Note ) 0 0 PU613 PU612 PU611 PU610 PU69 PU68 (PU6L) PU67 PU66 PU65 PU64 PU63 PU62 PU61 PU60 PU6n 0 1 Control of on-chip pull-up resistor connection (n = 0 to 13) Not connected Connected Note When reading from or writing to bits 8 to 15 of the PU6 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PU6H register. Caution An on-chip pull-up resistor can be provided for P614 and P615 (only in the mask ROM version). Remark The PU6 register can be read or written in 16-bit units. However, when the higher 8 bits and the lower 8 bits of the PU6 register are used as the PU6H register and as the PU6L register, respectively, this register can be read or written in 8-bit or 1-bit units. 116 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS 4.3.7 Port 7 Port 7 is a 16-bit input-only port for which all the pins are fixed to input. Port 7 includes the following alternate functions. Table 4-10. Alternate-Function Pins of Port 7 Pin Name P70 P71 P72 P73 P74 P77 P76 P77 P78 P79 P710 P711 P712 P713 P714 P715 Pin No. 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 Alternate Function ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 ANI12 ANI13 ANI14 ANI15 I/O Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input PULL No Note Remark - Block Type A-1 A-1 A-1 A-1 A-1 A-1 A-1 A-1 A-1 A-1 A-1 A-1 A-1 A-1 A-1 A-1 Note Software pull-up function (1) Port 7 register (P7) After reset: Undefined 15 14 R Address: P7 FFFFF40EH, P7L FFFFF40EH, P7H FFFFF40FH 13 12 11 10 9 8 P7 (P7H Note ) P715 P714 P713 P712 P711 P710 P79 P78 (P7L) P77 P76 P75 P74 P73 P72 P71 P70 P7n 0 1 Input low level Input high level Input data read (n = 0 to 15) Note When reading from bits 8 to 15 of the P7 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the P7H register. Remark The P7 register can be read only in 16-bit units. However, when the higher 8 bits of the P7 register are used as the P7H register and the lower 8 bits as the P7L register, they can be read only in 8-bit units. User's Manual U16889EJ1V0UD 117 CHAPTER 4 PORT FUNCTIONS 4.3.8 Port 8 Port 8 is a 2-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 8 includes the following alternate functions. Table 4-11. Alternate-Function Pins of Port 8 Pin Name P80 P81 Pin No. 59 60 Alternate Function RXD2/SDA1 TXD2/SCL1 Note 2 I/O I/O I/O PULL Yes Note 1 Remark N-ch open-drain output can be selected. Block Type G-5 G-6 Note 2 Notes 1. Software pull-up function 2. Only in products with an I2C bus (Y products) Caution P80 and P81 have hysteresis characteristics when the alternate function is input, but not in the port mode. (1) Port 8 register (P8) After reset: 00H (output latch) R/W Address: FFFFF410H P8 0 0 0 0 0 0 P81 P80 P8n 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0, 1) (2) Port 8 mode register (PM8) After reset: FFH R/W Address: FFFFF430H PM8 1 1 1 1 1 1 PM81 PM80 PM8n 0 1 Output mode Input mode Control of I/O mode (n = 0, 1) 118 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS (3) Port 8 mode control register (PMC8) After reset: 00H R/W Address: FFFFF450H PMC8 0 PMC81 0 1 PMC80 0 1 0 0 0 0 0 PMC81 PMC80 Specification of P81 pin operation mode I/O port TXD2 output/SCL1Note I/O Specification of P80 pin operation mode I/O port RXD2 input/SDA1Note I/O Note Only in products with an I C bus (Y products) 2 (4) Port 8 function register (PF8) After reset: 00H R/W Address: FFFFFC70H PF8 0 0 0 0 0 0 PF81 PF80 PF8n 0 1 Control of normal output/N-ch open-drain output (n = 0, 1) Normal output N-ch open-drain output Caution When using P80 and P81 as N-ch open-drain-output alternate-function pins, set in the following sequence. Be sure to set the port latch to 1 before setting the pin to N-ch open-drain output. P8n bit = 1 PFC8n bit = 0/1 PF8n bit = 1 PMC8n bit = 1 User's Manual U16889EJ1V0UD 119 CHAPTER 4 PORT FUNCTIONS (5) Port 8 function control register (PFC8) After reset: 00H R/W Address: FFFFF470H PFC8 0 0 0 0 0 0 PFC81 PFC80 PFC81 0 1 PFC80 0 1 RXD2 input SDA1Note I/O TXD2 output SCL1Note I/O Specification of alternate-function pin of P81 pin Specification of alternate-function pin of P80 pin Note Only in products with an I2C bus (Y products). Clear to 0 for all other products. (6) Pull-up resistor option register 8 (PU8) After reset: 00H R/W Address: FFFFFC50H PU8 0 0 0 0 0 0 PU81 PU80 PU8n 0 1 Control of on-chip pull-up resistor connection (n = 0, 1) Not connected Connected 120 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS 4.3.9 Port 9 Port 9 is a 16-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 9 includes the following alternate functions. Table 4-12. Alternate-Function Pins of Port 9 Pin Name P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P910 P911 P912 P913 P914 P915 Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 Alternate Function A0/TXD1/KR6 A1/RXD1/KR7 A2/TI020/TO02 A3/TI021 A4/TI030/TO03 A5/TI031 A6/TI51/TO51 A7/SI01 A8/SO01 A9/SCK01 A10/SIA1 A11/SOA1 A12/SCKA1 A13/INTP4 A14/INTP5 A15/INTP6 I/O I/O I/O I/O I/O I/O I/O I/O Output I/O I/O Output I/O I/O I/O I/O N-ch open-drain output can be specified. - N-ch open-drain output can be specified. Analog noise elimination I/O PULL No Note Remark - Block Type E-3 E-1 E-3 E-2 E-3 E-2 E-3 E-2 G-4 G-3 E-2 G-4 G-3 H-2 H-2 H-2 Note Software pull-up function Caution P93, P95, P97, P99, P910, and P912 to P915 have hysteresis characteristics when the alternate function is input, but not in the port mode. User's Manual U16889EJ1V0UD 121 CHAPTER 4 PORT FUNCTIONS (1) Port 9 register (P9) After reset: 00H (output latch) R/W Address: P9H FFFFF412H, P9L FFFFF412H, P9H FFFFF413H 12 11 10 9 8 15 14 13 P9 (P9HNote) P915 P914 P913 P912 P911 P910 P99 P98 (P9L) P97 P96 P95 P94 P93 P92 P91 P90 P9n 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0 to 15) Note When reading from or writing to bits 8 to 15 of the P9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the P9H register. Remark The P9 register can be read or written in 16-bit units. However, when the higher 8 bits and the lower 8 bits of the P9 register are used as the P9H register and as the P9L register, respectively, these registers can be read or written in 8-bit or 1-bit units. (2) Port 9 mode register (PM9) After reset: FFFFH R/W Address: PM9 FFFFF432H, PM9L FFFFF432H, PM9H FFFFF433H 13 12 11 10 9 8 15 14 PM9 (PM9H Note ) PM915 PM914 PM913 PM912 PM911 PM910 PM99 PM98 (PM9L) PM97 PM96 PM95 PM94 PM93 PM92 PM91 PM90 PM9n 0 1 Output mode Input mode Control of I/O mode (n = 0 to 5) Note When reading from or writing to bits 8 to 15 of the PM9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PM9H register. Remark The PM9 register can be read or written in 16-bit units. However, when the higher 8 bits and the lower 8 bits of the PM9 register are used as the PM9H register and as the PM9L register, respectively, this register can be read or written in 8-bit or 1-bit units. (3) Port 9 mode control register (PMC9) Caution When using port 9 as the A0 to A15 pins, set the PMC9 register to FFFFH in 16-bit units. 122 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS (1/2) After reset: 0000H R/W Address: PMC9 FFFFF452H, PMC9L FFFFF452H, PMC9H FFFFF453H 15 14 13 12 11 10 9 8 PMC9 (PMC9HNote) PMC915 PMC914 PMC913 PMC912 PMC911 PMC910 PMC99 PMC98 (PMC9L) PMC97 PMC96 PMC95 PMC94 PMC93 PMC92 PMC91 PMC90 PMC915 0 1 PMC914 0 1 PMC913 0 1 PMC912 0 1 PMC911 0 1 PMC910 0 1 PMC99 0 1 PMC98 0 1 I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port Specification of P915 pin operation mode A15 output/INTP6 input Specification of P914 pin operation mode A14 output/INTP5 input Specification of P913 pin operation mode A13 output/INTP4 input Specification of P912 pin operation mode A12 output/SCKA1 I/O Specification of P911 pin operation mode A11 output/SOA1 output Specification of P910 pin operation mode A10 output/SIA1 input Specification of P99 pin operation mode A9 output/SCK01 I/O Specification of P98 pin operation mode A8 output/SO01 output Note When reading from or writing to bits 8 to 15 of the PMC9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PMC9H register. Remark The PMC9 register can be read or written in 16-bit units. However, when the higher 8 bits and the lower 8 bits of the PMC9 register are used as the PMC9H register and as the PMC9L register, respectively, these registers can be read or written in 8-bit or 1-bit units. User's Manual U16889EJ1V0UD 123 CHAPTER 4 PORT FUNCTIONS (2/2) PMC97 0 1 PMC96 0 1 PMC95 0 1 PMC94 0 1 PMC93 0 1 PMC92 0 1 PMC91 0 1 PMC90 0 1 I/O port A3 output/TI021 input Specification of P92 pin operation mode I/O port/TI020 input A2 output/TO02 output Specification of P91 pin operation mode I/O port/KR7 input A1 output/RXD1 input Specification of P90 pin operation mode I/O port/KR6 input A0 output/TXD1 output I/O port A5 output/TI031 input Specification of P94 pin operation mode I/O port/TI030 input A4 output/TO03 output Specification of P93 pin operation mode I/O port A7 output/SI01 input Specification of P96 pin operation mode I/O port/TI51 input A6 output/TO51 output Specification of P95 pin operation mode Specification of P97 pin operation mode 124 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS (4) Port 9 function register H (PF9H) After reset: 00H R/W Address: FFFFFC73H PF9H 0 0 0 PF912 PF911 0 PF99 PF98 PF9n 0 1 Control of normal output/N-ch open-drain output (n = 0, 1, 3, 4) Normal output N-ch open-drain output Caution When using P98, P99, P911, and P912 as N-ch open-drain-output alternatefunction pins, set in the following sequence. Be sure to set the port latch to 1 before setting the pin to N-ch open-drain output. P9n bit = 1 PFC9n bit = 0/1 PF9n bit = 1 PMC9n bit = 1 (5) Port 9 function control register (PFC9) Caution When using port 9 as the A0 to A15 pins, set the PFC9 register to 0000H in 16-bit units. User's Manual U16889EJ1V0UD 125 CHAPTER 4 PORT FUNCTIONS (1/2) After reset: 0000H R/W Address: PFC9 FFFFF472H, PFC9L FFFFF472H, PFC9H FFFFF473H 13 12 11 10 9 8 15 14 PFC9 (PFC9HNote) PFC915 PFC914 PFC913 PFC912 PFC911 PFC910 PFC99 PFC98 (PFC9L) PFC97 PFC96 PFC95 PFC94 PFC93 PFC92 PFC91 PFC90 PFC915 0 1 PFC914 0 1 PFC913 0 1 PFC912 0 1 PFC911 0 1 PFC910 0 1 PFC99 0 1 PFC98 0 1 A8 output A9 output SCK01 I/O A10 output SIA1 input A11 output A12 output SCKA1 I/O A13 output INTP4 input A14 output INTP5 input A15 output INTP6 input Specification of alternate-function pin of P915 pin Specification of alternate-function pin of P914 pin Specification of alternate-function pin of P913 pin Specification of alternate-function pin of P912 pin Specification of alternate-function pin of P911 pin SOA1 output Specification of alternate-function pin of P910 pin Specification of alternate-function pin of P99 pin Specification of alternate-function pin of P98 pin SO01 output Note When reading from or writing to bits 8 to 15 of the PFC9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PFC9H register. Remark The PFC9 register can be read or written in 16-bit units. However, when the higher 8 bits and the lower 8 bits of the PFC9 register are used as the PFC9H register and as the PFC9L register, respectively, these registers can be read or written in 8-bit or 1-bit units. 126 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS (2/2) PFC97 0 1 PFC96 0 1 PFC95 0 1 PFC94 0 1 PFC93 0 1 PFC92 0 1 PFC91 0 1 PFC90 0 1 A0 output TXD1 output A1 output RXD1 input Specification of alternate-function pin of P90 pin A2 output TO02 output Specification of alternate-function pin of P91 pin A3 output TI021 input Specification of alternate-function pin of P92 pin A4 output TO03 output Specification of alternate-function pin of P93 pin A5 output TI031 input Specification of alternate-function pin of P94 pin A6 output TO51 output Specification of alternate-function pin of P95 pin A7 output SI01 input Specification of alternate-function pin of P96 pin Specification of alternate-function pin of P97 pin User's Manual U16889EJ1V0UD 127 CHAPTER 4 PORT FUNCTIONS (6) Pull-up resistor option register 9 (PU9) After reset: 0000H R/W Address: PU9 FFFFFC52H, PU9L FFFFFC52H, PU9H FFFFFC53H 13 12 11 10 9 8 15 14 PU9 (PU9H Note ) PU915 PU914 PU913 PU912 PU911 PU910 PU99 PU98 (PU9L) PU97 PU96 PU95 PU94 PU93 PU92 PU91 PU90 PU9n 0 1 Control of on-chip pull-up resistor connection (n = 0 to 15) Not connected Connected Note When reading from or writing to bits 8 to 15 of the PU9 register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PU9H register. Remark The PU9 register can be read or written in 16-bit units. However, when the higher 8 bits and the lower 8 bits of the PU9 register are used as the PU9H register and as the PU9L register, respectively, these registers can be read or written in 8-bit or 1-bit units. 128 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS 4.3.10 Port CD Port CD is a 4-bit I/O port for which I/O settings can be controlled in 1-bit units. Port CD does not have alternate-function pins. Table 4-13. Alternate-Function Pins of Port CD Pin Name PCD0 PCD1 PCD2 PCD3 Pin No. 77 78 79 80 Alternate Function - - - - I/O - - - - PULL No Note Remark - Block Type B-1 B-1 B-1 B-1 Note Software pull-up function (1) Port CD register (PCD) After reset: 00H (output latch) R/W Address: FFFFF00EH PCD 0 0 0 0 PCD3 PCD2 PCD1 PCD0 PCDn 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0 to 3) (2) Port CD mode register (PMCD) After reset: FFH R/W Address: FFFFF02EH PMCD 1 1 1 1 PMCD3 PMCD2 PMCD1 PMCD0 PMCDn 0 1 Output mode Input mode Control of I/O mode (n = 0 to 3) User's Manual U16889EJ1V0UD 129 CHAPTER 4 PORT FUNCTIONS 4.3.11 Port CM Port CM is a 6-bit I/O port for which I/O settings can be controlled in 1-bit units. Port CM includes the following alternate functions. Table 4-14. Alternate-Function Pins of Port CM Pin Name PCM0 PCM1 PCM2 PCM3 PCM4 PCM5 Pin No. 85 86 87 88 89 90 Alternate Function WAIT CLKOUT HLDAK HLDRQ - - I/O Input Output Output Input - - PULL No Note Remark - Block Type C-1 C-2 C-2 C-1 B-1 B-1 Note Software pull-up function (1) Port CM register (PCM) After reset: 00H (output latch) R/W Address: FFFFF00CH PCM 0 0 PCM5 PCM4 PCM3 PCM2 PCM1 PCM0 PCMn 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0 to 5) (2) Port CM mode register (PMCM) After reset: FFH R/W Address: FFFFF02CH PMCM 1 1 PMCM5 PMCM4 PMCM3 PMCM2 PMCM1 PMCM0 PMCMn 0 1 Output mode Input mode Control of I/O mode (n = 0 to 5) 130 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS (3) Port CM mode control register (PMCCM) After reset: 00H R/W Address: FFFFF04CH PMCCM 0 0 0 0 PMCCM3 PMCCM2 PMCCM1 PMCCM0 PMCCM3 0 1 PMCCM2 0 1 PMCCM1 0 1 PMCCM0 0 1 I/O port WAIT input I/O port CLKOUT output I/O port HLDAK output I/O port HLDRQ input Specification of PCM3 pin operation mode Specification of PCM2 pin operation mode Specification of PCM1 pin operation mode Specification of PCM0 pin operation mode User's Manual U16889EJ1V0UD 131 CHAPTER 4 PORT FUNCTIONS 4.3.12 Port CS Port CS is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. Port CS includes the following alternate functions. Table 4-15. Alternate-Function Pins of Port CS Pin Name PCS0 PCS1 PCS2 PCS3 PCS4 PCS5 PCS6 PCS7 Pin No. 81 82 83 84 91 92 93 94 Alternate Function CS0 CS1 CS2 CS3 - - - - I/O Output Output Output Output - - - - PULL No Note Remark - Block Type C-3 C-3 C-3 C-3 B-1 B-1 B-1 B-1 Note Software pull-up function (1) Port CS register (PCS) After reset: 00H (output latch) R/W Address: FFFFF008H PCS PCS7 PCS6 PCS5 PCS4 PCS3 PCS2 PCS1 PCS0 PCSn 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0 to 7) (2) Port CS mode register (PMCS) After reset: FFH R/W Address: FFFFF028H PMCS PMCS7 PMCS6 PMCS5 PMCS4 PMCS3 PMCS2 PMCS1 PMCS0 PMCSn 0 1 Output mode Input mode Control of I/O mode (n = 0 to 7) 132 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS (3) Port CS mode control register (PMCCS) After reset: 00H R/W Address: FFFFF048H PMCCS 0 0 0 0 PMCCS3 PMCCS2 PMCCS1 PMCCS0 PMCCSn 0 1 I/O port Specification of PCSn pin operation mode (n = 0 to 3) CSn output User's Manual U16889EJ1V0UD 133 CHAPTER 4 PORT FUNCTIONS 4.3.13 Port CT Port CT is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. Port CT includes the following alternate functions. Table 4-16. Alternate-Function Pins of Port CT Pin Name PCT0 PCT1 PCT2 PCT3 PCT4 PCT5 PCT6 PCT7 Pin No. 95 96 97 98 99 100 101 102 ASTB - RD - Alternate Function WR0 WR1 - - I/O Output Output - - Output - Output - PULL No Note Remark - Block Type C-3 C-3 B-1 B-1 C-3 B-1 C-3 B-1 Note Software pull-up function (1) Port CT register (PCT) After reset: 00H (output latch) R/W Address: FFFFF00AH PCT PCT7 PCT6 PCT5 PCT4 PCT3 PCT2 PCT1 PCT0 PCTn 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0 to 7) (2) Port CT mode register (PMCT) After reset: FFH R/W Address: FFFFF02AH PMCT PMCT7 PMCT6 PMCT5 PMCT4 PMCT3 PMCT2 PMCT1 PMCT0 PMCTn 0 1 Output mode Input mode Control of I/O mode (n = 0 to 7) 134 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS (3) Port CT mode control register (PMCCT) After reset: 00H R/W Address: FFFFF04AH PMCCT 0 PMCCT6 0 PMCCT4 0 0 PMCCT1 PMCCT0 PMCCT6 0 1 PMCCT4 0 1 PMCCT1 0 1 PMCCT0 0 1 I/O port WR0 output I/O port WR1 output I/O port RD output I/O port ASTB output Specification of PCT6 pin operation mode Specification of PCT4 pin operation mode Specification of PCT1 pin operation mode Specification of PCT0 pin operation mode User's Manual U16889EJ1V0UD 135 CHAPTER 4 PORT FUNCTIONS 4.3.14 Port DH Port DH is an 8-bit I/O port for which I/O settings can be controlled in 1-bit units. Port DH includes the following alternate functions. Table 4-17. Alternate-Function Pins of Port DH Pin Name PDH0 PDH1 PDH2 PDH3 PDH4 PDH5 PDH6 PDH7 Pin No. 121 122 123 124 125 126 127 128 Alternate Function A16 A17 A18 A19 A20 A21 A22 A23 I/O Output Output Output Output Output Output Output Output PULL No Note Remark - Block Type C-3 C-3 C-3 C-3 C-3 C-3 C-3 C-3 Note Software pull-up function (1) Port DH register (PDH) After reset: 00H (output latch) R/W Address: FFFFF006H PDH PDH7 PDH6 PDH5 PDH4 PDH3 PDH2 PDH1 PDH0 PDHn 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0 to 7) (2) Port DH mode register (PMDH) After reset: FFH R/W Address: FFFFF026H PMDH PMDH7 PMDH6 PMDH5 PMDH4 PMDH3 PMDH2 PMDH1 PMDH0 PMDHn 0 1 Output mode Input mode Control of I/O mode (n = 0 to 7) 136 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS (3) Port DH mode control register (PMCDH) After reset: 00H R/W Address: FFFFF046H PMCDH PMCDH7 PMCDH6 PMCDH5 PMCDH4 PMCDH3 PMCDH2 PMCDH1 PMCDH0 PMCDHn 0 1 I/O port Specification of PDHn pin operation mode (n = 0 to 7) Am output (address bus output) (m = 16 to 23) Caution When specifying the port/alternate function for each bit, pay careful attention to the operation of the alternate functions. User's Manual U16889EJ1V0UD 137 CHAPTER 4 PORT FUNCTIONS 4.3.15 Port DL Port DL is a 16-bit I/O port for which I/O settings can be controlled in 1-bit units. Port DL includes the following alternate functions. Table 4-18. Alternate-Function Pins of Port DL Pin Name PDL0 PDL1 PDL2 PDL3 PDL4 PDL5 PDL6 PDL7 PDL8 PDLDL PDL10 PDL11 PDL12 PDL13 PDL14 PDL15 Pin No. 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Alternate Function AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PULL No Note Remark - Block Type C-4 C-4 C-4 C-4 C-4 C-4 C-4 C-4 C-4 C-4 C-4 C-4 C-4 C-4 C-4 C-4 Note Software pull-up function 138 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS (1) Port DL register (PDL) After reset: 00H (output latch) R/W Address: PDL FFFFF004H, PDLL FFFFF004H, PDLH FFFFF005H 12 11 10 9 8 15 14 13 PDL (PDLH Note ) PDL15 PDL14 PDL13 PDL12 PDL11 PDL10 PDL9 PDL8 (PDLL) PDL7 PDL6 PDL5 PDL4 PDL3 PDL2 PDL1 PDL0 PDLn 0 1 0 is output 1 is output Control of output data (in output mode) (n = 0 to 15) Note When reading from or writing to bits 8 to 15 of the PDL register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PDLH register. Remark The PDL register can be read or written in 16-bit units. However, when the higher 8 bits and the lower 8 bits of the PDL register are used as the PDLH register and as the PDLL register, respectively, these registers can be read or written in 8-bit or 1-bit units. (2) Port DL mode register (PMDL) After reset: FFFFH R/W Address: PMDL FFFFF024H, PMDLL FFFFF024H, PMDLH FFFFF025H 13 12 11 10 9 8 15 14 PMDL (PMDLH Note ) PMDL15 PMDL14 PMDL13 PMDL12 PMDL11 PMDL10 PMDL9 PMDL8 (PMDLL) PMDL7 PMDL6 PMDL5 PMDL4 PMDL3 PMDL2 PMDL1 PMDL0 PMDLn 0 1 Output mode Input mode Control of I/O mode (n = 0 to 15) Note When reading from or writing to bits 8 to 15 of the PMDL register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PMDLH register. Remark The PMDL register can be read or written in 16-bit units. However, when the higher 8 bits and the lower 8 bits of the PMDL register are used as the PMDLH register and as the PMDLL register, respectively, these registers can be read or written in 8-bit or 1-bit units. User's Manual U16889EJ1V0UD 139 CHAPTER 4 PORT FUNCTIONS (3) Port DL mode control register (PMCDL) After reset: 0000H R/W Address: PMCDL FFFFF044H, PMCDLL FFFFF044H, PMCDLH FFFFF045H 15 14 13 12 11 10 9 8 PMCDL (PMCDLH Note ) PMCDL15 PMCDL14 PMCDL13 PMCDL12 PMCDL11PMCDL10 PMCDL9 PMCDL8 (PMCDLL) PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0 PMCDLn 0 1 I/O port Specification of PDLn pin operation mode (n = 0 to 15) ADn I/O (address/data bus I/O) Note When reading from or writing to bits 8 to 15 of the PMCDL register in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the PMCDLH register. Caution When specifying the port/alternate function for each bit, pay careful attention to the operation of the alternate functions. Remark The PMCDL register can be read or written in 16-bit units. However, when the higher 8 bits and the lower 8 bits of the PMCDL register are used as the PMCDLH register and as the PMCDLL register, respectively, these registers can be read or written in 8-bit or 1-bit units. 140 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS 4.4 Block Diagrams Figure 4-2. Block Diagram of Type A-1 Internal bus Pmn RD A/D input signal P-ch N-ch Figure 4-3. Block Diagram of Type A-2 AVREF1 WRPU PUmn WRPM P-ch PMmn WRPORT Internal bus Output latch (Pmn) Pmn Selector Address RD DAM.DACEn bit D/A output signal Selector P-ch N-ch User's Manual U16889EJ1V0UD 141 CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of Type B-1 WRPM PMmn WRPORT Output latch (Pmn) Pmn Internal bus Selector Address RD 142 User's Manual U16889EJ1V0UD Selector CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of Type C-1 WRPMC PMCmn WRPM PMmn Internal bus WRPORT Output latch (Pmn) Pmn Selector Address RD Input signal of alternate-function 1 Selector User's Manual U16889EJ1V0UD 143 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of Type C-2 WRPMC PMCmn WRPM PMmn Internal bus Selector WRPORT Output signal of alternate-function 1 Pmn Output latch (Pmn) Selector Address RD 144 User's Manual U16889EJ1V0UD Selector CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of Type C-3 Output buffer off signal WRPMC PMCmn WRPM PMmn Internal bus Selector WRPORT Output signal of alternate-function 1 Output latch (Pmn) Pmn Selector Address RD Remark Output buffer off signal: Signal that is asserted in the IDLE or STOP mode, or when the bus is held. Selector User's Manual U16889EJ1V0UD 145 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of Type C-4 WRPMC Output buffer off signal Output enable signal of alternate-function 1 PMCmn WRPM PMmn Internal bus Selector WRPORT Output signal of alternate-function 1 Output latch (Pmn) Pmn Selector Address Input enable signal of alternate-function 1 RD Input signal of alternate-function 1 Remark Output buffer off signal: Signal that is asserted in the IDLE or STOP mode, or when the bus is held. 146 User's Manual U16889EJ1V0UD Selector CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of Type D-1-1 EVDD WRPU PUmn WRPMC P-ch PMCmn WRPM Internal bus PMmn WRPORT Output latch (Pmn) Pmn Selector Selector Note Address RD Input signal of alternate-function 1 Note There are no hysteresis characteristics in the port mode. User's Manual U16889EJ1V0UD 147 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of Type D-1-2 EVDD WRPU PUmn WRPMC P-ch PMCmn WRPM Internal bus PMmn WRPORT Output latch (Pmn) Pmn Selector Selector Note Address RD Input signal of alternate-function 1 Note There are no hysteresis characteristics in the port mode. 148 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of Type D-2 EVDD WRPU PUmn WRPMC P-ch PMCmn WRPM Internal bus PMmn Selector WRPORT Output signal of alternate-function 1 Output latch (Pmn) Pmn Selector Address RD Selector User's Manual U16889EJ1V0UD 149 CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of Type E-1 EVDD WRPU PUmn P-ch WRPFC Output buffer off signal PFCmn WRPMC PMCmn Internal bus WRPM PMmn WRPORT Output signal of alternate-function 1 Output latch (Pmn) Selector Pmn Selector RD Address Input signal of alternate-function 2 Alternate-function input signal in port mode Remark Output buffer off signal: Signal that is asserted in the IDLE or STOP mode, or when the bus is held. 150 User's Manual U16889EJ1V0UD Selector CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of Type E-2 EVDD WRPU PUmn P-ch WRPFC Output buffer off signal PFCmn WRPMC PMCmn Internal bus WRPM PMmn WRPORT Output signal of alternate-function 1 Output latch (Pmn) Selector Pmn Selector Selector Note RD Address Input signal of alternate-function 2 Note There are no hysteresis characteristics in the port mode. Remark Output buffer off signal: Signal that is asserted in the IDLE or STOP mode, or when the bus is held. User's Manual U16889EJ1V0UD 151 CHAPTER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of Type E-3 EVDD WRPU PUmn Output buffer off signal WRPFC P-ch PFCmn WRPMC PMCmn Internal bus WRPM PMmn Output signal of alternate-function 2 Output signal of WRPORT alternate-function 1 Output latch (Pmn) Selector Selector Pmn Selector RD Address Alternate-function input signal in port mode Remark Output buffer off signal: Signal that is asserted in the IDLE or STOP mode, or when the bus is held. 152 User's Manual U16889EJ1V0UD Selector CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of Type E-4 EVDD WRPU PUmn WRPFC P-ch PFCmn WRPMC PMCmn WRPM Internal bus PMmn Selector WRPORT Selector Output signal of alternate-function 2 Output signal of alternate-function 1 Pmn Output latch (Pmn) Selector RD Address Alternate-function input signal in port mode Selector User's Manual U16889EJ1V0UD 153 CHAPTER 4 PORT FUNCTIONS Figure 4-16. Block Diagram of Type E-5 EVDD WRPU PUmn WRPFC P-ch PFCmn WRPMC PMCmn WRPM Internal bus PMmn Selector Output signal of WRPORT alternate-function 2 Pmn Output latch (Pmn) Selector RD Address Input signal of alternate-function 1 Alternate-function input signal in port mode 154 User's Manual U16889EJ1V0UD Selector CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of Type E-6 EVDD WRPU PUmn WRPFC P-ch PFCmn WRPMC PMCmn WRPM Internal bus PMmn WRPORT Selector Output signal of alternate-function 2 Output latch (Pmn) Pmn Selector Selector Note Address RD Input signal of alternate-function 1 Note There are no hysteresis characteristics in the port mode. User's Manual U16889EJ1V0UD 155 CHAPTER 4 PORT FUNCTIONS Figure 4-18. Block Diagram of Type F-1 EVDD WRPU PUmn WRPF P-ch PFmn WRPMC PMCmn Internal bus WRPM PMmn EVDD WRPORT Selector Output signal of alternate-function 1 Output latch (Pmn) P-ch Pmn N-ch Selector Selector EVSS Address RD 156 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-19. Block Diagram of Type F-2 EVDD WRPU PUmn WRPF P-ch PFmn WRPMC Output enable signal of alternate-function 1 PMCmn WRPM PMmn Internal bus EVDD WRPORT Selector Output signal of alternate-function 1 Output latch (Pmn) P-ch Pmn N-ch Selector Selector Note EVSS Address Output enable signal of alternate-function 1 RD Input signal of alternate-function 1 Note There are no hysteresis characteristics in the port mode. User's Manual U16889EJ1V0UD 157 CHAPTER 4 PORT FUNCTIONS Figure 4-20. Block Diagram of Type G-1 EVDD WRPU PUmn WRPF P-ch PFmn WRPFC PFCmn WRPMC PMCmn Internal bus WRPM PMmn EVDD Output signal of alternate-function 2 WRPORT Output signal of alternate-function 1 Output latch (Pmn) Selector Selector P-ch Pmn N-ch Selector Selector EVSS RD Address Alternate-function input signal in port mode 158 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-21. Block Diagram of Type G-2 EVDD WRPU PUmn WRPF P-ch PFmn WRPFC Output enable signal of alternate-function 1 PFCmn WRPMC Internal bus PMCmn WRPM PMmn EVDD Output signal of alternate-function 2 WRPORT Output signal of alternate-function 1 Output latch (Pmn) Selector Selector P-ch Pmn N-ch Selector Selector EVSS RD Address Output enable signal of alternate-function 1 Input signal of alternate-function 1 Alternate-function input signal in port mode User's Manual U16889EJ1V0UD 159 CHAPTER 4 PORT FUNCTIONS Figure 4-22. Block Diagram of Type G-3 EVDD WRPU PUmn WRPF P-ch PFmn Output buffer off signal Output enable signal of alternate-function 2 WRPFC PFCmn WRPMC Internal bus PMCmn WRPM PMmn EVDD Output signal of alternate-function 2 WRPORT Output signal of alternate-function 1 Output latch (Pmn) Selector Selector P-ch Pmn N-ch Selector EVSS Selector Note Address Output enable signal of alternate-function 2 RD Input signal of alternate-function 2 Note There are no hysteresis characteristics in the port mode. Remark Output buffer off signal: Signal that is asserted in the IDLE or STOP mode, or when the bus is held. 160 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-23. Block Diagram of Type G-4 EVDD WRPU PUmn WRPF P-ch PFmn WRPFC Output buffer off signal PFCmn WRPMC PMCmn WRPM Internal bus PMmn EVDD Selector WRPORT Output signal of alternate-function 1 Output latch (Pmn) Selector Output signal of alternate-function 2 P-ch Pmn N-ch Selector Selector EVSS Address RD Remark Output buffer off signal: Signal that is asserted in the IDLE or STOP mode, or when the bus is held. User's Manual U16889EJ1V0UD 161 CHAPTER 4 PORT FUNCTIONS Figure 4-24. Block Diagram of Type G-5 EVDD WRPU PUmn WRPF P-ch PFmn WRPFC PFCmn WRPMC Internal bus PMCmn WRPM EVDD PMmn Output signal of WRPORT alternate-function 2 Selector P-ch Pmn N-ch Output latch (Pmn) Selector EVSS Selector Note Address RD Input signal of alternate-function 1 Input signal of alternate-function 2 Note There are no hysteresis characteristics in the port mode. 162 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-25. Block Diagram of Type G-6 EVDD WRPU PUmn WRPF P-ch PFmn WRPFC PFCmn WRPMC Internal bus PMCmn WRPM PMmn EVDD Output signal of alternate-function 2 WRPORT Output signal of alternate-function 1 Output latch (Pmn) Selector Selector P-ch Pmn N-ch Selector EVSS Selector Note Address RD Input signal of alternate-function 2 Note There are no hysteresis characteristics in the port mode. User's Manual U16889EJ1V0UD 163 CHAPTER 4 PORT FUNCTIONS Figure 4-26. Block Diagram of Type G-7-1 EVDD WRPU PUmn WRPFCE P-ch PFCEmn WRPFC PFCmn WRPMC PMCmn Internal bus WRPM PMmn Output signal of alternate-function 4 WRPORT Output signal of alternate-function 2 Output latch (Pmn) Selector Selector Pmn Selector Selector Note Address RD Input signal of alternate-function 1 Input signal of alternate-function 3 Note There are no hysteresis characteristics in the port mode. 164 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-27. Block Diagram of Type G-7-2 EVDD WRPU PUmn WRPFCE P-ch PFCEmn WRPFC PFCmn WRPMC PMCmn Internal bus WRPM PMmn WRPORT Selector Output signal of alternate-function 4 Output latch (Pmn) Pmn Selector Selector Note Address RD Input signal of alternate-function 1 Input signal of alternate-function 3 Note There are no hysteresis characteristics in the port mode. User's Manual U16889EJ1V0UD 165 CHAPTER 4 PORT FUNCTIONS Figure 4-28. Block Diagram of Type H-1 EVDD WRPU PUmn WRINTR P-ch INTRmnNote 1 WRINTF INTFmnNote 1 WRPMC Internal bus PMCmn WRPM PMmn WRPORT Output latch (Pmn) Pmn Selector Selector Note 2 Address RD Input signal of alternate-function 1 Detection of noise elimination edge Notes 1. Refer to 20.4 External Interrupt Request Input Pins (NMI, INTP0 to INTP6). 2. There are no hysteresis characteristics in the port mode. 166 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-29. Block Diagram of Type H-2 EVDD WRPU PUmn WRINTR P-ch INTRmnNote 1 WRINTF INTFmnNote 1 WRPFC Output buffer off signal PFCmn Internal bus WRPMC PMCmn WRPM PMmn Selector WRPORT Output signal of alternate-function 1 Output latch (Pmn) Pmn Selector Selector Note 2 Address RD Input signal of alternate-function 2 Detection of noise elimination edge Notes 1. Refer to 20.4 External Interrupt Request Input Pins (NMI, INTP0 to INTP6). 2. There are no hysteresis characteristics in the port mode. User's Manual U16889EJ1V0UD 167 CHAPTER 4 PORT FUNCTIONS Figure 4-30. Block Diagram of Type J WRPM Mask option EVDD PMmn WRPORT Output latch (Pmn) Internal bus Pmn N-ch EVSS EVDD Selector Selector P-ch Medium-voltage input buffer Address RD 168 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-31. Block Diagram of Type K WRPF PFmn WRPMC PMCmn WRPM EVDD Internal bus PMmn Mask Option Pmn Selector WRPORT Output signal of alternate-function 1 Output latch (Pmn) N-ch EVSS Selector Selector Note Address RD Input signal of alternate-function 1 Note There are no hysteresis characteristics in the port mode. User's Manual U16889EJ1V0UD 169 CHAPTER 4 PORT FUNCTIONS 4.5 Port Register Setting When Alternate Function Is Used Table 4-19 shows the port register settings when each port is used for an alternate function. When using a port pin as an alternate-function pin, refer to description of each pin. 170 User's Manual U16889EJ1V0UD Table 4-19. Settings When Port Pins Are Used for Alternate Functions (1/7) Pin Name Alternate Function Function Name P00 P01 P02 P03 P04 P05 P06 P10 User's Manual U16889EJ1V0UD Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of Other Bits (Registers) I/O Output Output Input Input Input Input Input Output Output Output Input Input Input Output Input Output Input Input Output Input Output P00 = Setting not required P01 = Setting not required P02 = Setting not required P03 = Setting not required P04 = Setting not required P05 = Setting not required P06 = Setting not required P10 = Setting not required P11 = Setting not required P30 = Setting not required P31 = Setting not required P32 = Setting not required P33 = Setting not required P33 = Setting not required P33 = Setting not required P33 = Setting not required P34 = Setting not required P34 = Setting not required P34 = Setting not required P35 = Setting not required P35 = Setting not required P38 = 1 P39 = 1 PM00 = Setting not required PM01 = Setting not required PM02 = Setting not required PM03 = Setting not required PM04 = Setting not required PM05 = Setting not required PM06 = Setting not required PM10 = 1 PM11 = 1 Note 1 PMCn Register PFCn Register PMC00 = 1 PMC01 = 1 PMC02 = 1 PMC03 = 1 PMC04 = 1 PMC05 = 1 PMC06 = 1 - - PMC30 = 1 PMC31 = 1 PMC32 = 1 PMC33 = 1 PMC33 = 1 PMC33 = 1 PMC33 = 1 PMC34 = 1 PMC34 = 1 PMC34 = 1 PMC35 = 1 PMC35 = 1 PMC38 = 1 PMC39 = 1 - - - - - - - - - - - - PFC33 = 0 PFC33 = 1 PFC33 = 0 PFC33 = 1 PFC34 = 0 PFC34 = 0 PFC34 = 1 PFC35 = 0 PFC35 = 1 - - PF38 (PF3) = 1 PF39 (PF3) = 1 Note 2 TOH0 TOH1 NMI INTP0 INTP1 INTP2 INTP3 ANO0 ANO1 TXD0 RXD0 ASCK0 TI000 TO00 TIP00Note 2 TOP00 Note 2 - - - - - - - - - - - - PFCE33 (PFCE3) = 0Note 2 PFCE33 (PFCE3) = 0Note 2 PFCE33 (PFCE3) = 1 PFCE33 (PFCE3) = 1 PFCE34 (PFCE3) = 0Note 2 PFCE34 (PFCE3) = 1 PFCE34 (PFCE3) = 1 - - CHAPTER 4 PORT FUNCTIONS P11 P30 P31 P32 P33 Note 1 PM30 = Setting not required PM31 = Setting not required PM32 = Setting not required PM33 = Setting not required PM33 = Setting not required PM33 = Setting not required PM33 = Setting not required PM34 = Setting not required PM34 = Setting not required PM34 = Setting not required PM35 = Setting not required PM35 = Setting not required PM38 = Setting not required PM39 = Setting not required P34 TI001 TIP01Note 2 TOP01 Note 2 P35 TI010 TO01 P38 P39 SDA0 SCL0 Note 3 I/O I/O Note 3 Notes 1. When setting the ANO0 and ANO1 pins, set PM1 register = FFH all together. 2. Only in the PD70F3218H, 70F3218HY 3. Only in products with an I C bus (Y products) 2 171 172 Pin Name Alternate Function Function Name P40 P41 P42 P50 SI00 SO00 SCK00 TI011 RTP00 KR0 P51 User's Manual U16889EJ1V0UD Table 4-19. Settings When Port Pins Are Used for Alternate Functions (2/7) Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of Other Bits (Registers) I/O Input Output I/O Input Output Input Input Output Input Output Output Input Input Output Input Output Output Input I/O Output Input P40 = Setting not required P41 = Setting not required P42 = Setting not required P50 = Setting not required P50 = Setting not required P50 = Setting not required P51 = Setting not required P51 = Setting not required P51 = Setting not required P52 = Setting not required P52 = Setting not required P52 = Setting not required P53 = Setting not required P53 = Setting not required P53 = Setting not required P54 = Setting not required P54 = Setting not required P54 = Setting not required P55 = Setting not required P55 = Setting not required P55 = Setting not required PM40 = Setting not required PM41 = Setting not required PM42 = Setting not required PM50 = Setting not required PM50 = Setting not required PM50 = 1 PM51 = Setting not required PM51 = Setting not required PM51 = 1 PM52 = Setting not required PM52 = Setting not required PM52 = 1 PM53 = Setting not required PM53 = Setting not required PM53 = 1 PM54 = Setting not required PM54 = Setting not required PM54 = 1 PM55 = Setting not required PM55 = Setting not required PM55 = 1 PMCn Register PFCn Register PMC40 = 1 PMC41 = 1 PMC42 = 1 PMC50 = 1 PMC50 = 1 PMC50 = 0 PMC51 = 1 PMC51 = 1 PMC51 = 0 PMC52 = 1 PMC52 = 1 PMC52 = 0 PMC53 = 1 PMC53 = 1 PMC53 = 0 PMC54 = 1 PMC54 = 1 PMC54 = 0 PMC55 = 1 PMC55 = 1 PMC55 = 0 - - - PFC50 = 0 PFC50 = 1 PFC50 = 0 PFC51 = 0 PFC51 = 1 PFC51 = 0 PFC52 = 0 PFC52 = 1 PFC52 = 0 PFC53 = 0 PFC53 = 1 PFC53 = 0 PFC54 = 0 PFC54 = 1 PFC54 = 0 PFC55 = 0 PFC55 = 1 PFC55 = 0 KRM3 (KRM) = 1 PF54 (PF5) = Don't care PF54 (PF5) = 0 PF54 (PF5) = 0, KRM4 (KRM) = 1 PF55 (PF5) = Don't care PF55 (PF5) = 0 PF55 (PF5) = 0, KRM5 (KRM) = 1 KRM2 (KRM) = 1 - - KRM1 (KRM) = 1 - - KRM0 (KRM) = 1 - CHAPTER 4 PORT FUNCTIONS - - PF41 (PF4) = Don't care PF42 (PF4) = Don't care - - TI50 RTP01 KR1 P52 TO50 RTP02 KR2 P53 SIA0 RTP03 KR3 P54 SOA0 RTP04 KR4 P55 SCKA0 RTP05 KR5 Table 4-19. Settings When Port Pins Are Used for Alternate Functions (3/7) Pin Name Alternate Function Function Name P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P610 P611 P612 P613 User's Manual U16889EJ1V0UD Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of Other Bits (Registers) I/O Output Output Output Output Output Output Input Output I/O Input Input Output Input Input Output P60 = Setting not required P61 = Setting not required P62 = Setting not required P63 = Setting not required P64 = Setting not required P65 = Setting not required P66 = Setting not required P67 = Setting not required P68 = Setting not required P69 = Setting not required P610 = Setting not required P611 = Setting not required P612 = Setting not required P613 = Setting not required P613 = Setting not required PM60 = Setting not required PM61 = Setting not required PM62 = Setting not required PM63 = Setting not required PM64 = Setting not required PM65 = Setting not required PM66 = Setting not required PM67 = Setting not required PM68 = Setting not required PM69 = Setting not required PM610 = Setting not required PM611 = Setting not required PM612 = Setting not required PM613 = Setting not required PM613 = Setting not required PMCn Register PFCn Register PMC60 = 1 PMC61 = 1 PMC62 = 1 PMC63 = 1 PMC64 = 1 PMC65 = 1 PMC66 = 1 PMC67 = 1 PMC68 = 1 PMC69 = 1 PMC610 = 1 PMC611 = 1 PMC612 = 1 PMC613 = 1 PMC613 = 1 - - - - - - - - - - - - - PFC613 = 0 PFC613 = 1 - - - - - - - CHAPTER 4 PORT FUNCTIONS PF67 (PF6) = Don't care PF68 (PF6) = Don't care - - - - - - RTP10 RTP11 RTP12 RTP13 RTP14 RTP15 SI02 SO02 SCK02 TI040 TI041 TO04 TI050 TI051 TO05 173 174 Pin Name Alternate Function Function Name P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P710 P711 P712 P713 P714 P715 P80 User's Manual U16889EJ1V0UD Table 4-19. Settings When Port Pins Are Used for Alternate Functions (4/7) Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of Other Bits (Registers) I/O Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input I/O Output I/O 2 PMCn Register PFCn Register P70 = Setting not required P71 = Setting not required P72 = Setting not required P73 = Setting not required P74 = Setting not required P75 = Setting not required P76 = Setting not required P77 = Setting not required P78 = Setting not required P79 = Setting not required P710 = Setting not required P711 = Setting not required P712 = Setting not required P713 = Setting not required P714 = Setting not required P715 = Setting not required P80 = Setting not required P80 = Setting not required P81 = Setting not required P81 = Setting not required - - - - - - - - - - - - - - - - PM80 = Setting not required PM80 = Setting not required PM81 = Setting not required PM81 = Setting not required - - - - - - - - - - - - - - - - PMC80 = 1 PMC80 = 1 PMC81 = 1 PMC81 = 1 - - - - - - - - - - - - - - - - PFC80 = 0 PFC80 = 1 PFC81 = 0 PFC81 = 1 PF80 (PF8) = 0 PF80 (PF8) = 1 PF80 (PF8) = 0 PF81 (PF8) = 1 - - - - - - - CHAPTER 4 PORT FUNCTIONS - - - - - - - - - ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 ANI12 ANI13 ANI14 ANI15 RXD2 SDA1 Note P81 TXD2 SCL1 Note Note Only in products with an I C bus (Y products) Table 4-19. Settings When Port Pins Are Used for Alternate Functions (5/7) Pin Name Alternate Function Function Name P90 A0 TXD1 KR6 P91 A1 RXD1 KR7 P92 A2 TI020 User's Manual U16889EJ1V0UD Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of Other Bits (Registers) I/O Output Output Input Output Input Input Output Input Output Output Input Output Input Output Output Input Output Input Output Output Input Output Output Output I/O P90 = Setting not required P90 = Setting not required P90 = Setting not required P91 = Setting not required P91 = Setting not required P91 = Setting not required P92 = Setting not required P92 = Setting not required P92 = Setting not required P93 = Setting not required P93 = Setting not required P94 = Setting not required P94 = Setting not required P94 = Setting not required P95 = Setting not required P95 = Setting not required P96 = Setting not required P96 = Setting not required P96 = Setting not required P97 = Setting not required P97 = Setting not required P98 = Setting not required P98 = Setting not required P99 = Setting not required P99 = Setting not required PM90 = Setting not required PM90 = Setting not required PM90 = 1 PM91 = Setting not required PM91 = Setting not required PM91 = 1 PM92 = Setting not required PM92 = 1 PM92 = Setting not required PM93 = Setting not required PM93 = Setting not required PM94 = Setting not required PM94 = 1 PM94 = Setting not required PM95 = Setting not required PM95 = Setting not required PM96 = Setting not required PM96 = 1 PM96 = Setting not required PM97 = Setting not required PM97 = Setting not required PM98 = Setting not required PM98 = Setting not required PM99 = Setting not required PM99 = Setting not required PMCn Register PFCn Register PMC90 = 1 PMC90 = 1 PMC90 = 0 PMC91 = 1 PMC91 = 1 PMC91 = 0 PMC92 = 1 PMC92 = 0 PMC92 = 1 PMC93 = 1 PMC93 = 1 PMC94 = 1 PMC94 = 0 PMC94 = 1 PMC95 = 1 PMC95 = 1 PMC96 = 1 PMC96 = 0 PMC96 = 1 PMC97 = 1 PMC97 = 1 PMC98 = 1 PMC98 = 1 PMC99 = 1 PMC99 = 1 PFC90 = 0 PFC90 = 1 PFC90 = 0 PFC91 = 0 PFC91 = 1 PFC91 = 0 PFC92 = 0 PFC92 = 0 PFC92 = 1 PFC93 = 0 PFC93 = 1 PFC94 = 0 PFC94 = 0 PFC94 = 1 PFC95 = 0 PFC95 = 1 PFC96 = 0 PFC96 = 0 PFC96 = 1 PFC97 = 0 PFC97 = 1 PFC98 = 0 PFC98 = 1 PFC99 = 0 PFC99 = 1 Note - Note, PF98 (PF9) = 0 PF98 (PF9) = Don't care Note, PF98 (PF9) = 0 PF98 (PF9) = Don't care Note - - Note - Note - - Note - KRM7 (KRM) = 1 Note - - CHAPTER 4 PORT FUNCTIONS KRM6 (KRM) = 1 Note - Note - TO02 P93 A3 TI021 P94 A4 TI030 TO03 P95 A5 TI031 P96 A6 TI51 TO51 P97 A7 SI01 P98 A8 SO01 P99 A9 SCK01 175 Note When setting the A0 to A15 pins, set the PFC9 register to 0000H and the PMC9 register to FFFFH in 16-bit units. 176 Pin Name Alternate Function Function Name P910 A10 SIA1 P911 A11 SOA1 P912 A12 SCKA1 P913 User's Manual U16889EJ1V0UD Table 4-19. Settings When Port Pins Are Used for Alternate Functions (6/7) Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of Other Bits (Registers) I/O Output Input Output Output Output I/O Output Input Output Input Output Input Input Output Output Input Output Output Output Output Output Output Output Output P910 = Setting not required P910 = Setting not required P911 = Setting not required P911 = Setting not required P912 = Setting not required P912 = Setting not required P913 = Setting not required P913 = Setting not required P914 = Setting not required P914 = Setting not required P915 = Setting not required P915 = Setting not required PCM0 = Setting not required PCM1 = Setting not required PCM2 = Setting not required PCM3 = Setting not required PCS0 = Setting not required PCS1 = Setting not required PCS2 = Setting not required PCS3 = Setting not required PCT0 = Setting not required PCT1 = Setting not required PCT4 = Setting not required PCT6 = Setting not required PM910 = Setting not required PM910 = Setting not required PM911 = Setting not required PM911 = Setting not required PM912 = Setting not required PM912 = Setting not required PM913 = Setting not required PM913 = Setting not required PM914 = Setting not required PM914 = Setting not required PM915 = Setting not required PM915 = Setting not required PMCM0 = Setting not required PMCM1 = Setting not required PMCM2 = Setting not required PMCM3 = Setting not required PMCS0 = Setting not required PMCS1 = Setting not required PMCS2 = Setting not required PMCS3 = Setting not required PMCT0 = Setting not required PMCT1 = Setting not required PMCT4 = Setting not required PMCT6 = Setting not required PMCn Register PFCn Register PMC910 = 1 PMC910 = 1 PMC911 = 1 PMC911 = 1 PMC912 = 1 PMC912 = 1 PMC913 = 1 PMC913 = 1 PMC914 = 1 PMC914 = 1 PMC915 = 1 PMC915 = 1 PMCCM0 = 1 PMCCM1 = 1 PMCCM2 = 1 PMCCM3 = 1 PMCCS0 = 1 PMCCS1 = 1 PMCCS2 = 1 PMCCS3 = 1 PMCCT0 = 1 PMCCT1 = 1 PMCCT4 = 1 PMCCT6 = 1 PFC910 = 0 PFC910 = 1 PFC911 = 0 PFC911 = 1 PFC912 = 0 PFC912 = 1 PFC913 = 0 PFC913 = 1 PFC914 = 0 PFC914 = 1 PFC915 = 0 PFC915 = 1 - - - - - - - - - - - - Note - - - - - - - - - - - - - Note - Note - Note, PF911 (PF9) = 0 PF911 (PF9) = Don't care Note, PF912 (PF9) = 0 PF912 (PF9) = Don't care Note CHAPTER 4 PORT FUNCTIONS - A13 INTP4 P914 A14 INTP5 P915 A15 INTP6 PCM0 PCM1 PCM2 PCM3 PCS0 PCS1 PCS2 PCS3 PCT0 PCT1 PCT4 PCT6 WAIT CLKOUT HLDAK HLDRQ CS0 CS1 CS2 CS3 WR0 WR1 RD ASTB Note When setting the A0 to A15 pins, set the PFC9 register to 0000H and the PMC9 register to FFFFH in 16-bit units. Table 4-19. Settings When Port Pins Are Used for Alternate Functions (7/7) Pin Name Alternate Function Function Name PDH0 PDH1 PDH2 PDH3 PDH4 PDH5 PDH6 PDH7 PDL0 PDL1 PDL2 PDL3 PDL4 PDL5 PDL6 PDL7 PDL8 PDL9 PDL10 PDL11 PDL12 PDL13 PDL14 PDL15 User's Manual U16889EJ1V0UD Pnx Bit of Pn Register PMnx Bit of PMn Register PMCnx Bit of PFCnx Bit of Other Bits (Registers) I/O Output Output Output Output Output Output Output Output I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PDH0 = Setting not required PDH1 = Setting not required PDH2 = Setting not required PDH3 = Setting not required PDH4 = Setting not required PDH5 = Setting not required PDH6 = Setting not required PDH7 = Setting not required PDL0 = Setting not required PDL1 = Setting not required PDL2 = Setting not required PDL3 = Setting not required PDL4 = Setting not required PDL5 = Setting not required PDL6 = Setting not required PDL7 = Setting not required PDL8 = Setting not required PDL9 = Setting not required PDL10 = Setting not required PDL11 = Setting not required PDL12 = Setting not required PDL13 = Setting not required PDL14 = Setting not required PDL15 = Setting not required PMDH0 = Setting not required PMDH1 = Setting not required PMDH2 = Setting not required PMDH3 = Setting not required PMDH4 = Setting not required PMDH5 = Setting not required PMDH6 = Setting not required PMDH7 = Setting not required PMDL0 = Setting not required PMDL1 = Setting not required PMDL2 = Setting not required PMDL3 = Setting not required PMDL4 = Setting not required PMDL5 = Setting not required PMDL6 = Setting not required PMDL7 = Setting not required PMDL8 = Setting not required PMDL9 = Setting not required PMCn Register PFCn Register PMCDH0 = 1 PMCDH1 = 1 PMCDH2 = 1 PMCDH3 = 1 PMCDH4 = 1 PMCDH5 = 1 PMCDH6 = 1 PMCDH7 = 1 PMCDL0 = 1 PMCDL1 = 1 PMCDL2 = 1 PMCDL3 = 1 PMCDL4 = 1 PMCDL5 = 1 PMCDL6 = 1 PMCDL7 = 1 PMCDL8 = 1 PMCDL9 = 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CHAPTER 4 PORT FUNCTIONS - - - - - - - - - - - - - - - - - A16 A17 A18 A19 A20 A21 A22 A23 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 PMDL10 = Setting not required PMCDL10 = 1 PMDL11 = Setting not required PMCDL11 = 1 PMDL12 = Setting not required PMCDL12 = 1 PMDL13 = Setting not required PMCDL13 = 1 PMDL14 = Setting not required PMCDL14 = 1 PMDL15 = Setting not required PMCDL15 = 1 177 CHAPTER 4 PORT FUNCTIONS 4.6 Cautions 4.6.1 Cautions on bit manipulation instruction for port n register (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit. Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode. P90 Low-level output P91 to P97 Pin status: High level Port 9L latch 0 0 0 0 0 0 0 0 Bit manipulation instruction (set1 0, P9L[r0]) is executed for P90 bit. P90 Low-level output P91 to P97 Pin status: High level Port 9L latch 1 1 1 1 1 1 1 1 Bit manipulation instruction for P90 bit <1> The P9L register is read in 8-bit units. * In the case of P90, an output port, the value of the port latch (0) is read. * In the case of P91 to P97, input ports, the pin status (1) is read. <2> Set P90 bit to 1. <3> Write the results of <2> to the output latch of the P9L register in 8 bit units. 178 User's Manual U16889EJ1V0UD CHAPTER 4 PORT FUNCTIONS 4.6.2 Hysteresis characteristics In port mode, the following ports do not have hysteresis characteristics. P02 to P06 P31 to P35, P38, P39 P40, P42 P66, P68 to P610, P612, P613 P80, P81 P93, P95, P97, P99, P910, P912 to P915 User's Manual U16889EJ1V0UD 179 CHAPTER 5 BUS CONTROL FUNCTION The V850ES/KJ1 is provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. 5.1 Features Output is selectable from a multiplex bus with a minimum of 3 bus cycles and a separate bus with a minimum of 2 bus cycles Chip select function for up to 4 spaces 8-bit/16-bit data bus selectable (for each area selected by chip select function) Wait function * Programmable wait function of up to 7 states (selectable for each area selected by chip select function) * External wait function using WAIT pin Idle state function Bus hold function The bus can be controlled using a different voltage from the operating voltage by setting BVDD VDD = EVDD (however, only in multiplex bus mode). 180 User's Manual U16889EJ1V0UD CHAPTER 5 BUS CONTROL FUNCTION 5.2 Bus Control Pins The pins used to connect an external device are listed in the table below. Table 5-1. Bus Control Pins (When Multiplex Bus Selected) Bus Control Pin AD0 to AD15 A16 to A23 WAIT CLKOUT CS0 to CS3 WR0, WR1 RD ASTB HLDRQ HLDAK Alternate-Function Pin PDL0 to PDL15 PDH0 to PDH7 PCM0 PCM1 PCS0 to PCS3 PCT0, PCT1 PCT4 PCT6 PCM3 PCM2 I/O I/O Output Input Output Output Output Output Output Input Output Address/data bus Address bus External wait control Internal system clock output Chip select Write strobe signal Read strobe signal Address strobe signal Bus hold control Function Table 5-2. Bus Control Pins (When Separate Bus Selected) Bus Control Pin AD0 to AD15 A0 to A15 A16 to A23 WAIT CLKOUT CS0 to CS3 WR0, WR1 RD HLDRQ HLDAK Alternate-Function Pin PDL0 to PDL15 P90 to P915 PDH0 to PDH7 PCM0 PCM1 PCS0 to PCS3 PCT0, PCT1 PCT4 PCM3 PCM2 I/O I/O Output Output Input Output Output Output Output Input Output Data bus Address bus Address bus External wait control Internal system clock output Chip select Write strobe signal Read strobe signal Bus hold control Function User's Manual U16889EJ1V0UD 181 CHAPTER 5 BUS CONTROL FUNCTION 5.2.1 Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed When the internal ROM, internal RAM, or on-chip peripheral I/O are accessed, the status of each pin is as follows. Table 5-3. Pin Statuses When Internal ROM, Internal RAM, or On-Chip Peripheral I/O Is Accessed Separate Bus Mode Address bus (A23 to A0) Data bus (AD15 to AD0) Control signal Undefined Hi-Z Inactive Multiplex Bus Mode Address bus (A23 to A16) Address/data bus (AD15 to AD0) Control signal Undefined Undefined Inactive Caution When a write access is performed to the internal ROM area, address, data, and control signals are activated in the same way as access to the external memory area. 5.2.2 Pin status in each operation mode For the pin status of the V850ES/KJ1 in each operation mode, refer to 2.2 Pin Status. 182 User's Manual U16889EJ1V0UD CHAPTER 5 BUS CONTROL FUNCTION 5.3 Memory Block Function The 64 MB memory space is divided into memory blocks of (lower) 2 MB, 2 MB, 4 MB, and 8 MB. one-block units. Figure 5-1. Data Memory Map: Physical Address The programmable wait function and bus cycle operation mode for each of these blocks can be independently controlled in 3FFFFFFH (80 KB) 3FEC000H 3FEBFFFH On-chip peripheral I/O area (4 KB) 3FFFFFFH 3FFF000H 3FFEFFFHNote 1 Internal RAM area (6 KBNote 1) Access-prohibited area 3FFD800H Note 1 3FFD7FFH Access-prohibited area 1000000H 0FFFFFFH 3FEC000H External memory area (8 MB) CS3 0800000H 07FFFFFH External memory area (4 MB) 0400000H 03FFFFFH 0200000H 01FFFFFH 0000000H External memory area (2 MB) CS2 01FFFFFH CS1 External memory area (1 MB) Internal ROM areaNote 2 (1 MB) 0000000H 0100000H 00FFFFFH (2 MB) CS0 Notes 1. PD70F3218H, 70F3218HY: 16 KB (3FFB000H to 3FFEFFFH) 2. This area is an external memory area in the case of a data write access. User's Manual U16889EJ1V0UD 183 CHAPTER 5 BUS CONTROL FUNCTION 5.3.1 Chip select control function Of the 64 MB (linear) address space, the lower 16 MB (0000000H to 0FFFFFFH) include four chip select control functions, CS0 to CS3. The areas that can be selected by CS0 to CS3 are fixed. By using these chip select control functions, the memory space can be used effectively. The allocation of the chip select areas is shown in the table below. CS0 CS1 CS2 CS3 0000000H to 01FFFFFH (2 MB) 0200000H to 03FFFFFH (2 MB) 0400000H to 07FFFFFH (4 MB) 0800000H to 0FFFFFFH (8 MB) 5.4 External Bus Interface Mode Control Function The V850ES/KJ1 includes the following two external bus interface modes. * Multiplex bus mode * Separate bus mode These two modes can be selected by using the EXIMC register. (1) External bus interface mode control register (EXIMC) This register can be read or written in 8-bit or 1-bit units. After reset, EXIMC is cleared to 00H. After reset: 00H R/W Address: FFFFFFBEH EXIMC 0 0 0 0 0 0 0 SMSEL SMSEL 0 1 Multiplex bus mode Separate bus mode Mode selection Caution Set the EXIMC register from the internal ROM or internal RAM area before external access. After setting the EXIMC register, be sure to set a NOP instruction. 184 User's Manual U16889EJ1V0UD CHAPTER 5 BUS CONTROL FUNCTION 5.5 Bus Access 5.5.1 Number of clocks for access The following table shows the number of basic clocks required for accessing each resource. Area (Bus Width) Bus Cycle Type Instruction fetch (normal access) Instruction fetch (branch) Operand data access Internal ROM (32 Bits) 1 2 3 Internal RAM (32 Bits) 1 2 Note 1 External Memory (16 Bits) 3+n 3+ n Note 2 On-Chip Peripheral I/O (16 Bits) - - 3 Note 3 Note 1 Note 2 1 3 +n Note 2 Notes 1. If the access conflicts with a data access, the number of clock is increased by 1. 2. 2 + n clocks (n: Number of wait states) when the separate bus mode is selected. 3. This value varies depending on the setting of the VSWC register. Remark Unit: Clocks/access 5.5.2 Bus size setting function The bus size of each external memory area selected by CSn can be set (to 8 bits or 16 bits) by using the BSC register. The external memory area of the V850ES/KJ1 is selected by CS0 to CS3. (1) Bus size configuration register (BSC) This register can be read or written in 16-bit units. After reset, BSC is set to 5555H. Caution Write to the BSC register after reset, and then do not change the set values. Also, do not access an external memory area until the initial settings of the BSC register are complete. After reset: 5555H 15 R/W 14 Address: FFFFF066H 13 12 11 10 9 8 BSC 0 7 1 6 0 5 1 4 0 3 1 2 0 1 1 0 0 CSn signal BSn0 0 1 BS30 CS3 0 BS20 CS2 0 BS10 CS1 0 BS00 CS0 Data bus width of CSn space (n = 0 to 3) 8 bits 16 bits Caution Be sure to set bits 14, 12, 10, and 8 to 1, and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to 0. User's Manual U16889EJ1V0UD 185 CHAPTER 5 BUS CONTROL FUNCTION 5.5.3 Access by bus size The V850ES/KJ1 accesses the on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The bus size is as follows. * The bus size of the on-chip peripheral I/O is fixed to 16 bits. * The bus size of the external memory is selectable from 8 bits or 16 bits (by using the BSC register). The operation when each of the above is accessed is described below. All data is accessed starting from the lower side. The V850ES/KJ1 supports only the little endian format. Figure 5-2. Little Endian Address in Word 31 000BH 0007H 0003H 24 23 000AH 0006H 0002H 16 15 0009H 0005H 0001H 87 0008H 0004H 0000H 0 (1) Data space The V850ES/KJ1 has an address misalign function. With this function, data can be placed at all addresses, regardless of the format of the data (word data or halfword data). However, if the word data or halfword data is not aligned at the boundary, a bus cycle is generated at least twice, causing the bus efficiency to drop. (a) Halfword-length data access A byte-length bus cycle is generated twice if the least significant bit of the address is 1. (b) Word-length data access (i) A byte-length bus cycle, halfword-length bus cycle, and byte-length bus cycle are generated in that order if the least significant bit of the address is 1. (ii) A halfword-length bus cycle is generated twice if the lower 2 bits of the address are 10. 186 User's Manual U16889EJ1V0UD CHAPTER 5 BUS CONTROL FUNCTION (2) Byte access (8 bits) (a) 16-bit data bus width <1> Access to even address (2n) Address 15 15 2n + 1 <2> Access to odd address (2n + 1) Address 7 8 7 2n 7 8 7 0 Byte data 0 External data bus 0 Byte data 0 External data bus (b) 8-bit data bus width <1> Access to even address (2n) Address 7 7 2n 0 Byte data 0 External data bus <2> Access to odd address (2n + 1) Address 7 7 2n + 1 0 Byte data 0 External data bus User's Manual U16889EJ1V0UD 187 CHAPTER 5 BUS CONTROL FUNCTION (3) Halfword access (16 bits) (a) With 16-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) First access Address 15 15 2n + 1 8 7 8 7 2n 0 Halfword data 0 External data bus 0 Halfword data 0 External data bus 8 7 8 7 2n 0 Halfword data 0 External data bus 15 15 2n + 1 8 7 8 7 2n + 2 Address 15 15 Second access Address (b) 8-bit data bus width <1> Access to even address (2n) First access 15 8 7 0 Halfword data Address 7 2n 0 External data bus 0 Halfword data 0 External data bus 15 8 7 Address 7 2n + 1 <2> Access to odd address (2n + 1) First access 15 8 7 0 Halfword data Address 7 2n + 1 0 External data bus 0 Halfword data 0 External data bus 15 8 7 Address 7 2n + 2 Second access Second access 188 User's Manual U16889EJ1V0UD CHAPTER 5 BUS CONTROL FUNCTION (4) Word access (32 bits) (a) 16-bit data bus width (1/2) <1> Access to address (4n) First access 31 31 Second access 24 23 Address 15 4n + 1 8 7 8 7 4n 0 Word data 0 External data bus 24 23 Address 15 4n + 3 8 7 8 7 4n + 2 0 Word data 0 External data bus 16 15 16 15 <2> Access to address (4n + 1) First access 31 31 Second access 31 Third access 24 23 Address 15 4n + 1 8 7 8 7 24 23 Address 15 4n + 3 8 7 8 7 4n + 2 24 23 Address 15 16 15 16 15 16 15 8 7 8 7 4n + 4 0 Word data 0 External data bus 0 Word data 0 External data bus 0 Word data 0 External data bus User's Manual U16889EJ1V0UD 189 CHAPTER 5 BUS CONTROL FUNCTION (a) 16-bit data bus width (2/2) <3> Access to address (4n + 2) First access 31 31 Second access 24 23 Address 15 4n + 3 8 7 8 7 4n + 2 0 Word data 0 External data bus 24 23 Address 15 4n + 5 8 7 8 7 4n + 4 0 Word data 0 External data bus 16 15 16 15 <4> Access to address (4n + 3) First access 31 31 Second access 31 Third access 24 23 Address 15 4n + 3 8 7 8 7 24 23 Address 15 4n + 5 8 7 8 7 4n + 4 24 23 Address 15 16 15 16 15 16 15 8 7 8 7 4n + 6 0 Word data 0 External data bus 0 Word data 0 External data bus 0 Word data 0 External data bus 190 User's Manual U16889EJ1V0UD CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (1/2) <1> Access to address (4n) First access 31 24 23 16 15 8 7 0 Word data Address 7 4n 0 External data bus 0 Word data 0 External data bus 31 24 23 16 15 8 7 Address 7 4n + 1 0 Word data 0 External data bus Second access 31 24 23 16 15 8 7 Third access 31 24 23 16 15 Address 7 4n + 2 8 7 Fourth access Address 7 4n + 3 0 External data bus 0 Word data <2> Access to address (4n + 1) First access 31 24 23 16 15 8 7 0 Word data Address 4n + 1 0 External data bus 0 Word data 0 External data bus 31 24 23 16 15 8 7 Address 4n + 2 0 Word data 0 External data bus Second access 31 24 23 16 15 8 7 Third access 31 24 23 16 15 Address 4n + 3 0 8 7 Fourth access 7 7 7 7 0 Address 4n + 4 Word data External data bus User's Manual U16889EJ1V0UD 191 CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (2/2) <3> Access to address (4n + 2) First access 31 24 23 16 15 8 7 0 Word data Address 7 4n + 2 0 External data bus 0 Word data 0 External data bus 31 24 23 16 15 8 7 Address 7 4n + 3 0 Word data 0 External data bus Second access 31 24 23 16 15 8 7 Third access 31 24 23 16 15 Address 7 4n + 4 8 7 Fourth access Address 7 4n + 5 0 External data bus 0 Word data <4> Access to address (4n + 3) First access 31 24 23 16 15 8 7 0 Word data Address 7 4n + 3 0 External data bus 0 Word data 0 External data bus 31 24 23 16 15 8 7 Address 7 4n + 4 0 Word data 0 External data bus Second access 31 24 23 16 15 8 7 Third access 31 24 23 16 15 Address 7 4n + 5 0 8 7 Fourth access Address 7 4n + 6 0 External data bus Word data 192 User's Manual U16889EJ1V0UD CHAPTER 5 BUS CONTROL FUNCTION 5.6 Wait Function 5.6.1 Programmable wait function (1) Data wait control register 0 (DWC0) To realize interfacing with a low-speed memory or I/O, up to seven data wait states can be inserted in the bus cycle that is executed for each CS space. The number of wait states can be programmed by using the DWC0 register. Immediately after system reset, 7 data wait states are inserted for all the chip select areas. The DWC0 register can be read or written in 16-bit units. After reset, DWC0 is set to 7777H. Cautions 1. The internal ROM and internal RAM areas are not subject to programmable wait, and are always accessed without a wait state. The on-chip peripheral I/O area is also not subject to programmable wait, and only wait control from each peripheral function is performed. 2. Write to the DWC0 register after reset, and then do not change the set values. Also, do not access an external memory area until the initial settings of the DWC0 register are complete. After reset: 7777H 15 R/W 14 Address: FFFFF484H 13 12 11 10 9 8 DWC0 0 DW32 DW31 CS3 DW30 0 DW22 DW21 CS2 DW20 CSn signal 7 6 5 4 3 2 1 0 0 CSn signal DWn2 0 0 0 0 1 1 1 1 DW12 DW11 CS1 DW10 0 DW02 DW01 CS0 DW00 DWn1 0 0 1 1 0 0 1 1 DWn0 0 1 0 1 0 1 0 1 Number of wait states inserted in CSn space (n = 0 to 3) None 1 2 3 4 5 6 7 Caution Be sure to clear bits 15, 11, 7, and 3 to 0. User's Manual U16889EJ1V0UD 193 CHAPTER 5 BUS CONTROL FUNCTION 5.6.2 External wait function To synchronize an extremely slow memory, I/O, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (WAIT). Access to each area of the internal ROM, internal RAM, and on-chip peripheral I/O is not subject to control by the external wait function, in the same manner as the programmable wait function. The WAIT signal can be input asynchronously to CLKOUT, and is sampled at the falling edge of the clock in the T2 and TW states of the bus cycle in the multiplex bus mode. In the separate bus mode, it is sampled at the rising edge of the clock immediately after the T1 and TW states of the bus cycle. If the setup/hold time of the sampling timing is not satisfied, a wait state is inserted in the next state, or not inserted at all. 194 User's Manual U16889EJ1V0UD CHAPTER 5 BUS CONTROL FUNCTION 5.6.3 Relationship between programmable wait and external wait Wait cycles are inserted as the result of an OR operation between the wait cycles specified by the set value of the programmable wait and the wait cycles controlled by the WAIT pin. Programmable wait Wait control Wait via WAIT pin For example, if the timing of the programmable wait and the WAIT pin signal is as illustrated below, three wait states will be inserted in the bus cycle. Figure 5-3. Example of Inserting Wait States (a) In separate bus mode T1 TW TW TW T2 CLKOUT WAIT pin Wait via WAIT pin Programmable wait Wait control Remark The circles indicate the sampling timing. (b) In multiplex bus mode T1 CLKOUT WAIT pin Wait via WAIT pin Programmable wait Wait control T2 TW TW TW T3 Remark The circles indicate the sampling timing. User's Manual U16889EJ1V0UD 195 CHAPTER 5 BUS CONTROL FUNCTION 5.6.4 Programmable address wait function Address-setup or address-hold waits to be inserted in each bus cycle can be set by using the AWC register. Address wait insertion is set for each chip select area (CS0 to CS3). If an address setup wait is inserted, it seems that the high-clock period of T1 state is extended by 1 clock. If an address hold wait is inserted, it seems that the low-clock period of T1 state is extended by 1 clock. (1) Address wait control register (AWC) This register can be read or written in 16-bit units. After reset, AWC is set to FFFFH. Cautions 1. The internal ROM, internal RAM, and on-chip peripheral I/O areas are not subject to address setup wait or address hold wait insertion. 2. Write the AWC register after reset, and then do not change the set values. Also, do not access an external memory area until the initial settings of the AWC register are complete. After reset: FFFFH 15 R/W 14 Address: FFFFF488H 13 12 11 10 9 8 AWC 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 AHW3 CSn signal CS3 ASW3 AHW2 ASW2 CS2 AHW1 ASW1 CS1 AHW0 ASW0 CS0 AHWn 0 1 Specifies insertion of address hold wait (n = 0 to 3) Not inserted Inserted ASWn 0 1 Specifies insertion of address setup wait (n = 0 to 3) Not inserted Inserted Caution Be sure to set bits 15 to 8 to 1. 196 User's Manual U16889EJ1V0UD CHAPTER 5 BUS CONTROL FUNCTION 5.7 Idle State Insertion Function To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus cycle that is executed for each space selected by CSn in the multiplex address/data bus mode. In the separate bus mode, one idle state (TI) can be inserted after the T2 state. By inserting idle states, the data output float delay time of the memory can be secured during read access (an idle state cannot be inserted during write access). Whether the idle state is to be inserted can be programmed by using the BCC register. An idle state is inserted for all the areas immediately after system reset. (1) Bus cycle control register (BCC) This register can be read or written in 16-bit units. After reset, BCC is set to AAAAH. Cautions 1. The internal ROM, internal RAM, and on-chip peripheral I/O areas are not subject to idle state insertion. 2. Write to the BCC register after reset, and then do not change the set values. Also, do not access an external memory area until the initial settings of the BCC register are complete. After reset: AAAAH 15 14 R/W Address: FFFFF48AH 13 12 11 10 9 8 BCC 1 7 0 6 1 5 0 4 1 3 0 2 1 1 0 0 BC31 CSn signal CS3 BCn1 0 1 0 BC21 CS2 0 BC11 CS1 0 BC01 CS0 0 Specifies insertion of idle state (n = 0 to 3) Not inserted Inserted Caution Be sure to set bits 15, 13, 11, and 9 to 1, and clear bits 14, 12, 10, 8, 6, 4, 2, and 0 to 0. User's Manual U16889EJ1V0UD 197 CHAPTER 5 BUS CONTROL FUNCTION 5.8 Bus Hold Function 5.8.1 Functional outline The HLDRQ and HLDAK functions are valid if the PCM2 and PCM3 pins are set in the control mode. When the HLDRQ pin is asserted (low level), indicating that another bus master has requested bus mastership, the external address/data bus goes into a high-impedance state and is released (bus hold status). If the request for the bus mastership is cleared and the HLDRQ pin is deasserted (high level), driving these pins is started again. During the bus hold period, execution of the program in the internal ROM and internal RAM is continued until a peripheral I/O register or the external memory is accessed. The bus hold status is indicated by assertion (low level) of the HLDAK pin. The bus hold function enables the configuration of multi-processor type systems in which two or more bus masters exist. Note that the bus hold request is not acknowledged during a multiple-access cycle initiated by the bus sizing function or a bit manipulation instruction. Status Data Bus Width CPU bus lock 16 bits Word access to even address Word access to odd address Access Type Timing in Which Bus Hold Request Not Acknowledged Between first and second access Between first and second access Between second and third access Halfword access to odd address 8 bits Word access Between first and second access Between first and second access Between second and third access Between third and fourth access Halfword access Read-modify-write access of bit manipulation instruction - - Between first and second access Between read access and write access 198 User's Manual U16889EJ1V0UD CHAPTER 5 BUS CONTROL FUNCTION 5.8.2 Bus hold procedure The bus hold status transition procedure is shown below. <1> Low-level input to HLDRQ pin acknowledged <2> All bus cycle start requests inhibited <3> End of current bus cycle <4> Shift to bus idle status. <5> Output low level from HLDAK pin Normal status Bus hold status <6> High-level input to HLDRQ pin acknowledged <7> Output high level from HLDAK pin <8> Bus cycle start request inhibition released <9> Bus cycle starts Normal status HLDRQ (input) HLDAK (output) <1> <2> <3><4> <5> <6> <7><8><9> 5.8.3 Operation in power save mode Because the internal system clock is stopped in the STOP and IDLE modes, the bus hold status is not entered even if the HLDRQ pin is asserted. In the HALT mode, the HLDAK pin is asserted as soon as the HLDRQ pin has been asserted, and the bus hold status is entered. When the HLDRQ pin is later deasserted, the HLDAK pin is also deasserted, and the bus hold status is cleared. User's Manual U16889EJ1V0UD 199 CHAPTER 5 BUS CONTROL FUNCTION 5.9 Bus Priority Bus hold, instruction fetch (branch), instruction fetch (successive), and operand data accesses are executed in the external bus cycle. Bus hold has the highest priority, followed by operand data access, instruction fetch (branch), and instruction fetch (successive). An instruction fetch may be inserted between the read access and write access in a read-modify-write access. If an instruction is executed for two or more accesses, an instruction fetch and bus hold are not inserted between accesses due to bus size limitations. Table 5-4. Bus Priority Priority High Bus hold Operand data access Instruction fetch (branch) Low Instruction fetch (successive) External Bus Cycle Bus Master External device CPU CPU CPU 200 User's Manual U16889EJ1V0UD CHAPTER 5 BUS CONTROL FUNCTION 5.10 Bus Timing Figure 5-4. Multiplex Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access) T1 T2 T3 T1 T2 TW TW T3 TI T1 CLKOUT A23 to A16 ASTB CS3 to CS0 WAIT AD15 to AD0 RD Programmable External wait wait 8-bit access AD15 to AD8 AD7 to AD0 Odd address Active Hi-Z Even address Hi-Z Active Idle state A1 D1 A2 D2 A3 A1 A2 A3 Remark The broken lines indicate high impedance. Figure 5-5. Multiplex Bus Read Timing (Bus Size: 8 Bits) T1 CLKOUT A23 to A16, AD15 to AD8 ASTB CS3 to CS0 WAIT AD7 to AD0 RD A1 T2 T3 T1 T2 TW TW T3 TI T1 A1 A2 A3 D1 A2 D2 A3 Programmable External wait wait Idle state Remark The broken lines indicate high impedance. User's Manual U16889EJ1V0UD 201 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-6. Multiplex Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access) T1 CLKOUT A23 to A16 ASTB CS3 to CS0 WAIT AD15 to AD0 WR1, WR0 A1 11 T2 T3 T1 T2 TW TW T3 T1 A1 A2 A3 D1 00 11 A2 11 D2 00 A3 11 Programmable External wait wait 8-bit access AD15 to AD8 AD7 to AD0 WR1, WR0 Odd address Active Undefined 01 10 Even address Undefined Active Figure 5-7. Multiplex Bus Write Timing (Bus Size: 8 Bits) T1 CLKOUT A23 to A16, AD15 to AD8 ASTB CS3 to CS0 WAIT AD7 to AD0 WR1, WR0 A1 11 T2 T3 T1 T2 TW TW T3 T1 A1 A2 A3 D1 10 11 A2 11 D2 10 A3 11 Programmable External wait wait 202 User's Manual U16889EJ1V0UD CHAPTER 5 BUS CONTROL FUNCTION Figure 5-8. Multiplex Bus Hold Timing (Bus Size: 16 Bits, 16-Bit Access) T1 CLKOUT HLDRQ HLDAK A23 to A16 AD15 to AD0 ASTB RD CS3 to CS0 A1 T2 T3 TINote TH TH TH TH TINote T1 T2 T3 A1 D1 Undefined Undefined Undefined Undefined A2 A2 D2 1111 1111 Note This idle state (TI) does not depend on the BCC register settings. Remarks 1. Refer to Table 2-2 for the pin statuses in the bus hold mode. 2. The broken lines indicate high impedance. User's Manual U16889EJ1V0UD 203 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-9. Separate Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access) T1 CLKOUT CS3 to CS0 WAIT A23 to A0 RD AD15 to AD0 A1 T2 T1 TW TW T2 TI T1 T2 A2 A3 D1 D2 D3 Programmable External wait wait 8-bit access AD15 to AD8 AD7 to AD0 Odd address Active Hi-Z Even address Hi-Z Active Idle state Remark The broken lines indicate high impedance. Figure 5-10. Separate Bus Read Timing (Bus Size: 8 Bits) T1 CLKOUT CS3 to CS0 WAIT A23 to A0 RD AD7 to AD0 A1 T2 T1 TW TW T2 TI T1 T2 A2 A3 D1 D2 D3 Programmable External wait wait Idle state Remark The broken lines indicate high impedance. 204 User's Manual U16889EJ1V0UD CHAPTER 5 BUS CONTROL FUNCTION Figure 5-11. Separate Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access) T1 CLKOUT CS3 to CS0 WAIT A23 to A0 WR1, WR0 AD15 to AD0 11 A1 T2 T1 TW TW T2 T1 T2 A2 00 D1 11 11 00 D2 11 A3 00 D3 11 Programmable External wait wait 8-bit access AD15 to AD8 AD7 to AD0 WR1, WR0 Odd address Active Undefined 01 10 Even address Undefined Active Remark The broken lines indicate high impedance. Figure 5-12. Separate Bus Write Timing (Bus Size: 8 Bits) T1 CLKOUT CS3 to CS0 WAIT A23 to A0 WR1, WR0 AD7 to AD0 11 A1 T2 T1 TW TW T2 T1 T2 A2 10 D1 11 11 10 D2 11 A3 10 D3 11 Programmable External wait wait Remark The broken lines indicate high impedance. User's Manual U16889EJ1V0UD 205 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-13. Separate Bus Hold Timing (Bus Size: 8 Bits, Write) T1 CLKOUT HLDRQ HLDAK A23 to A0 AD7 to AD0 WR1, WR0 CS3 to CS0 11 A1 T2 T1 T2 TINote TH TH TH TH TINote T1 T2 A2 D1 D2 11 10 Undefined Undefined A3 D3 10 11 1111 1111 11 10 11 Note This idle state (TI) does not depend on the BCC register settings. Remark The broken lines indicate high impedance. Figure 5-14. Address Wait Timing (Separate Bus Read, Bus Size: 16 Bits, 16-Bit Access) T1 CLKOUT ASTB CS3 to CS0 WAIT A23 to A0 RD AD15 to AD0 A1 T2 CLKOUT ASTB CS3 to CS0 WAIT A23 to A0 RD D1 AD15 to AD0 TASW T1 TAHW T2 A1 D1 Remarks 1. TASW (address setup wait): Image of high-level width of T1 state expanded. 2. TAHW (address hold wait): Image of low-level width of T1 state expanded. 3. The broken lines indicate high impedance. 206 User's Manual U16889EJ1V0UD CHAPTER 5 BUS CONTROL FUNCTION 5.11 Cautions With the external bus function, signals may not be output at the correct timing under the following conditions. User's Manual U16889EJ1V0UD 207 CHAPTER 6 CLOCK GENERATION FUNCTION 6.1 Overview The following clock generation functions are available. Main clock oscillator * fX = 2 to 2.5 MHz (fXX = 8 to 10 MHz, REGC = VDD = 2.7 to 5.5 V, in PLL mode) * fX = 2 to 5 MHz (fXX = 8 to 20 MHz, REGC = VDD = 4.5 to 5.5 V, in PLL mode) * fX = 2 to 4 MHz (fXX = 8 to 16 MHz, REGC = capacitor, VDD = 4.0 to 5.5 V, in PLL mode) * fX = 2 to 10 MHz (fXX = 2 to 10 MHz, REGC = VDD = 2.7 to 5.5 V, in clock-through mode) Caution In the PD70F3217H, 70F3217HY, 70F3218H, and 70F3218HY, the main clock oscillator oscillates the following frequencies (these values may change after evaluation). * fX = 2 MHz (fXX = 8 MHz, REGC = VDD = 2.7 to 5.5 V, in PLL mode) * fX = 2 to 5 MHz (fXX = 8 to 20 MHz, REGC = VDD = 4.5 to 5.5 V, in PLL mode) * fX = 2 MHz (fXX = 8 MHz, REGC = capacitor, VDD = 4.0 to 5.5 V, in PLL mode) * fX = 2 to 8 MHz (fXX = 2 to 8 MHz, REGC = VDD = 2.7 to 5.5 V, in clock-through mode) Subclock oscillator * 32.768 kHz Multiplication (x4) function by PLL (Phase Locked Loop) * Clock-through mode/PLL mode selectable * Usable voltage: VDD = 2.7 to 5.5 V Internal system clock generation * 7 steps (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT) Peripheral clock generation Clock output function Remark fX: Main clock oscillation frequency fXX: Main clock frequency 208 User's Manual U16889EJ1V0UD CHAPTER 6 CLOCK GENERATION FUNCTION 6.2 Configuration Figure 6-1. Clock Generator FRC bit XT1 XT2 Subclock oscillator fXT fXT fBRG = fX/2 to fX/212 Interval timer BRG MCK MFRC bit bit X1 X2 Main clock oscillator Main clock oscillator stop control STOP mode SELPLL bit fX IDLE control CK2 to CK0 bits Selector Watch timer clock, watchdog timer clock Watch timer clock IDLE mode PLLON bit IDLE mode CLS bit, CK3 bit PLL IDLE fXX control Prescaler 2 fXX/32 fXX/16 fXX/8 fXX/4 fXX/2 fXX HALT mode Selector Selector HALT fCPU control fCLK CPU clock Internal system clock IDLE mode Prescaler 1 fXX to fXX/1024 Peripheral clock, watchdog timer 2 clock fXW Watchdog timer 1 clock IDLE control CLKOUT Port CM fX: fXX: fXT: Main clock oscillation frequency Main clock frequency Subclock frequency fCLK: Internal system clock frequency fCPU: CPU clock frequency fBRG: Watch timer clock frequency fXW: Watchdog timer 1 clock frequency User's Manual U16889EJ1V0UD 209 CHAPTER 6 CLOCK GENERATION FUNCTION (1) Main clock oscillator The main clock oscillator oscillates the following frequencies (fX): * fX = 2 to 2.5 MHz (REGC = VDD = 2.7 to 5.5 V, in PLL mode) * fX = 2 to 5 MHz (REGC = VDD = 4.5 to 5.5 V, in PLL mode) * fX = 2 to 4 MHz (REGC = capacitor, VDD = 4.0 to 5.5 V, in PLL mode) * fX = 2 to 10 MHz (REGC = VDD = 2.7 to 5.5 V, in clock-through mode) Caution In the PD70F3217H, 70F3217HY, 70F3218H, and 70F3218HY, the main clock oscillator oscillates the following frequencies (these values may change after evaluation). * fX = 2 MHz (REGC = VDD = 2.7 to 5.5 V, in PLL mode) * fX = 2 to 5 MHz (REGC = VDD = 4.5 to 5.5 V, in PLL mode) * fX = 2 MHz (REGC = capacitor, VDD = 4.0 to 5.5 V, in PLL mode) * fX = 2 to 8 MHz (REGC = VDD = 2.7 to 5.5 V, in clock-through mode) (2) Subclock oscillator The subclock oscillator oscillates a frequency of 32.768 kHz (fXT). (3) Main clock oscillator stop control This circuit generates a control signal that stops oscillation of the main clock oscillator. Oscillation of the main clock oscillator is stopped in the STOP mode or when the PCC.MCK bit = 1 (valid only when the PCC.CLS bit = 1). (4) Prescaler 1 This prescaler generates the clock (fXX to fXX/1024) to be supplied to the following on-chip peripheral functions: TMP0 2 Note , TM00 to TM05, TM50, TM51, TMH0, TMH1, CSI00 to CSI02, CSIA0, CSIA1, UART0 to UART2, I2C0, I C1, ADC, DAC, and WDT2 Note Only in the PD70F3218H, 70F3218HY (5) Prescaler 2 This circuit divides the main clock (fXX). The clock generated by prescaler 2 (fXX to fXX/32) is supplied to the selector that generates the CPU clock (fCPU) and internal system clock (fCLK). fCLK is the clock supplied to the INTC, ROM correction, ROM, and RAM blocks, and can be output from the CLKOUT pin. (6) Interval timer BRG This circuit divides the clock (fX) generated by the main clock oscillator to a specific frequency (32.768 kHz) and supplies that clock to the watch timer block. For details, refer to CHAPTER 11 INTERVAL TIMER, WATCH TIMER. 210 User's Manual U16889EJ1V0UD CHAPTER 6 CLOCK GENERATION FUNCTION (7) PLL This circuit multiplies the clock (fX) generated by the main clock oscillator. It operates in two modes: clock-through mode in which fX is output as is, and PLL mode in which a multiplied clock is output. These modes can be selected by using the PLLCTL.SELPLL bit. Operation of the PLL can be started or stopped by the PLLCTL.PLLON bit. 6.3 Registers (1) Processor clock control register (PCC) The PCC register is a special register. Data can be written to this register only in combination of specific sequences (refer to 3.4.7 Special registers). This register can be read or written in 8-bit or 1-bit units. After reset, PCC is set to 03H. (1/2) After reset: 03H R/W <> PCC FRC MCK MFRC After reset: FFFFF828H <> CLS Note <> CK3 CK2 CK1 CK0 FRC 0 1 Used Not used Use of subclock on-chip feedback resistor MCK 0 1 Oscillation enabled Oscillation stopped Control of main clock oscillator * Even if the MCK bit is set to 1 while the system is operating with the main clock as the CPU clock, the operation of the main clock does not stop. It stops after the CPU clock has been changed to the subclock. * When the main clock is stopped and the device is operating on the subclock, clear the MCK bit to 0 and wait until the oscillation stabilization time has been secured by the program before switching back to the main clock. MFRC 0 1 Used Not used Use of main clock on-chip feedback resistor CLSNote 0 1 Main clock operation Subclock operation Status of CPU clock (fCPU) Note The CLS bit is a read-only bit. User's Manual U16889EJ1V0UD 211 CHAPTER 6 CLOCK GENERATION FUNCTION (2/2) CK3 0 0 0 0 0 0 0 1 CK2 0 0 0 0 1 1 1 x CK1 0 0 1 1 0 0 1 x CK0 0 1 0 1 0 1 x x fXX fXX/2 fXX/4 fXX/8 (default value) fXX/16 fXX/32 Setting prohibited fXT Clock selection (fCLK/fCPU) Cautions 1. Do not change the CPU clock (by using the CK3 to CK0 bits) while CLKOUT is being output. 2. Use a bit manipulation instruction to manipulate the CK3 bit. When using an 8-bit manipulation instruction, do not change the set values of the CK2 to CK0 bits. 3. When the CPU operates on the subclock and no clock is input to the X1 pin, do not access a register in which a wait occurs using an access method that causes a wait (refer to 3.4.8 (2) Access to special on-chip peripheral I/O register for details of the access methods). If a wait occurs, it can only be released by a reset. Remark x: don't care 212 User's Manual U16889EJ1V0UD CHAPTER 6 CLOCK GENERATION FUNCTION (a) Example of setting main clock operation subclock operation <1> CK3 bit 1: Use of a bit manipulation instruction is recommended. Do not change the CK2 to CK0 bits. <2> Subclock operation: Read the CLS bit to check if subclock operation has started. It takes the following time after the CK3 bit is set until subclock operation is started. Max.: 1/fXT (1/subclock frequency) <3> MCK bit 1: Set the MCK bit to 1 only when stopping the main clock. Cautions 1. When stopping the main clock, stop the PLL. 2. If the following conditions are not satisfied, change the CK2 to CK0 bits so that the conditions are satisfied, then change to the subclock operation mode. Main clock (fXX) > Subclock (fXT: 32.768 kHz) x 4 [Description example] <1> _SET_SUB_RUN : st.b set1 tst1 bz st.b set1 Remark r0, PRCMD[r0] 3, PCC[r0] 4, PCC[r0] _CHECK_CLS r0, PRCMD[r0] 6, PCC[r0] -- MCK bit 1, main clock is stopped -- CK3 bit 1 -- Wait until subclock operation starts. <2> _CHECK_CLS : <3> _STOP_MAIN_CLOCK : The above description is an example. Note with caution that the CLS bit is read in a closed loop in <2>. User's Manual U16889EJ1V0UD 213 CHAPTER 6 CLOCK GENERATION FUNCTION (b) Example of setting subclock operation main clock operation <1> MCK bit 0: <3> CK3 bit 0: <4> Main clock operation: Main clock starts oscillating Use of a bit manipulation instruction is recommended. Do not change the CK2 to CK0 bits. It takes the following time after the CK3 bit is set until main clock operation is started. Max.: 1/fXT (1/subclock frequency) Therefore, insert one NOP instruction immediately after setting the CK3 bit to 0 or read the CLS bit to check if main clock operation has started. [Description example] <1> _START_MAIN_OSC : st.b clr1 <2> movea _WAIT_OST : nop nop nop addi mp bne <3> st.b clr1 tst1 bnz Remark -1, r11, r11 r0, r11 _PROGRAM_WAIT r0, PRCMD[r0] 3, PCC[r0] 4, PCC[r0] _CHECK_CLS The above description is an example. Note with caution that the CLS bit is read in a closed loop in <4>. -- CK3 0 -- Wait until main clock operation starts r0, PRCMD[r0] 6, PCC[r0] 0x55, r0, r11 -- Release of protection of special registers -- Main clock starts oscillating -- Wait for oscillation stabilization time <2> Insert waits by the program and wait until the oscillation stabilization time of the main clock elapses. <4> _CHECK_CLS : 214 User's Manual U16889EJ1V0UD CHAPTER 6 CLOCK GENERATION FUNCTION 6.4 Operation 6.4.1 Operation of each clock The following table shows the operation status of each clock. Table 6-1. Operation Status of Each Clock Register Setting and Operation Status CLS bit = 0, MCK bit = 0 During reset Target Clock Main clock oscillator (fX) Subclock oscillator (fXT) CPU clock (fCPU) Internal system clock (fCLK) Peripheral clock (fXX to fXX/1024) WT clock (main) WT clock (sub) WDT1 clock (fXW) WDT2 clock (main) WDT2 clock (sub) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x During oscillation stabilization time count PCC Register CLS bit = 1, MCK bit = 0 HALT mode IDLE mode STOP mode x CLS bit = 1, MCK bit = 1 Subclock Sub-IDLE Subclock Sub-IDLE mode mode mode x mode x Remark O: Operable x: Stopped 6.4.2 Clock output function The clock output function is used to output the internal system clock (fCLK) from the CLKOUT pin. The internal system clock (fCLK) is selected by using the PCC.CK3 to PCC.CK0 bits. The CLKOUT pin functions alternately as the PCM1 pin and functions as a clock output pin if so specified by the control register of port CM. The status of the CLKOUT pin is the same as the internal system clock in Table 6-1 and the pin can output the clock when it is in the operable status. It outputs a low level in the stopped status. However, the port mode (PCM1: input mode) is selected until the CLKOUT pin output is set after reset. Consequently, the CLKOUT pin goes into a high-impedance state. 6.4.3 External clock input function An external clock can be directly input to the oscillator. Input the clock to the X1 pin and its inverse signal to the X2 pin. Set the PCC.MFRC bit to 1 (on-chip feedback resistor not used). Note, however, that oscillation stabilization time is inserted even in the external clock mode. Connect VDD directly to the REGC pin. User's Manual U16889EJ1V0UD 215 CHAPTER 6 CLOCK GENERATION FUNCTION 6.5 PLL Function 6.5.1 Overview The PLL function is used to output the operating clock of the CPU and peripheral macro at a frequency 4 times higher than the oscillation frequency, and select the clock-through mode. When PLL function is used: Input clock = 2 to 5 MHz (fXX: 8 to 20 MHz) Clock-through mode: 6.5.2 Register (1) PLL control register (PLLCTL) The PLLCTL register is an 8-bit register that controls the security function of PLL and RTO. This register can be read or written in 8-bit or 1-bit units. After reset, PLLCTL is set to 01H. Input clock = 2 to 10 MHz (fXX: 2 to 10 MHz) After reset: 01H R/W Address: FFFFF806H <> <> Note <> Note <> PLLON PLLCTL 0 0 0 0 RTOST1 RTOST0 SELPLL PLLON 0 1 PLL stopped PLL operating PLL operation stop register SELPLL 0 1 PLL clock selection register Clock-through operation PLL operation Note For the RTOST1 and RTOST0 bits, refer to CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO). Caution Be sure to clear bits 4 to 7 to 0. 216 User's Manual U16889EJ1V0UD CHAPTER 6 CLOCK GENERATION FUNCTION 6.5.3 Usage (1) When PLL is used * After reset has been released, the PLL operates (PLLCTL.PLLON bit = 1), but because the default mode is the clock-through mode (PLLCTL.SELPLL bit = 0), select the PLL mode (SELPLL bit = 1). * To set the STOP mode in which the main clock is stopped, or to set the IDLE mode, first select the clockthrough mode and then stop the PLL. To return from the IDLE or STOP mode, first enable PLL operation (PLLON bit = 1), and then select the PLL mode (SELPLL bit = 1). * To enable the PLL operation, first set the PLLON bit to 1, wait for 200 s, and then set the SELPLL bit to 1. To stop the PLL, first select the clock-through mode (SELPLL bit = 0), wait for 8 clocks or more, and then stop the PLL (PLLON bit = 0). (2) When PLL is not used * The clock-through mode (SELPLL bit = 0) is selected after reset has been released, but the PLL is operating (PLLON bit = 1) and must therefore be stopped (PLLON bit = 0). Remark The PLL is operable in the IDLE mode. To realize low power consumption, stop the PLL. Be sure to stop the PLL when shifting to the STOP mode. User's Manual U16889EJ1V0UD 217 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Timer P (TMP) is a 16-bit timer/event counter. The following products have TMP0 of the V850ES/KJ1. PD70F3218H, 70F3218HY 7.1 Overview An outline of TMP0 is shown below. * Clock selection: 8 ways * Capture trigger input pins: 2 * External event count input pins: 1 * External trigger input pins: 1 * Timer/counters: 1 * Capture/compare registers: 2 * Capture/compare match interrupt request signals: 2 * Timer output pins: 2 7.2 Functions TMP0 has the following functions. * Interval timer * External event counter * External trigger pulse output * One-shot pulse output * PWM output * Free-running timer * Pulse width measurement 218 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.3 Configuration TMP0 includes the following hardware. Table 7-1. Configuration of TMP0 Item Timer register Registers 16-bit counter TMP0 capture/compare registers 0, 1 (TP0CCR0, TP0CCR1) TMP0 counter read buffer register (TP0CNT) CCR0, CCR1 buffer registers Timer inputs Timer outputs Control registers 2 (TIP00 Note Configuration , TIP01 pins) 2 (TOP00, TOP01 pins) TMP0 control registers 0, 1 (TP0CTL0, TP0CTL1) TMP0 I/O control registers 0 to 2 (TP0IOC0 to TP0IOC2) TMP0 option registers 0, 1 (TP0OPT0, TP0OPT1) Note The TIP00 pin functions alternately as a capture trigger input signal, external event count input signal, and external trigger input signal. Figure 7-1. Block Diagram of TMP0 Internal bus Output controller fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 TP0CNT Selector Selector 16-bit counter Clear INTTP0OV TOP00 TOP01 Edge detector CCR0 buffer register CCR1 buffer register INTTP0CC0 INTTP0CC1 TIP00 TIP01 Digital noise eliminator Edge detector TP0CCR0 TP0CCR1 Internal bus Remark fXX: Main clock frequency User's Manual U16889EJ1V0UD 219 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TP0CNT register. When the TP0CTL0.TP0CE bit = 0, the value of the 16-bit counter is FFFFH. If the TP0CNT register is read at this time, 0000H is read. Reset input clears the TP0CE bit to 0. Therefore, the 16-bit counter is set to FFFFH. (2) CCR0 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TP0CCR0 register is used as a compare register, the value written to the TP0CCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTP0CC0) is generated. The CCR0 buffer register cannot be read or written directly. The CCR0 buffer register is cleared to 0000H after reset, as the TP0CCR0 register is cleared to 0000H. (3) CCR1 buffer register This is a 16-bit compare register that compares the count value of the 16-bit counter. When the TP0CCR1 register is used as a compare register, the value written to the TP0CCR1 register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTP0CC1) is generated. The CCR1 buffer register cannot be read or written directly. The CCR1 buffer register is cleared to 0000H after reset, as the TP0CCR1 register is cleared to 0000H. (4) Edge detector This circuit detects the valid edges input to the TIP00 and TIP01 pins. No edge, rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the TP0IOC1 and TP0IOC2 registers. (5) Output controller This circuit controls the output of the TOP00 and TOP01 pins. The output controller is controlled by the TP0IOC0 register. (6) Selector This selector selects the count clock for the 16-bit counter. Eight types of internal clocks or an external event can be selected as the count clock. (7) Digital noise eliminator This circuit is valid only when the TIP0a pin is used as a capture trigger input pin. This circuit is controlled by the TIP0a noise elimination register (PaNFC). Remark a = 0, 1 220 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.4 Registers (1) TMP0 control register 0 (TP0CTL0) The TP0CTL0 register is an 8-bit register that controls the operation of TMP0. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. The same value can always be written to the TP0CTL0 register by software. After reset: 00H <7> R/W 6 0 Address: FFFFF5A0H 5 0 4 0 3 0 2 1 0 TP0CTL0 TP0CE TP0CKS2 TP0CKS1 TP0CKS0 TP0CE 0 1 TMP0 operation control TMP0 operation disabled (TMP0 reset asynchronouslyNote). TMP0 operation enabled. TMP0 operation started. TP0CKS2 TP0CKS1 TP0CKS0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 Internal count clock selection Note TP0OPT0.TP0OVF bit, 16-bit counter, timer output (TOP00, TOP01 pins) Cautions 1. Set the TP0CKS2 to TP0CKS0 bits when the TP0CE bit = 0. When the value of the TP0CE bit is changed from 0 to 1, the TP0CKS2 to TP0CKS0 bits can be set simultaneously. 2. Be sure to clear bits 3 to 6 to 0. Remark fXX: Main clock frequency User's Manual U16889EJ1V0UD 221 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) TMP0 control register 1 (TP0CTL1) The TP0CTL1 register is an 8-bit register that controls the operation of TMP0. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: 00H 7 R/W <6> TP0EST Address: FFFFF5A1H <5> TP0EEE 4 0 3 0 2 1 0 TP0CTL1 0 TP0MD2 TP0MD1 TP0MD0 TP0EST 0 1 Software trigger control - Generate a valid signal for external trigger input. * In one-shot pulse output mode: A one-shot pulse is output with writing 1 to the TP0EST bit as the trigger. * In external trigger pulse output mode: A PWM waveform is output with writing 1 to the TP0EST bit as the trigger. TP0EEE 0 Count clock selection Disable operation with external event count input. (Perform counting with the count clock selected by the TP0CTL0.TP0CK0 to TP0CTL0.TP0CK2 bits.) Enable operation with external event count input. (Perform counting at the valid edge of the external event count input signal.) 1 The TP0EEE bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. TP0MD2 TP0MD1 TP0MD0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Timer mode selection Interval timer mode External event count mode External trigger pulse output mode One-shot pulse output mode PWM output mode Free-running timer mode Pulse width measurement mode Setting prohibited Cautions 1. The TP0EST bit is valid only in the external trigger pulse output mode or one-shot pulse output mode. In any other mode, writing 1 to this bit is ignored. 2. External event count input is selected in the external event count mode regardless of the value of the TP0EEE bit. 3. Set the TP0EEE and TP0MD2 to TP0MD0 bits when the TP0CTL0.TP0CE bit = 0. (The same value can be written when the TP0CE bit = 1.) The operation is not guaranteed when rewriting is performed with the TP0CE bit = 1. If rewriting was mistakenly performed, clear the TP0CE bit to 0 and then set the bits again. 4. Be sure to clear bits 3, 4, and 7 to 0. 222 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (3) TMP0 I/O control register 0 (TP0IOC0) The TP0IOC0 register is an 8-bit register that controls the timer output (TOP00, TOP01 pins). This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: 00H 7 R/W 6 0 Address: FFFFF5A2H 5 0 4 0 3 <2> 1 TP0OL0 <0> TP0IOC0 0 TP0OL1 TP0OE1 TP0OE0 TP0OL1 0 1 TOP01 pin output level setting TOP01 pin output inversion disabled TOP01 pin output inversion enabled TP0OE1 0 TOP01 pin output setting Timer output disabled * When TP0OL1 bit = 0: Low level is output from the TOP01 pin * When TP0OL1 bit = 1: High level is output from the TOP01 pin Timer output enabled (a square wave is output from the TOP01 pin). 1 TP0OL0 0 1 TOP00 pin output level setting TOP00 pin output inversion disabled TOP00 pin output inversion enabled TP0OE0 0 TOP00 pin output setting Timer output disabled * When TP0OL0 bit = 0: Low level is output from the TOP00 pin * When TP0OL0 bit = 1: High level is output from the TOP00 pin Timer output enabled (a square wave is output from the TOP00 pin). 1 Cautions 1. Rewrite the TP0OL1, TP0OE1, TP0OL0, and TP0OE0 bits when the TP0CTL0.TP0CE bit = 0. (The same value can be written when the TP0CE bit = 1.) set the bits again. 2. Even if the TP0OLa bit is manipulated when the TP0CE and TP0OEa bits are 0, the TOP0a pin output level varies (a = 0, 1). If rewriting was mistakenly performed, clear the TP0CE bit to 0 and then User's Manual U16889EJ1V0UD 223 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (4) TMP0 I/O control register 1 (TP0IOC1) The TP0IOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIP00, TIP01 pins). This register can be read or written in 8-bit units. Reset input clears this register to 00H. After reset: 00H 7 R/W 6 0 Address: FFFFF5A3H 5 0 4 0 3 TP0IS3 2 TP0IS2 1 TP0IS1 0 TP0IOC1 0 TP0IS0 TP0IS3 0 0 1 1 TP0IS2 0 1 0 1 Capture trigger input signal (TIP01 pin) valid edge setting No edge detection (capture operation invalid) Detection of rising edge Detection of falling edge Detection of both edges TP0IS1 0 0 1 1 TP0IS0 0 1 0 1 Capture trigger input signal (TIP00 pin) valid edge setting No edge detection (capture operation invalid) Detection of rising edge Detection of falling edge Detection of both edges Cautions 1. Rewrite the TP0IS3 to TP0IS0 bits when the TP0CTL0.TP0CE bit = 0. (The same value can be written when the TP0CE bit = 1.) again. 2. The TP0IS3 to TP0IS0 bits are valid only in the freerunning timer mode and the pulse width measurement mode. In all other modes, a capture operation is not possible. If rewriting was mistakenly performed, clear the TP0CE bit to 0 and then set the bits 224 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (5) TMP0 I/O control register 2 (TP0IOC2) The TP0IOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIP00 pin) and external trigger input signal (TIP00 pin). This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: 00H 7 R/W 6 0 Address: FFFFF5A4H 5 0 4 0 3 2 1 0 TP0IOC2 0 TP0EES1 TP0EES0 TP0ETS1 TP0ETS0 TP0EES1 TP0EES0 External event count input signal (TIP00 pin) valid edge setting 0 0 1 1 0 1 0 1 No edge detection (external event count invalid) Detection of rising edge Detection of falling edge Detection of both edges TP0ETS1 TP0ETS0 0 0 1 1 0 1 0 1 External trigger input signal (TIP00 pin) valid edge setting No edge detection (external trigger invalid) Detection of rising edge Detection of falling edge Detection of both edges Cautions 1. Rewrite the TP0EES1, TP0EES0, TP0ETS1, and TP0ETS0 bits when the TP0CTL0.TP0CE bit = 0. (The same value can be written when the TP0CE bit = 1.) If rewriting was mistakenly performed, clear the TP0CE bit to 0 and then set the bits again. 2. The TP0EES1 and TP0EES0 bits are valid only when the TP0CTL1.TP0EEE bit = 1 or when the external event count mode (TP0CTL1.TP0MD2 to TP0CTL1.TP0MD0 bits = 001) has been set. User's Manual U16889EJ1V0UD 225 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (6) TMP0 option register 0 (TP0OPT0) The TP0OPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: 00H 7 R/W 6 0 Address: FFFFF5A5H 5 4 3 0 2 0 1 0 <0> TP0OPT0 0 TP0CCS1 TP0CCS0 TP0OVF TP0CCS1 0 1 TP0CCR1 register capture/compare selection Compare register selected Capture register selected The TP0CCS1 bit setting is valid only in the free-running timer mode. TP0CCS0 0 1 TP0CCR0 register capture/compare selection Compare register selected Capture register selected The TP0CCS0 bit setting is valid only in the free-running timer mode. TP0OVF Set (1) Reset (0) TMP0 overflow detection flag Overflow occurred TP0OVF bit 0 written or TP0CTL0.TP0CE bit = 0 * The TP0OVF bit is reset when the 16-bit counter count value overflows from FFFFH to 0000H in the free-running timer mode or the pulse width measurement mode. * An interrupt request signal (INTTP0OV) is generated at the same time that the TP0OVF bit is set to 1. The INTTP0OV signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. * The TP0OVF bit is not cleared even when the TP0OVF bit or the TP0OPT0 register are read when the TP0OVF bit = 1. * The TP0OVF bit can be both read and written, but the TP0OVF bit cannot be set to 1 by software. Writing 1 has no influence on the operation of TMP0. Cautions 1. Rewrite the TP0CCS1 and TP0CCS0 bits when the TP0CE bit = 0. (The same value can be written when the TP0CE bit = 1.) If rewriting was mistakenly performed, clear the TP0CE bit to 0 and then set the bits again. 2. Be sure to clear bits 1 to 3, 6, and 7 to 0. 226 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (7) TMP0 capture/compare register 0 (TP0CCR0) The TP0CCR0 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TP0OPT0.TP0CCS0 bit. In the pulse width measurement mode, the TP0CCR0 register can be used only as a capture register. In any other mode, this register can be used only as a compare register. The TP0CCR0 register can be read or written during operation. This register can be read or written in 16-bit units. Reset input clears this register to 0000H. Caution Accessing the TP0CCR0 register is disabled during subclock operation with the main clock stopped. For details, refer to 3.4.8 (2). After reset: 0000H 15 14 R/W 13 12 Address: FFFFF5A6H 11 10 9 8 7 6 5 4 3 2 1 0 TP0CCR0 User's Manual U16889EJ1V0UD 227 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (a) Function as compare register The TP0CCR0 register can be rewritten even when the TP0CTL0.TP0CE bit = 1. The set value of the TP0CCR0 register is transferred to the CCR0 buffer register. When the value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTP0CC0) is generated. If TOP00 pin output is enabled at this time, the output of the TOP00 pin is inverted. When the TP0CCR0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse output mode, or PWM output mode, the value of the 16-bit counter is cleared (0000H) if its count value matches the value of the CCR0 buffer register. (b) Function as capture register When the TP0CCR0 register is used as a capture register in the free-running timer mode, the count value of the 16-bit counter is stored in the TP0CCR0 register if the valid edge of the capture trigger input pin (TIP00 pin) is detected. In the pulse width measurement mode, the count value of the 16-bit counter is stored in the TP0CCR0 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin (TIP00 pin) is detected. Even if the capture operation and reading the TP0CCR0 register conflict, the correct value of the TP0CCR0 register can be read. The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 7-2. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode Interval timer External event counter External trigger pulse output One-shot pulse output PWM output Free-running timer Pulse width measurement Capture/Compare Register Compare register Compare register Compare register Compare register Compare register Capture/compare register Capture register How to Write Compare Register Anytime write Anytime write Batch write Anytime write Batch write Anytime write - 228 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (8) TMP0 capture/compare register 1 (TP0CCR1) The TP0CCR1 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TP0OPT0.TP0CCS1 bit. In the pulse width measurement mode, the TP0CCR1 register can be used only as a capture register. In any other mode, this register can be used only as a compare register. The TP0CCR1 register can be read or written during operation. This register can be read or written in 16-bit units. Reset input clears this register to 0000H. Caution Accessing the TP0CCR1 register is disabled during subclock operation with the main clock stopped. For details, refer to 3.4.8 (2). After reset: 0000H 15 14 R/W 13 12 Address: FFFFF5A8H 11 10 9 8 7 6 5 4 3 2 1 0 TP0CCR1 User's Manual U16889EJ1V0UD 229 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (a) Function as compare register The TP0CCR1 register can be rewritten even when the TP0CTL0.TP0CE bit = 1. The set value of the TP0CCR1 register is transferred to the CCR1 buffer register. When the value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTP0CC1) is generated. If TOP01 pin output is enabled at this time, the output of the TOP01 pin is inverted. (b) Function as capture register When the TP0CCR1 register is used as a capture register in the free-running timer mode, the count value of the 16-bit counter is stored in the TP0CCR1 register if the valid edge of the capture trigger input pin (TIP01 pin) is detected. In the pulse width measurement mode, the count value of the 16-bit counter is stored in the TP0CCR1 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin (TIP01 pin) is detected. Even if the capture operation and reading the TP0CCR1 register conflict, the correct value of the TP0CCR1 register can be read. The following table shows the functions of the capture/compare register in each mode, and how to write data to the compare register. Table 7-3. Function of Capture/Compare Register in Each Mode and How to Write Compare Register Operation Mode Interval timer External event counter External trigger pulse output One-shot pulse output PWM output Free-running timer Pulse width measurement Capture/Compare Register Compare register Compare register Compare register Compare register Compare register Capture/compare register Capture register How to Write Compare Register Anytime write Anytime write Batch write Anytime write Batch write Anytime write - 230 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (9) TMP0 counter read buffer register (TP0CNT) The TP0CNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TP0CTL0.TP0CE bit = 1, the count value of the 16-bit timer can be read. This register is read-only, in 16-bit units. The value of the TP0CNT register is cleared to 0000H when the TP0CE bit = 0. If the TP0CNT register is read at this time, the value of the 16-bit counter (FFFFH) is not read, but 0000H is read. The value of the TP0CNT register is cleared to 0000H after reset, as the TP0CE bit is cleared to 0. Caution Accessing the TP0CNT register is disabled during subclock operation with the main clock stopped. For details, refer to 3.4.8 (2). After reset: 0000H 15 14 R 13 12 Address: FFFFF5AAH 11 10 9 8 7 6 5 4 3 2 1 0 TP0CNT User's Manual U16889EJ1V0UD 231 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5 Operation TMP0 can perform the following operations. Operation TP0CTL1.TP0EST Bit TIP00 Pin Capture/Compare Register Setting Compare only Compare only Compare only Compare only Compare only Switching enabled Capture only Compare Register Write Anytime write Anytime write Batch write Anytime write Batch write Anytime write Not applicable (Software Trigger Bit) (External Trigger Input) Interval timer mode External event count mode Note 1 Invalid Invalid Note 2 Invalid Invalid Valid Valid Invalid Invalid Invalid External trigger pulse output mode One-shot pulse output mode PWM output mode Free-running timer mode Pulse width measurement mode Note 2 Valid Valid Invalid Invalid Note 2 Invalid Notes 1. To use the external event count mode, specify that the valid edge of the TIP00 pin capture trigger input is not detected (by clearing the TP0IOC1.TP0IS1 and TP0IOC1.TP0IS0 bits to "00"). 2. When using the external trigger pulse output mode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by clearing the TP0CTL1.TP0EEE bit to 0). 232 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.1 Interval timer mode (TP0MD2 to TP0MD0 bits = 000) In the interval timer mode, an interrupt request signal (INTTP0CC0) is generated at the specified interval if the TP0CTL0.TP0CE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOP00 pin. Usually, the TP0CCR1 register is not used in the interval timer mode. Figure 7-2. Configuration of Interval Timer Clear Count clock selection 16-bit counter Match signal Output controller TOP00 pin INTTP0CC0 signal TP0CE bit CCR0 buffer register TP0CCR0 register Figure 7-3. Basic Timing of Operation in Interval Timer Mode FFFFH 16-bit counter 0000H TP0CE bit TP0CCR0 register TOP00 pin output INTTP0CC0 signal Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1) Interval (D0 + 1) D0 D0 D0 D0 D0 User's Manual U16889EJ1V0UD 233 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TP0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOP00 pin is inverted. Additionally, the set value of the TP0CCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared to 0000H, the output of the TOP00 pin is inverted, and a compare match interrupt request signal (INTTP0CC0) is generated. The interval can be calculated by the following expression. Interval = (Set value of TP0CCR0 register + 1) x Count clock cycle Figure 7-4. Register Setting for Interval Timer Mode Operation (1/2) (a) TMP0 control register 0 (TP0CTL0) TP0CE TP0CTL0 0/1 0 0 0 0 TP0CKS2 TP0CKS1 TP0CKS0 0/1 0/1 0/1 Select count clock 0: Stop counting 1: Enable counting (b) TMP0 control register 1 (TP0CTL1) TP0EST TP0EEE TP0CTL1 0 0 0 0 0 TP0MD2 TP0MD1 TP0MD0 0 0 0 0, 0, 0: Interval timer mode (c) TMP0 I/O control register 0 (TP0IOC0) TP0OL1 TP0IOC0 0 0 0 0 0/1 TP0OE1 TP0OL0 0/1 0/1 TP0OE0 0/1 0: Disable TOP00 pin output 1: Enable TOP00 pin output Setting of output level with operation of TOP00 pin disabled 0: Low level 1: High level 0: Disable TOP01 pin output 1: Enable TOP01 pin output Setting of output level with operation of TOP01 pin disabled 0: Low level 1: High level 234 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-4. Register Setting for Interval Timer Mode Operation (2/2) (d) TMP0 counter read buffer register (TP0CNT) By reading the TP0CNT register, the count value of the 16-bit counter can be read. (e) TMP0 capture/compare register 0 (TP0CCR0) If the TP0CCR0 register is set to D0, the interval is as follows. Interval = (D0 + 1) x Count clock cycle (f) TMP0 capture/compare register 1 (TP0CCR1) Usually, the TP0CCR1 register is not used in the interval timer mode. However, the set value of the TP0CCR1 register is transferred to the CCR1 buffer register. A compare match interrupt request signal (INTTP0CC1) is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register. Therefore, mask the interrupt request by using the corresponding interrupt mask flag (TP0CCMK1). Remark TMP0 I/O control register 1 (TP0IOC1), TMP0 I/O control register 2 (TP0IOC2), and TMP0 option register 0 (TP0OPT0) are not used in the interval timer mode. User's Manual U16889EJ1V0UD 235 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Interval timer mode operation flow Figure 7-5. Software Processing Flow in Interval Timer Mode FFFFH 16-bit counter 0000H TP0CE bit TP0CCR0 register TOP00 pin output INTTP0CC0 signal D0 D0 D0 D0 <1> <2> <1> Count operation start flow START Register initial setting TP0CTL0 register (TP0CKS0 to TP0CKS2 bits) TP0CTL1 register, TP0IOC0 register, TP0CCR0 register Initial setting of these registers is performed before setting the TP0CE bit to 1. TP0CE bit = 1 The TP0CKS0 to TP0CKS2 bits can be set at the same time when counting has been started (TP0CE bit = 1). <2> Count operation stop flow The counter is initialized and counting is stopped by clearing the TP0CE bit to 0. TP0CE bit = 0 STOP 236 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Interval timer mode operation timing (a) Operation if TP0CCR0 register is cleared to 0000H If the TP0CCR0 register is cleared to 0000H, the INTTP0CC0 signal is generated at each count clock, and the output of the TOP00 pin is inverted. The value of the 16-bit counter is always 0000H. Count clock 16-bit counter TP0CE bit TP0CCR0 register TOP00 pin output INTTP0CC0 signal Interval time Interval time Interval time Count clock cycle Count clock cycle Count clock cycle 0000H FFFFH 0000H 0000H 0000H 0000H User's Manual U16889EJ1V0UD 237 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Operation if TP0CCR0 register is set to FFFFH If the TP0CCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to 0000H in synchronization with the next count-up timing. The INTTP0CC0 signal is generated and the output of the TOP00 pin is inverted. At this time, an overflow interrupt request signal (INTTP0OV) is not generated, nor is the overflow flag (TP0OPT0.TP0OVF bit) set to 1. FFFFH 16-bit counter 0000H TP0CE bit TP0CCR0 register TOP00 pin output INTTP0CC0 signal Interval time Interval time Interval time 10000H x 10000H x 10000H x count clock cycle count clock cycle count clock cycle FFFFH 238 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Notes on rewriting TP0CCR0 register To change the value of the TP0CCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TP0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. FFFFH D1 16-bit counter 0000H TP0CE bit TP0CCR0 register TP0OL0 bit TOP00 pin output INTTP0CC0 signal L D1 D2 D2 D1 D2 D2 Interval time (1) Interval time (NG) Interval time (2) Remark Interval time (1): (D1 + 1) x Count clock cycle Interval time (NG): (10000H + D2 + 1) x Count clock cycle Interval time (2): (D2 + 1) x Count clock cycle If the value of the TP0CCR0 register is changed from D1 to D2 while the count value is greater than D2 but less than D1, the count value is transferred to the CCR0 buffer register as soon as the TP0CCR0 register has been rewritten. Consequently, the value of the 16-bit counter that is compared is D2. Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows, and then counts up again from 0000H. When the count value matches D2, the INTTP0CC0 signal is generated and the output of the TOP00 pin is inverted. Therefore, the INTTP0CC0 signal may not be generated at the interval time "(D1 + 1) x Count clock cycle" or "(D2 + 1) x Count clock cycle" originally expected, but may be generated at an interval of "(10000H + D2 + 1) x Count clock period". User's Manual U16889EJ1V0UD 239 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Operation of TP0CCR1 register Figure 7-6. Configuration of TP0CCR1 Register TP0CCR1 register CCR1 buffer register Match signal Clear Output controller TOP01 pin INTTP0CC1 signal Count clock selection 16-bit counter Match signal Output controller TOP00 pin INTTP0CC0 signal TP0CE bit CCR0 buffer register TP0CCR0 register 240 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TP0CCR1 register is less than the set value of the TP0CCR0 register, the INTTP0CC1 signal is generated once per cycle. At the same time, the output of the TOP01 pin is inverted. The TOP01 pin outputs a square wave with the same cycle as that output by the TOP00 pin. Figure 7-7. Timing Chart When D01 D11 FFFFH D01 16-bit counter 0000H TP0CE bit TP0CCR0 register TOP00 pin output INTTP0CC0 signal TP0CCR1 register TOP01 pin output INTTP0CC1 signal D11 D01 D11 D11 D01 D11 D01 D11 D01 User's Manual U16889EJ1V0UD 241 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TP0CCR1 register is greater than the set value of the TP0CCR0 register, the count value of the 16-bit counter does not match the value of the TP0CCR1 register. INTTP0CC1 signal is not generated, nor is the output of the TOP01 pin changed. Figure 7-8. Timing Chart When D01 < D11 Consequently, the FFFFH D01 16-bit counter 0000H TP0CE bit TP0CCR0 register TOP00 pin output INTTP0CC0 signal TP0CCR1 register TOP01 pin output INTTP0CC1 signal L D11 D01 D01 D01 D01 242 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.2 External event count mode (TP0MD2 to TP0MD0 bits = 001) In the external event count mode, the valid edge of the external event count input is counted when the TP0CTL0.TP0CE bit is set to 1, and an interrupt request signal (INTTP0CC0) is generated each time the specified number of edges have been counted. The TOP00 pin cannot be used. Usually, the TP0CCR1 register is not used in the external event count mode. Figure 7-9. Configuration in External Event Count Mode Clear TIP00 pin (external event count input) Edge detector 16-bit counter Match signal INTTP0CC0 signal TP0CE bit CCR0 buffer register TP0CCR0 register Figure 7-10. Basic Timing in External Event Count Mode FFFFH 16-bit counter 0000H TP0CE bit TP0CCR0 register INTTP0CC0 signal External event count interval (D0 + 1) External event count interval (D0 + 1) External event count interval (D0 + 1) D0 D0 D0 D0 D0 - 1 16-bit counter External event count input (TIP00 pin input) TP0CCR0 register INTTP0CC0 signal D0 0000 0001 D0 Remark This figure shows the basic timing when the rising edge is specified as the valid edge of the external event count input. User's Manual U16889EJ1V0UD 243 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TP0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TP0CCR0 register is transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared to 0000H, and a compare match interrupt request signal (INTTP0CC0) is generated. The INTTP0CC0 signal is generated each time the valid edge of the external event count input has been detected (set value of TP0CCR0 register + 1) times. Figure 7-11. Register Setting for Operation in External Event Count Mode (1/2) (a) TMP0 control register 0 (TP0CTL0) TP0CE TP0CTL0 0/1 0 0 0 0 TP0CKS2 TP0CKS1 TP0CKS0 0 0 0 0: Stop counting 1: Enable counting (b) TMP0 control register 1 (TP0CTL1) TP0EST TP0EEE TP0CTL1 0 0 0 0 0 TP0MD2 TP0MD1 TP0MD0 0 0 1 0, 0, 1: External event count mode (c) TMP0 I/O control register 0 (TP0IOC0) TP0OL1 TP0IOC0 0 0 0 0 0/1 TP0OE1 TP0OL0 0/1 0 TP0OE0 0 0: Disable TOP00 pin output 0: Disable TOP01 pin output 1: Enable TOP01 pin output Setting of output level with operation of TOP01 pin disabled 0: Low level 1: High level (d) TMP0 I/O control register 2 (TP0IOC2) TP0EES1 TP0EES0 TP0ETS1 TP0ETS0 TP0IOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input 244 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-11. Register Setting for Operation in External Event Count Mode (2/2) (e) TMP0 counter read buffer register (TP0CNT) The count value of the 16-bit counter can be read by reading the TP0CNT register. (f) TMP0 capture/compare register 0 (TP0CCR0) If D0 is set to the TP0CCR0 register, the counter is cleared and a compare match interrupt request signal (INTTP0CC0) is generated when the number of external event counts reaches (D0 + 1). (g) TMP0 capture/compare register 1 (TP0CCR1) Usually, the TP0CCR1 register is not used in the external event count mode. However, the set value of the TP0CCR1 register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTP0CC1) is generated. Therefore, mask the interrupt signal by using the interrupt mask flag (TP0CCMK1). Remark TMP0 I/O control register 1 (TP0IOC1) and TMP0 option register 0 (TP0OPT0) are not used in the external event count mode. User's Manual U16889EJ1V0UD 245 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) External event count mode operation flow Figure 7-12. Flow of Software Processing in External Event Count Mode FFFFH 16-bit counter 0000H TP0CE bit TP0CCR0 register INTTP0CC0 signal D0 D0 D0 D0 <1> <2> <1> Count operation start flow START Register initial setting TP0CTL0 register (TP0CKS0 to TP0CKS2 bits) TP0CTL1 register, TP0IOC0 register, TP0IOC2 register, TP0CCR0 register Initial setting of these registers is performed before setting the TP0CE bit to 1. TP0CE bit = 1 The TP0CKS0 to TP0CKS2 bits can be set at the same time when counting has been started (TP0CE bit = 1). <2> Count operation stop flow The counter is initialized and counting is stopped by clearing the TP0CE bit to 0. TP0CE bit = 0 STOP 246 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in external event count mode (a) Operation if TP0CCR0 register is cleared to 0000H If the TP0CCR0 register is cleared to 0000H, the INTTP0CC0 signal is generated each time the valid signal of the external event count signal has been detected. The 16-bit counter is always 0000H. External event count signal 16-bit counter TP0CE bit TP0CCR0 register INTTP0CC0 signal External event count signal interval External event count signal interval External event count signal interval 0000H FFFFH 0000H 0000H 0000H 0000H (b) Operation if TP0CCR0 register is set to FFFFH If the TP0CCR0 register is set to FFFFH, the 16-bit counter counts to FFFFH each time the valid edge of the external event count signal has been detected. TP0OPT0.TP0OVF bit is not set. The 16-bit counter is cleared to 0000H in synchronization with the next count-up timing, and the INTTP0CC0 signal is generated. At this time, the FFFFH 16-bit counter 0000H TP0CE bit TP0CCR0 register INTTP0CC0 signal External event count signal interval External event count signal interval External event count signal interval FFFFH User's Manual U16889EJ1V0UD 247 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Notes on rewriting the TP0CCR0 register To change the value of the TP0CCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TP0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. FFFFH D1 16-bit counter 0000H TP0CE bit TP0CCR0 register INTTP0CC0 signal D1 D2 D2 D1 D2 D2 External event count signal interval (1) (D1 + 1) External event count signal interval (NG) (10000H + D2 + 1) External event count signal interval (2) (D2 + 1) If the value of the TP0CCR0 register is changed from D1 to D2 while the count value is greater than D2 but less than D1, the count value is transferred to the CCR0 buffer register as soon as the TP0CCR0 register has been rewritten. Consequently, the value that is compared with the 16-bit counter is D2. Because the count value has already exceeded D2, however, the 16-bit counter counts up to FFFFH, overflows, and then counts up again from 0000H. When the count value matches D2, the INTTP0CC0 signal is generated. Therefore, the INTTP0CC0 signal may not be generated at the valid edge count of "(D1 + 1) times" or "(D2 + 1) times" originally expected, but may be generated at the valid edge count of "(10000H + D2 + 1) times". 248 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Operation of TP0CCR1 register Figure 7-13. Configuration of TP0CCR1 Register TP0CCR1 register CCR1 buffer register Match signal Clear Output controller TOP01 pin INTTP0CC1 signal TIP00 pin Edge detector 16-bit counter Match signal INTTP0CC0 signal TP0CE bit CCR0 buffer register TP0CCR0 register If the set value of the TP0CCR1 register is smaller than the set value of the TP0CCR0 register, the INTTP0CC1 signal is generated once per cycle. At the same time, the output signal of the TOP01 pin is inverted. Figure 7-14. Timing Chart When D01 D11 FFFFH D01 16-bit counter 0000H TP0CE bit TP0CCR0 register INTTP0CC0 signal TP0CCR1 register TOP01 pin output INTTP0CC1 signal D11 D01 D11 D11 D01 D11 D01 D11 D01 User's Manual U16889EJ1V0UD 249 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TP0CCR1 register is greater than the set value of the TP0CCR0 register, the INTTP0CC1 signal is not generated because the count value of the 16-bit counter and the value of the TP0CCR1 register do not match. Nor is the output signal of the TOP01 pin changed. Figure 7-15. Timing Chart When D01 < D11 FFFFH D01 16-bit counter 0000H TP0CE bit TP0CCR0 register INTTP0CC0 signal TP0CCR1 register TOP01 pin output INTTP0CC1 signal L D11 D01 D01 D01 D01 250 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.3 External trigger pulse output mode (TP0MD2 to TP0MD0 bits = 010) In the external trigger pulse output mode, 16-bit timer/event counter P waits for a trigger when the TP0CTL0.TP0CE bit is set to 1. When the valid edge of an external trigger input signal is detected, 16-bit timer/event counter P starts counting, and outputs a PWM waveform from the TOP01 pin. Pulses can also be output by generating a software trigger instead of using the external trigger. When using a software trigger, a square wave that has one cycle of the PWM waveform as half its cycle can also be output from the TOP00 pin. Figure 7-16. Configuration in External Trigger Pulse Output Mode TP0CCR1 register TIP00 pin Edge detector CCR1 buffer register Software trigger generation Match signal Clear Count clock selection Count start control Transfer Output S controller R (RS-FF) TOP01 pin INTTP0CC1 signal 16-bit counter Match signal Output controller TOP00 pin INTTP0CC0 signal TP0CE bit CCR0 buffer register Transfer TP0CCR0 register User's Manual U16889EJ1V0UD 251 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-17. Basic Timing in External Trigger Pulse Output Mode FFFFH D0 16-bit counter 0000H TP0CE bit External trigger input (TIP00 pin input) TP0CCR0 register INTTP0CC0 signal TOP00 pin output (software trigger) TP0CCR1 register INTTP0CC1 signal TOP01 pin output Wait Active level for width (D1) trigger Cycle (D0 + 1) Active level width (D1) Cycle (D0 + 1) Active level width (D1) Cycle (D0 + 1) D1 D0 D1 D1 D0 D1 D0 D1 D0 16-bit timer/event counter P waits for a trigger when the TP0CE bit is set to 1. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from the TOP01 pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and restarted. The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows. Active level width = (Set value of TP0CCR1 register) x Count clock cycle Cycle = (Set value of TP0CCR0 register + 1) x Count clock cycle Duty factor = (Set value of TP0CCR1 register)/(Set value of TP0CCR0 register + 1) The compare match interrupt request signal INTTP0CC0 is generated when the 16-bit counter counts next time after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal INTTP0CC1 is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register. The value set to the TP0CCRa register is transferred to the CCRa buffer register when the count value of the 16-bit counter matches the value of the CCRa buffer register and the 16-bit counter is cleared to 0000H. The valid edge of an external trigger input signal, or setting the software trigger (TP0CTL1.TP0EST bit) to 1 is used as the trigger. Remark a = 0, 1 User's Manual U16889EJ1V0UD 252 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-18. Setting of Registers in External Trigger Pulse Output Mode (1/2) (a) TMP0 control register 0 (TP0CTL0) TP0CE TP0CTL0 0/1 0 0 0 0 TP0CKS2 TP0CKS1 TP0CKS0 0/1 0/1 0/1 Select count clockNote 0: Stop counting 1: Enable counting Note The setting is invalid when the TP0CTL1.TP0EEE bit = 1. (b) TMP0 control register 1 (TP0CTL1) TP0EST TP0EEE TP0CTL1 0 0/1 0/1 0 0 TP0MD2 TP0MD1 TP0MD0 0 1 0 0, 1, 0: External trigger pulse output mode 0: Operate on count clock selected by TP0CKS0 to TP0CKS2 bits 1: Count with external event input signal Generate software trigger when 1 is written (c) TMP0 I/O control register 0 (TP0IOC0) TP0OL1 TP0IOC0 0 0 0 0 0/1 TP0OE1 TP0OL0 0/1 0/1 TP0OE0 0/1 0: Disable TOP00 pin output 1: Enable TOP00 pin output Settings of output level while operation of TOP00 pin is disabled 0: Low level 1: High level 0: Disable TOP01 pin output 1: Enable TOP01 pin output Specifies active level of TOP01 pin output 0: Active-high 1: Active-low * When TP0OL1 bit = 0 16-bit counter TOP01 pin output * When TP0OL1 bit = 1 16-bit counter TOP01 pin output User's Manual U16889EJ1V0UD 253 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-18. Setting of Registers in External Trigger Pulse Output Mode (2/2) (d) TMP0 I/O control register 2 (TP0IOC2) TP0EES1 TP0EES0 TP0ETS1 TP0ETS0 TP0IOC2 0 0 0 0 0/1 0/1 0/1 0/1 Select valid edge of external trigger input Select valid edge of external event count input (e) TMP0 counter read buffer register (TP0CNT) The value of the 16-bit counter can be read by reading the TP0CNT register. (f) TMP0 capture/compare registers 0 and 1 (TP0CCR0 and TP0CCR1) If D0 is set to the TP0CCR0 register and D1 to the TP0CCR1 register, the cycle and active level of the PWM waveform are as follows. Cycle = (D0 + 1) x Count clock cycle Active level width = D1 x Count clock cycle Remark TMP0 I/O control register 1 (TP0IOC1) and TMP0 option register 0 (TP0OPT0) are not used in the external trigger pulse output mode. 254 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in external trigger pulse output mode Figure 7-19. Software Processing Flow in External Trigger Pulse Output Mode (1/2) FFFFH D01 16-bit counter 0000H TP0CE bit External trigger input (TIP00 pin input) TP0CCR0 register CCR0 buffer register INTTP0CC0 signal TOP00 pin output (software trigger) TP0CCR1 register CCR1 buffer register INTTP0CC1 signal TOP01 pin output D10 D10 D10 D10 D11 D11 D10 D10 D00 D00 D01 D01 D00 D00 D00 D10 D00 D10 D10 D11 D01 D11 D01 D00 D10 <1> <2> <3> <4> <5> User's Manual U16889EJ1V0UD 255 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-19. Software Processing Flow in External Trigger Pulse Output Mode (2/2) <1> Count operation start flow <3> TP0CCR0, TP0CCR1 register setting change flow Only writing of the TP0CCR1 register must be performed when the set duty factor is changed. When the counter is cleared after setting, the value of the TP0CCRa register is transferred to the CCRa buffer register. START Setting of TP0CCR1 register Register initial setting TP0CTL0 register (TP0CKS0 to TP0CKS2 bits) TP0CTL1 register, TP0IOC0 register, TP0IOC2 register, TP0CCR0 register, TP0CCR1 register Initial setting of these registers is performed before setting the TP0CE bit to 1. <4> TP0CCR0, TP0CCR1 register setting change flow The TP0CKS0 to TP0CKS2 bits can be set at the same time when counting is enabled (TP0CE bit = 1). Trigger wait status TP0CE bit = 1 Setting of TP0CCR0 register When the counter is cleared after setting, the value of the TP0CCRa register is transferred to the CCRa buffer register. Setting of TP0CCR1 register <2> TP0CCR0 and TP0CCR1 register setting change flow <5> Count operation stop flow Setting of TP0CCR0 register TP0CCR1 register write processing is necessary only when the set cycle is changed. When the counter is cleared after setting, the value of the TP0CCRa register is transferred to the CCRa buffer register. TP0CE bit = 0 Counting is stopped. Setting of TP0CCR1 register STOP Remark a = 0, 1 256 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TP0CCR1 register last. Rewrite the TP0CCRa register after writing the TP0CCR1 register after the INTTP0CC0 signal is detected. FFFFH D01 16-bit counter 0000H TP0CE bit External trigger input (TIP00 pin input) TP0CCR0 register CCR0 buffer register INTTP0CC0 signal TOP00 pin output (software trigger) TP0CCR1 register CCR1 buffer register INTTP0CC1 signal TOP01 pin output D10 D10 D11 D11 D00 D00 D01 D01 D00 D10 D00 D10 D00 D10 D11 D11 D01 User's Manual U16889EJ1V0UD 257 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) In order to transfer data from the TP0CCRa register to the CCRa buffer register, the TP0CCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TP0CCR0 register and then set the active level width to the TP0CCR1 register. To change only the cycle of the PWM waveform, first set the cycle to the TP0CCR0 register, and then write the same value to the TP0CCR1 register. To change only the active level width (duty factor) of the PWM waveform, only the TP0CCR1 register has to be set. After data is written to the TP0CCR1 register, the value written to the TP0CCRa register is transferred to the CCRa buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared with the 16-bit counter. To write the TP0CCR0 or TP0CCR1 register again after writing the TP0CCR1 register once, do so after the INTTP0CC0 signal is generated. Otherwise, the value of the CCRa buffer register may become undefined because the timing of transferring data from the TP0CCRa register to the CCRa buffer register conflicts with writing the TP0CCRa register. Remark a = 0, 1 258 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) 0%/100% output of PWM waveform To output a 0% waveform, clear the TP0CCR1 register to 0000H. If the set value of the TP0CCR0 register is FFFFH, the INTTP0CC1 signal is generated periodically. Count clock 16-bit counter TP0CE bit TP0CCR0 register TP0CCR1 register INTTP0CC0 signal INTTP0CC1 signal TOP01 pin output D0 0000H D0 0000H D0 0000H FFFF 0000 D0 - 1 D0 0000 0001 D0 - 1 D0 0000 To output a 100% waveform, set a value of (set value of TP0CCR0 register + 1) to the TP0CCR1 register. If the set value of the TP0CCR0 register is FFFFH, 100% output cannot be produced. Count clock 16-bit counter TP0CE bit TP0CCR0 register TP0CCR1 register INTTP0CC0 signal INTTP0CC1 signal TOP01 pin output D0 D0 + 1 D0 D0 + 1 D0 D0 + 1 FFFF 0000 D0 - 1 D0 0000 0001 D0 - 1 D0 0000 User's Manual U16889EJ1V0UD 259 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Conflict between trigger detection and match with TP0CCR1 register If the trigger is detected immediately after the INTTP0CC1 signal is generated, the 16-bit counter is immediately cleared to 0000H, the output signal of the TOP01 pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened. 16-bit counter External trigger input (TIP00 pin input) TP0CCR1 register INTTP0CC1 signal TOP01 pin output FFFF 0000 D1 - 1 0000 D1 Shortened If the trigger is detected immediately before the INTTP0CC1 signal is generated, the INTTP0CC1 signal is not generated, and the 16-bit counter is cleared to 0000H and continues counting. The output signal of the TOP01 pin remains active. Consequently, the active period of the PWM waveform is extended. 16-bit counter External trigger input (TIP00 pin input) TP0CCR1 register INTTP0CC1 signal TOP01 pin output FFFF 0000 D1 - 2 0000 0001 D1 - 1 D1 D1 Extended 260 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Conflict between trigger detection and match with TP0CCR0 register If the trigger is detected immediately after the INTTP0CC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up. Therefore, the active period of the TOP01 pin is extended by time from generation of the INTTP0CC0 signal to trigger detection. 16-bit counter External trigger input (TIP00 pin input) TP0CCR0 register INTTP0CC0 signal TOP01 pin output FFFF 0000 D0 - 1 D0 0000 0000 D0 Extended If the trigger is detected immediately before the INTTP0CC0 signal is generated, the INTTP0CC0 signal is not generated. The 16-bit counter is cleared to 0000H, the TOP01 pin is asserted, and the counter continues counting. Consequently, the inactive period of the PWM waveform is shortened. 16-bit counter External trigger input (TIP00 pin input) TP0CCR0 register INTTP0CC0 signal TOP01 pin output FFFF 0000 D0 - 1 D0 0000 0001 D0 Shortened User's Manual U16889EJ1V0UD 261 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (e) Generation timing of compare match interrupt request signal (INTTP0CC1) The timing of generation of the INTTP0CC1 signal in the external trigger pulse output mode differs from the timing of other INTTP0CC1 signals; the INTTP0CC1 signal is generated when the count value of the 16-bit counter matches the value of the TP0CCR1 register. Count clock 16-bit counter TP0CCR1 register TOP01 pin output INTTP0CC1 signal D1 - 1 D1 - 1 D1 D1 D1 + 1 D1 + 2 Usually, the INTTP0CC1 signal is generated in synchronization with the next count up, after the count value of the 16-bit counter matches the value of the TP0CCR1 register. In the external trigger pulse output mode, however, it is generated one clock earlier. This is because the timing is changed to match the timing of changing the output signal of the TOP01 pin. 262 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.4 One-shot pulse output mode (TP0MD2 to TP0MD0 bits = 011) In the one-shot pulse output mode, 16-bit timer/event counter P waits for a trigger when the TP0CTL0.TP0CE bit is set to 1. When the valid edge of an external trigger input is detected, 16-bit timer/event counter P starts counting, and outputs a one-shot pulse from the TOP01 pin. Instead of the external trigger, a software trigger can also be generated to output the pulse. When the software trigger is used, the TOP00 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the counter is stopped (waiting for a trigger). Figure 7-20. Configuration in One-Shot Pulse Output Mode TP0CCR1 register TIP00 pin Edge detector CCR1 buffer register Software trigger generation Match signal Clear Count clock selection Count start control Output S controller R (RS-FF) Transfer Output S controller R (RS-FF) TOP01 pin INTTP0CC1 signal 16-bit counter Match signal TOP00 pin INTTP0CC0 signal TP0CE bit CCR0 buffer register Transfer TP0CCR0 register User's Manual U16889EJ1V0UD 263 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-21. Basic Timing in One-Shot Pulse Output Mode FFFFH D0 16-bit counter 0000H TP0CE bit External trigger input (TIP00 pin input) TP0CCR0 register INTTP0CC0 signal TOP00 pin output (software trigger) TP0CCR1 register INTTP0CC1 signal TOP01 pin output Delay (D1) Active level width (D0 - D1 + 1) Delay (D0) Delay Active level width (D1) (D0 - D1 + 1) Active level width (D0 - D1 + 1) D1 D0 D1 D1 D0 D1 D0 When the TP0CE bit is set to 1, 16-bit timer/event counter P waits for a trigger. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOP01 pin. After the one-shot pulse is output, the 16-bit counter is set to FFFFH, stops counting, and waits for a trigger. If a trigger is generated again while the one-shot pulse is being output, it is ignored. The output delay period and active level width of the one-shot pulse can be calculated as follows. Output delay period = (Set value of TP0CCR1 register) x Count clock cycle Active level width = (Set value of TP0CCR0 register - Set value of TP0CCR1 register + 1) x Count clock cycle The compare match interrupt request signal INTTP0CC0 is generated when the 16-bit counter counts after its count value matches the value of the CCR0 buffer register. The compare match interrupt request signal INTTP0CC1 is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register. The valid edge of an external trigger input or setting the software trigger (TP0CTL1.TP0EST bit) to 1 is used as the trigger. 264 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-22. Setting of Registers in One-Shot Pulse Output Mode (1/2) (a) TMP0 control register 0 (TP0CTL0) TP0CE TP0CTL0 0/1 0 0 0 0 TP0CKS2 TP0CKS1 TP0CKS0 0/1 0/1 0/1 Select count clockNote 0: Stop counting 1: Enable counting Note The setting is invalid when the TP0CTL1.TP0EEE bit = 1. (b) TMP0 control register 1 (TP0CTL1) TP0EST TP0EEE TP0CTL1 0 0/1 0/1 0 0 TP0MD2 TP0MD1 TP0MD0 0 1 1 0, 1, 1: One-shot pulse output mode 0: Operate on count clock selected by TP0CKS0 to TP0CKS2 bits 1: Count external event input signal Generate software trigger when 1 is written (c) TMP0 I/O control register 0 (TP0IOC0) TP0OL1 TP0IOC0 0 0 0 0 0/1 TP0OE1 TP0OL0 0/1 0/1 TP0OE0 0/1 0: Disable TOP00 pin output 1: Enable TOP00 pin output Setting of output level while operation of TOP00 pin is disabled 0: Low level 1: High level 0: Disable TOP01 pin output 1: Enable TOP01 pin output Specifies active level of TOP01 pin output 0: Active-high 1: Active-low * When TP0OL1 bit = 0 16-bit counter TOP01 pin output * When TP0OL1 bit = 1 16-bit counter TOP01 pin output User's Manual U16889EJ1V0UD 265 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-22. Setting of Registers in One-Shot Pulse Output Mode (2/2) (d) TMP0 I/O control register 2 (TP0IOC2) TP0EES1 TP0EES0 TP0ETS1 TP0ETS0 TP0IOC2 0 0 0 0 0/1 0/1 0/1 0/1 Select valid edge of external trigger input Select valid edge of external event count input (e) TMP0 counter read buffer register (TP0CNT) The value of the 16-bit counter can be read by reading the TP0CNT register. (f) TMP0 capture/compare registers 0 and 1 (TP0CCR0 and TP0CCR1) If D0 is set to the TP0CCR0 register and D1 to the TP0CCR1 register, the active level width and output delay period of the one-shot pulse are as follows. Active level width = (D1 - D0 + 1) x Count clock cycle Output delay period = D1 x Count clock cycle Remark TMP0 I/O control register 1 (TP0IOC1) and TMP0 option register 0 (TP0OPT0) are not used in the one-shot pulse output mode. 266 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in one-shot pulse output mode Figure 7-23. Software Processing Flow in One-Shot Pulse Output Mode FFFFH D0 16-bit counter 0000H TP0CE bit External trigger input (TIP00 pin input) TP0CCR0 register INTTP0CC0 signal TP0CCR1 register INTTP0CC1 signal TOP01 pin output D1 D0 D1 D1 D0 <1> <2> <1> Count operation start flow START Register initial setting TP0CTL0 register (TP0CKS0 to TP0CKS2 bits) TP0CTL1 register, TP0IOC0 register, TP0IOC2 register, TP0CCR0 register, TP0CCR1 register Initial setting of these registers is performed before setting the TP0CE bit to 1. TP0CE bit = 1 The TP0CKS0 to TP0CKS2 bits can be set at the same time when counting has been started (TP0CE bit = 1). Trigger wait status <2> Count operation stop flow TP0CE bit = 0 Count operation is stopped STOP User's Manual U16889EJ1V0UD 267 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in one-shot pulse output mode (a) Note on rewriting TP0CCRa register To change the set value of the TP0CCRa register to a smaller value, stop counting once, and then change the set value. If the value of the TP0CCRa register is rewritten to a smaller value during counting, the 16-bit counter may overflow. FFFFH D00 16-bit counter 0000H TP0CE bit External trigger input (TIP00 pin input) TP0CCR0 register INTTP0CC0 signal TOP00 pin output (software trigger) TP0CCR1 register INTTP0CC1 signal TOP01 pin output Delay (D10) Delay (D10) Active level width (D00 - D10 + 1) Delay (10000H + D11) Active level width (D01 - D11 + 1) D10 D11 D00 D01 D10 D10 D00 D10 D00 D01 D11 Active level width (D00 - D10 + 1) When the TP0CCR0 register is rewritten from D00 to D01 and the TP0CCR1 register from D10 to D11 where D00 > D01 and D10 > D11, if the TP0CCR1 register is rewritten when the count value of the 16-bit counter is greater than D11 and less than D10 and if the TP0CCR0 register is rewritten when the count value is greater than D01 and less than D00, each set value is reflected as soon as the register has been rewritten and compared with the count value. The counter counts up to FFFFH and then counts up again from 0000H. When the count value matches D11, the counter generates the INTTP0CC1 signal and asserts the TOP01 pin. When the count value matches D01, the counter generates the INTTP0CC0 signal, deasserts the TOP01 pin, and stops counting. Therefore, the counter may output a pulse with a delay period or active period different from that of the one-shot pulse that is originally expected. Remark a = 0, 1 268 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Generation timing of compare match interrupt request signal (INTTP0CC1) The generation timing of the INTTP0CC1 signal in the one-shot pulse output mode is different from other INTTP0CC1 signals; the INTTP0CC1 signal is generated when the count value of the 16-bit counter matches the value of the TP0CCR1 register. Count clock 16-bit counter TP0CCR1 register TOP01 pin output INTTP0CC1 signal D1 - 2 D1 - 1 D1 D1 D1 + 1 D1 + 2 Usually, the INTTP0CC1 signal is generated when the 16-bit counter counts up next time after its count value matches the value of the TP0CCR1 register. In the one-shot pulse output mode, however, it is generated one clock earlier. This is because the timing is changed to match the change timing of the TOP01 pin. User's Manual U16889EJ1V0UD 269 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.5 PWM output mode (TP0MD2 to TP0MD0 bits = 100) In the PWM output mode, a PWM waveform is output from the TOP01 pin when the TP0CTL0.TP0CE bit is set to 1. In addition, a pulse with one cycle of the PWM waveform as half its cycle is output from the TOP00 pin. Figure 7-24. Configuration in PWM Output Mode TP0CCR1 register Transfer CCR1 buffer register Match signal Clear Count clock selection Count start control Output S controller R (RS-FF) TOP01 pin INTTP0CC1 signal 16-bit counter Match signal Output controller TOP00 pin INTTP0CC0 signal TP0CE bit CCR0 buffer register Transfer TP0CCR0 register 270 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-25. Basic Timing in PWM Output Mode FFFFH D01 16-bit counter 0000H TP0CE bit TP0CCR0 register CCR0 buffer register INTTP0CC0 signal TOP00 pin output TP0CCR1 register CCR1 buffer register INTTP0CC1 signal TOP01 pin output D10 D10 D11 D11 D00 D00 D01 D01 D00 D10 D00 D10 D00 D10 D11 D11 D01 Active period (D10) Cycle (D00 + 1) Inactive period (D00 - D10 + 1) When the TP0CE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a PWM waveform from the TOP01 pin. The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows. Active level width = (Set value of TP0CCR1 register ) x Count clock cycle Cycle = (Set value of TP0CCR0 register + 1) x Count clock cycle Duty factor = (Set value of TP0CCR1 register)/(Set value of TP0CCR0 register + 1) The PWM waveform can be changed by rewriting the TP0CCRa register while the counter is operating. The newly written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal INTTP0CC0 is generated when the 16-bit counter counts next time after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare match interrupt request signal INTTP0CC1 is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register. The value set to the TP0CCRa register is transferred to the CCRa buffer register when the count value of the 16-bit counter matches the value of the CCRa buffer register and the 16-bit counter is cleared to 0000H. Remark a = 0, 1 User's Manual U16889EJ1V0UD 271 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-26. Register Setting in PWM Output Mode (1/2) (a) TMP0 control register 0 (TP0CTL0) TP0CE TP0CTL0 0/1 0 0 0 0 TP0CKS2 TP0CKS1 TP0CKS0 0/1 0/1 0/1 Select count clockNote 0: Stop counting 1: Enable counting Note The setting is invalid when the TP0CTL1.TP0EEE bit = 1. (b) TMP0 control register 1 (TP0CTL1) TP0EST TP0EEE TP0CTL1 0 0 0 0 0 TP0MD2 TP0MD1 TP0MD0 1 0 0 1, 0, 0: PWM output mode (c) TMP0 I/O control register 0 (TP0IOC0) TP0OL1 TP0IOC0 0 0 0 0 0/1 TP0OE1 TP0OL0 0/1 0/1 TP0OE0 0/1 0: Disable TOP00 pin output 1: Enable TOP00 pin output Setting of output level while operation of TOP00 pin is disabled 0: Low level 1: High level 0: Disable TOP01 pin output 1: Enable TOP01 pin output Specifies active level of TOP01 pin output 0: Active-high 1: Active-low * When TP0OL1 bit = 0 16-bit counter TOP01 pin output * When TP0OL1 bit = 1 16-bit counter TOP01 pin output 272 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-26. Register Setting in PWM Output Mode (2/2) (d) TMP0 I/O control register 2 (TP0IOC2) TP0EES1 TP0EES0 TP0ETS1 TP0ETS0 TP0IOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input. (e) TMP0 counter read buffer register (TP0CNT) The value of the 16-bit counter can be read by reading the TP0CNT register. (f) TMP0 capture/compare registers 0 and 1 (TP0CCR0 and TP0CCR1) If D0 is set to the TP0CCR0 register and D1 to the TP0CCR1 register, the cycle and active level of the PWM waveform are as follows. Cycle = (D0 + 1) x Count clock cycle Active level width = D1 x Count clock cycle Remark TMP0 I/O control register 1 (TP0IOC1) and TMP0 option register 0 (TP0OPT0) are not used in the PWM output mode. User's Manual U16889EJ1V0UD 273 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in PWM output mode Figure 7-27. Software Processing Flow in PWM Output Mode (1/2) FFFFH D01 16-bit counter D10 0000H TP0CE bit TP0CCR0 register CCR0 buffer register INTTP0CC0 signal TOP00 pin output TP0CCR1 register CCR1 buffer register INTTP0CC1 signal TOP01 pin output D10 D10 D10 D10 D11 D11 D10 D10 D00 D00 D01 D01 D00 D00 D00 D10 D00 D10 D11 D01 D11 D10 D01 D00 <1> <2> <3> <4> <5> 274 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-27. Software Processing Flow in PWM Output Mode (2/2) <1> Count operation start flow <3> TP0CCR0, TP0CCR1 register setting change flow Only writing of the TP0CCR1 register must be performed when the set duty factor is changed. When the counter is cleared after setting, the value of compare register a is transferred to the CCRa buffer register. START Setting of TP0CCR1 register Register initial setting TP0CTL0 register (TP0CKS0 to TP0CKS2 bits) TP0CTL1 register, TP0IOC0 register, TP0IOC2 register, TP0CCR0 register, TP0CCR1 register Initial setting of these registers is performed before setting the TP0CE bit to 1. <4> TP0CCR0, TP0CCR1 register setting change flow The TP0CKS0 to TP0CKS2 bits can be set at the same time when counting is enabled (TP0CE bit = 1). TP0CE bit = 1 Setting of TP0CCR0 register When the counter is cleared after setting, the value of compare register a is transferred to the CCRa buffer register. Setting of TP0CCR1 register <2> TP0CCR0, TP0CCR1 register setting change flow <5> Count operation stop flow Setting of TP0CCR0 register TP0CCR1 write processing is necessary only when the set cycle is changed. When the counter is cleared after setting, the value of the TP0CCRa register is transferred to the CCRa buffer register. TP0CE bit = 0 Counting is stopped. Setting of TP0CCR1 register STOP Remark a = 0, 1 User's Manual U16889EJ1V0UD 275 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TP0CCR1 register last. Rewrite the TP0CCRa register after writing the TP0CCR1 register after the INTTP0CC1 signal is detected. FFFFH D01 16-bit counter 0000H TP0CE bit TP0CCR0 register CCR0 buffer register TP0CCR1 register CCR1 buffer register TOP01 pin output INTTP0CC0 signal D00 D00 D10 D10 D11 D11 D01 D01 D00 D10 D00 D10 D00 D10 D11 D11 D01 To transfer data from the TP0CCRa register to the CCRa buffer register, the TP0CCR1 register must be written. To change both the cycle and active level of the PWM waveform at this time, first set the cycle to the TP0CCR0 register and then set the active level to the TP0CCR1 register. To change only the cycle of the PWM waveform, first set the cycle to the TP0CCR0 register, and then write the same value to the TP0CCR1 register. To change only the active level width (duty factor) of the PWM waveform, only the TP0CCR1 register has to be set. After data is written to the TP0CCR1 register, the value written to the TP0CCRa register is transferred to the CCRa buffer register in synchronization with clearing of the 16-bit counter, and is used as the value compared with the 16-bit counter. To write the TP0CCR0 or TP0CCR1 register again after writing the TP0CCR1 register once, do so after the INTTP0CC0 signal is generated. Otherwise, the value of the CCRa buffer register may become undefined because the timing of transferring data from the TP0CCRa register to the CCRa buffer register conflicts with writing the TP0CCRa register. Remark a = 0, 1 276 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TP0CCR1 register to 0000H. If the set value of the TP0CCR0 register is FFFFH, the INTTP0CC1 signal is generated periodically. Count clock 16-bit counter TP0CE bit TP0CCR0 register TP0CCR1 register INTTP0CC0 signal INTTP0CC1 signal TOP01 pin output D00 0000H D00 0000H D00 0000H FFFF 0000 D00 - 1 D00 0000 0001 D00 - 1 D00 0000 To output a 100% waveform, set a value of (set value of TP0CCR0 register + 1) to the TP0CCR1 register. If the set value of the TP0CCR0 register is FFFFH, 100% output cannot be produced. Count clock 16-bit counter TP0CE bit TP0CCR0 register TP0CCR1 register INTTP0CC0 signal INTTP0CC1 signal TOP01 pin output D00 D00 + 1 D00 D00 + 1 D00 D00 + 1 FFFF 0000 D00 - 1 D00 0000 0001 D00 - 1 D00 0000 User's Manual U16889EJ1V0UD 277 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Generation timing of compare match interrupt request signal (INTTP0CC1) The timing of generation of the INTTP0CC1 signal in the PWM output mode differs from the timing of other INTTP0CC1 signals; the INTTP0CC1 signal is generated when the count value of the 16-bit counter matches the value of the TP0CCR1 register. Count clock 16-bit counter TP0CCR1 register TOP01 pin output INTTP0CC1 signal D1 - 2 D1 - 1 D1 D1 D1 + 1 D1 + 2 Usually, the INTTP0CC1 signal is generated in synchronization with the next counting up after the count value of the 16-bit counter matches the value of the TP0CCR1 register. In the PWM output mode, however, it is generated one clock earlier. This is because the timing is changed to match the change timing of the output signal of the TOP01 pin. 278 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.6 Free-running timer mode (TP0MD2 to TP0MD0 bits = 101) In the free-running timer mode, 16-bit timer/event counter P starts counting when the TP0CTL0.TP0CE bit is set to 1. At this time, the TP0CCRa register can be used as a compare register or a capture register, depending on the setting of the TP0OPT0.TP0CCS0 and TP0OPT0.TP0CCS1 bits. Figure 7-28. Configuration in Free-Running Timer Mode TP0CCR1 register (compare) Output controller TOP01 pin output TP0CCR0 register (compare) Output controller TOP00 pin output TP0CCS0, TP0CCS1 bits (capture/compare selection) Internal count clock TIP00 pin (external event count input/ capture trigger input) Edge detector Count clock selection TP0CE bit Digital noise eliminator Digital noise eliminator Edge detector TP0CCR0 register (capture) Edge detector TP0CCR1 register (capture) 16-bit counter INTTP0OV signal 0 1 0 INTTP0CC1 signal INTTP0CC0 signal 1 TIP01 pin (capture trigger input) Remark a = 0, 1 User's Manual U16889EJ1V0UD 279 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TP0CE bit is set to 1, 16-bit timer/event counter P starts counting, and the output signals of the TOP00 and TOP01 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TP0CCRa register, a compare match interrupt request signal (INTTP0CCa) is generated, and the output signal of the TOP0a pin is inverted. The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it generates an overflow interrupt request signal (INTTP0OV) at the next clock, is cleared to 0000H, and continues counting. At this time, the overflow flag (TP0OPT0.TP0OVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction by software. The TP0CCRa register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected at that time, and compared with the count value. Figure 7-29. Basic Timing in Free-Running Timer Mode (Compare Function) FFFFH D00 16-bit counter D10 0000H TP0CE bit TP0CCR0 register INTTP0CC0 signal TOP00 pin output TP0CCR1 register INTTP0CC1 signal TOP01 pin output INTTP0OV signal TP0OVF bit Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction D10 D11 D00 D01 D10 D11 D00 D01 D11 D01 D11 Remark a = 0, 1 280 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TP0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIP0a pin is detected, the count value of the 16-bit counter is stored in the TP0CCRa register, and a capture interrupt request signal (INTTP0CCa) is generated. The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it generates an overflow interrupt request signal (INTTP0OV) at the next clock, is cleared to 0000H, and continues counting. At this time, the overflow flag (TP0OPT0.TP0OVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction by software. Figure 7-30. Basic Timing in Free-Running Timer Mode (Capture Function) FFFFH D10 D00 16-bit counter 0000H TP0CE bit TIP00 pin input TP0CCR0 register INTTP0CC0 signal TIP01 pin input TP0CCR1 register INTTP0CC1 signal INTTP0OV signal TP0OVF bit Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction D10 D11 D12 D13 D00 D01 D02 D03 D01 D02 D03 D11 D12 D13 User's Manual U16889EJ1V0UD 281 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-31. Register Setting in Free-Running Timer Mode (1/2) (a) TMP0 control register 0 (TP0CTL0) TP0CE TP0CTL0 0/1 0 0 0 0 TP0CKS2 TP0CKS1 TP0CKS0 0/1 0/1 0/1 Select count clockNote 0: Stop counting 1: Enable counting Note The setting is invalid when the TP0CTL1.TP0EEE bit = 1 (b) TMP0 control register 1 (TP0CTL1) TP0EST TP0EEE TP0CTL1 0 0 0/1 0 0 TP0MD2 TP0MD1 TP0MD0 1 0 1 1, 0, 1: Free-running mode 0: Operate with count clock selected by TP0CKS0 to TP0CKS2 bits 1: Count on external event count input signal (c) TMP0 I/O control register 0 (TP0IOC0) TP0OL1 TP0IOC0 0 0 0 0 0/1 TP0OE1 TP0OL0 0/1 0/1 TP0OE0 0/1 0: Disable TOP00 pin output 1: Enable TOP00 pin output Setting of output level with operation of TOP00 pin disabled 0: Low level 1: High level 0: Disable TOP01 pin output 1: Enable TOP01 pin output Setting of output level with operation of TOP01 pin disabled 0: Low level 1: High level 282 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-31. Register Setting in Free-Running Timer Mode (2/2) (d) TMP0 I/O control register 1 (TP0IOC1) TP0IS3 TP0IOC1 0 0 0 0 0/1 TP0IS2 0/1 TP0IS1 0/1 TP0IS0 0/1 Select valid edge of TIP00 pin input Select valid edge of TIP01 pin input (e) TMP0 I/O control register 2 (TP0IOC2) TP0EES1 TP0EES0 TP0ETS1 TP0ETS0 TP0IOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input (f) TMP0 option register 0 (TP0OPT0) TP0CCS1 TP0CCS0 TP0OPT0 0 0 0/1 0/1 0 0 0 TP0OVF 0/1 Overflow flag Specifies if TP0CCR0 register functions as capture or compare register Specifies if TP0CCR1 register functions as capture or compare register (g) TMP0 counter read buffer register (TP0CNT) The value of the 16-bit counter can be read by reading the TP0CNT register. (h) TMP0 capture/compare registers 0 and 1 (TP0CCR0 and TP0CCR1) These registers function as capture registers or compare registers depending on the setting of the TP0OPT0.TP0CCSa bit. When the registers function as capture registers, they store the count value of the 16-bit counter when the valid edge input to the TIP0a pin is detected. When the registers function as compare registers and when Da is set to the TP0CCRa register, the INTTP0CCa signal is generated when the counter reaches (Da + 1), and the output signal of the TOP0a pin is inverted. Remark a = 0, 1 User's Manual U16889EJ1V0UD 283 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 7-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2) FFFFH D00 16-bit counter D10 0000H TP0CE bit TP0CCR0 register INTTP0CC0 signal TOP00 pin output TP0CCR1 register INTTP0CC1 signal TOP01 pin output INTTP0OV signal TP0OVF bit <1> Cleared to 0 by CLR instruction <2> Cleared to 0 by CLR instruction <2> Cleared to 0 by CLR instruction <2> <3> D10 D11 D00 D01 D10 D11 D00 D01 D11 D01 D11 284 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) <1> Count operation start flow START Register initial setting TP0CTL0 register (TP0CKS0 to TP0CKS2 bits) TP0CTL1 register, TP0IOC0 register, TP0IOC2 register, TP0OPT0 register, TP0CCR0 register, TP0CCR1 register Initial setting of these registers is performed before setting the TP0CE bit to 1. TP0CE bit = 1 The TP0CKS0 to TP0CKS2 bits can be set at the same time when counting has been started (TP0CE bit = 1). <2> Overflow flag clear flow Read TP0OPT0 register (check overflow flag). TP0OVF bit = 1 NO YES Execute instruction to clear TP0OVF bit (CLR TP0OVF). <3> Count operation stop flow Counter is initialized and counting is stopped by clearing TP0CE bit to 0. TP0CE bit = 0 STOP User's Manual U16889EJ1V0UD 285 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) When using capture/compare register as capture register Figure 7-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2) FFFFH D10 D00 16-bit counter 0000H TP0CE bit TIP00 pin input TP0CCR0 register INTTP0CC0 signal TIP01 pin input TP0CCR1 register INTTP0CC1 signal INTTP0OV signal TP0OVF bit Cleared to 0 by CLR instruction <2> Cleared to 0 by CLR instruction <2> 0000 D10 D11 D12 0000 0000 D00 D01 D02 D03 0000 D01 D02 D03 D11 D12 <1> <3> 286 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting TP0CTL0 register (TP0CKS0 to TP0CKS2 bits) TP0CTL1 register, TP0IOC1 register, TP0OPT0 register Initial setting of these registers is performed before setting the TP0CE bit to 1. TP0CE bit = 1 The TP0CKS0 to TP0CKS2 bits can be set at the same time when counting has been started (TP0CE bit = 1). <2> Overflow flag clear flow Read TP0OPT0 register (check overflow flag). TP0OVF bit = 1 NO YES Execute instruction to clear TP0OVF bit (CLR TP0OVF). <3> Count operation stop flow Counter is initialized and counting is stopped by clearing TP0CE bit to 0. TP0CE bit = 0 STOP User's Manual U16889EJ1V0UD 287 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in free-running timer mode (a) Interval operation with compare register When 16-bit timer/event counter P is used as an interval timer with the TP0CCRa register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTP0CCa signal has been detected. FFFFH D10 D00 16-bit counter D01 0000H TP0CE bit TP0CCR0 register INTTP0CC0 signal TOP00 pin output D00 D01 D11 D02 D03 D12 D13 D04 D02 D03 D04 D05 Interval period Interval period Interval period Interval period Interval period (D00 + 1) (10000H + (D02 - D01) (10000H + (10000H + D01 - D00) D03 - D02) D04 - D03) TP0CCR1 register INTTP0CC1 signal TOP01 pin output D10 D11 D12 D13 D14 Interval period Interval period Interval period Interval period (D10 + 1) (10000H + (10000H + (10000H + D11 - D10) D12 - D11) D13 - D12) When performing an interval operation in the free-running timer mode, two intervals can be set with one channel. To perform the interval operation, the value of the corresponding TP0CCRa register must be re-set in the interrupt servicing that is executed when the INTTP0CCa signal is detected. The set value for re-setting the TP0CCRa register can be calculated by the following expression, where "Da" is the interval period. Compare register default value: Da - 1 Value set to compare register second and subsequent time: Previous set value + Da (If the calculation result is greater than FFFFH, subtract 10000H from the result and set this value to the register.) Remark a = 0, 1 288 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Pulse width measurement with capture register When pulse width measurement is performed with the TP0CCRa register used as a capture register, software processing is necessary for reading the capture register each time the INTTP0CCa signal has been detected and for calculating an interval. FFFFH D10 D00 16-bit counter D01 0000H TP0CE bit TIP00 pin input TP0CCR0 register INTTP0CC0 signal 0000H D00 D11 D02 D03 D12 D13 D04 D01 D02 D03 D04 Pulse interval Pulse interval Pulse interval Pulse interval Pulse interval (D00) (10000H + (D02 - D01) (10000H + (10000H + D01 - D00) D03 - D02) D04 - D03) TIP01 pin input TP0CCR1 register INTTP0CC1 signal Pulse interval Pulse interval Pulse interval Pulse interval (D10) (10000H + (10000H + (10000H + D11 - D10) D12 - D11) D13 - D12) 0000H D10 D11 D12 D13 INTTP0OV signal TP0OVF bit Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction Cleared to 0 by CLR instruction When executing pulse width measurement in the free-running timer mode, two pulse widths can be measured with one channel. To measure a pulse width, the pulse width can be calculated by reading the value of the TP0CCRa register in synchronization with the INTTP0CCa signal, and calculating the difference between the read value and the previously read value. Remark a = 0, 1 User's Manual U16889EJ1V0UD 289 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Processing of overflow when two capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below. Example of incorrect processing when two capture registers are used FFFFH D11 16-bit counter D00 0000H TP0CE bit TIP00 pin input TP0CCR0 register TIP01 pin input TP0CCR1 register INTTP0OV signal TP0OVF bit D10 D11 D00 D01 D10 D01 <1> <2> <3> <4> The following problem may occur when two pulse widths are measured in the free-running timer mode. <1> Read the TP0CCR0 register (setting of the default value of the TIP00 pin input). <2> Read the TP0CCR1 register (setting of the default value of the TIP01 pin input). <3> Read the TP0CCR0 register. Read the overflow flag. If the overflow flag is 1, clear it to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 - D00). <4> Read the TP0CCR1 register. Read the overflow flag. Because the flag is cleared in <3>, 0 is read. Because the overflow flag is 0, the pulse width can be calculated by (D11 - D10) (incorrect). When two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtain the correct pulse width. Use software when using two capture registers. An example of how to use software is shown below. 290 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH D11 16-bit counter D00 0000H TP0CE bit INTTP0OV signal TP0OVF bit TP0OVF0 flagNote TIP00 pin input TP0CCR0 register TP0OVF1 flagNote TIP01 pin input TP0CCR1 register D10 D11 D00 D01 D10 D01 <1> <2> <3> <4> <5> <6> Note The TP0OVF0 and TP0OVF1 flags are set on the internal RAM by software. <1> Read the TP0CCR0 register (setting of the default value of the TIP00 pin input). <2> Read the TP0CCR1 register (setting of the default value of the TIP01 pin input). <3> An overflow occurs. Set the TP0OVF0 and TP0OVF1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> Read the TP0CCR0 register. Read the TP0OVF0 flag. If the TP0OVF0 flag is 1, clear it to 0. Because the TP0OVF0 flag is 1, the pulse width can be calculated by (10000H + D01 - D00). <5> Read the TP0CCR1 register. Read the TP0OVF1 flag. If the TP0OVF1 flag is 1, clear it to 0 (the TP0OVF0 flag is cleared in <4>, and the TP0OVF1 flag remains 1). Because the TP0OVF1 flag is 1, the pulse width can be calculated by (10000H + D11 - D10) (correct). <6> Same as <3> User's Manual U16889EJ1V0UD 291 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH D11 16-bit counter D00 0000H TP0CE bit INTTP0OV signal TP0OVF bit TP0OVF0 flagNote TIP00 pin input TP0CCR0 register TP0OVF1 flagNote TIP01 pin input TP0CCR1 register D10 D11 D00 D01 D10 D01 <1> <2> <3> <4> <5> <6> Note The TP0OVF0 and TP0OVF1 flags are set on the internal RAM by software. <1> Read the TP0CCR0 register (setting of the default value of the TIP00 pin input). <2> Read the TP0CCR1 register (setting of the default value of the TIP01 pin input). <3> An overflow occurs. Nothing is done by software. <4> Read the TP0CCR0 register. Read the overflow flag. If the overflow flag is 1, set only the TP0OVF1 flag to 1, and clear the overflow flag to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + D01 - D00). <5> Read the TP0CCR1 register. Read the overflow flag. Because the overflow flag is cleared in <4>, 0 is read. Read the TP0OVF1 flag. If the TP0OVF1 flag is 1, clear it to 0. Because the TP0OVF1 flag is 1, the pulse width can be calculated by (10000H + D11 - D10) (correct). <6> Same as <3> 292 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below. Example of incorrect processing when capture trigger interval is long FFFFH 16-bit counter Da1 0000H TP0CE bit TIP0a pin input TP0CCRa register INTTP0OV signal TP0OVF bit 1 cycle of 16-bit counter Pulse width <1> <2> <3> <4> Da0 Da1 Da0 The following problem may occur when long pulse width is measured in the free-running timer mode. <1> Read the TP0CCRa register (setting of the default value of the TIP0a pin input). <2> An overflow occurs. Nothing is done by software. <3> An overflow occurs a second time. Nothing is done by software. <4> Read the TP0CCRa register. Read the overflow flag. If the overflow flag is 1, clear it to 0. Because the overflow flag is 1, the pulse width can be calculated by (10000H + Da1 - Da0) (incorrect). Actually, the pulse width must be (20000H + Da1 - Da0) because an overflow occurs twice. If an overflow occurs twice or more when the capture trigger interval is long, the correct pulse width may not be obtained. If the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. An example of how to use software is shown next. User's Manual U16889EJ1V0UD 293 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Example when capture trigger interval is long FFFFH 16-bit counter Da1 0000H TP0CE bit TIP0a pin input TP0CCRa register INTTP0OV signal TP0OVF bit Overflow counterNote 0H 1H 2H 0H Da0 Da1 Da0 1 cycle of 16-bit counter Pulse width <1> <2> <3> <4> Note The overflow counter is set arbitrarily by software on the internal RAM. <1> Read the TP0CCRa register (setting of the default value of the TIP0a pin input). <2> An overflow occurs. Increment the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <3> An overflow occurs a second time. Increment (+1) the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> Read the TP0CCRa register. Read the overflow counter. When the overflow counter is "N", the pulse width can be calculated by (N x 10000H + Da1 - Da0). In this example, the pulse width is (20000H + Da1 - Da0) because an overflow occurs twice. Clear the overflow counter (0H). 294 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TP0OVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TP0OPT0 register. To accurately detect an overflow, read the TP0OVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) Operation to write 0 (without conflict with setting) (iii) Operation to clear to 0 (without conflict with setting) Overflow set signal 0 write signal Overflow flag (TP0OVF bit) L Overflow set signal 0 write signal Register access signal Overflow flag (TP0OVF bit) L Read Write (ii) Operation to write 0 (conflict with setting) (iv) Operation to clear to 0 (conflict with setting) Overflow set signal 0 write signal Overflow flag (TP0OVF bit) Overflow set signal 0 write signal Register access signal Overflow flag (TP0OVF bit) H Read Write To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set information of overflow may be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is cleared to 0 with the CLR instruction, the overflow flag remains set even after execution of the clear instruction. User's Manual U16889EJ1V0UD 295 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.7 Pulse width measurement mode (TP0MD2 to TP0MD0 bits = 110) In the pulse width measurement mode, 16-bit timer/event counter P starts counting when the TP0CTL0.TP0CE bit is set to 1. Each time the valid edge input to the TIP0a pin has been detected, the count value of the 16-bit counter is stored in the TP0CCRa register, and the 16-bit counter is cleared to 0000H. The interval of the valid edge can be measured by reading the TP0CCRa register after a capture interrupt request signal (INTTP0CCa) occurs. Select either the TIP00 or TIP01 pin as the capture trigger input pin. Specify "No edge detected" by using the TP0IOC1 register for the unused pins. When an external clock is used as the count clock, measure the pulse width of the TIP01 pin because the external clock is fixed to the TIP00 pin. At this time, clear the TP0IOC1.TP0IS1 and TP0IOC1.TP0IS0 bits to 00 (capture trigger input (TIP00 pin): No edge detected). Figure 7-34. Configuration in Pulse Width Measurement Mode Clear Internal count clock TIP00 pin (external event count input/capture trigger input) Edge detector Count clock selection 16-bit counter INTTP0OV signal INTTP0CC0 signal TP0CE bit Digital noise eliminator Digital noise eliminator Edge detector TP0CCR0 register (capture) Edge detector TP0CCR1 register (capture) INTTP0CC1 signal TIP01 pin (capture trigger input) Remark a = 0, 1 296 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-35. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TP0CE bit TIP0a pin input TP0CCRa register INTTP0CCa signal INTTP0OV signal TP0OVF bit Cleared to 0 by CLR instruction 0000H D0 D1 D2 D3 Remark a = 0, 1 When the TP0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIP0a pin is later detected, the count value of the 16-bit counter is stored in the TP0CCRa register, the 16-bit counter is cleared to 0000H, and a capture interrupt request signal (INTTP0CCa) is generated. The pulse width is calculated as follows. First pulse width = (D0 + 1) x Count clock cycle Second and subsequent pulse width = (DN - DN - 1) x Count clock cycle If the valid edge is not input to the TIP0a pin even when the 16-bit counter counted up to FFFFH, an overflow interrupt request signal (INTTP0OV) is generated at the next count clock, and the counter is cleared to 0000H and continues counting. At this time, the overflow flag (TP0OPT0.TP0OVF bit) is also set to 1. Clear the overflow flag to 0 by executing the CLR instruction via software. If the overflow flag is set to 1, the pulse width can be calculated as follows. First pulse width = (D0 + 10001H) x Count clock cycle Second pulse width and on = (10000H + DN - DN - 1) x Count clock cycle Remark a = 0, 1 User's Manual U16889EJ1V0UD 297 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-36. Register Setting in Pulse Width Measurement Mode (1/2) (a) TMP0 control register 0 (TP0CTL0) TP0CE TP0CTL0 0/1 0 0 0 0 TP0CKS2 TP0CKS1 TP0CKS0 0/1 0/1 0/1 Select count clockNote 0: Stop counting 1: Enable counting Note Setting is invalid when the TP0EEE bit = 1. (b) TMP0 control register 1 (TP0CTL1) TP0EST TP0EEE TP0CTL1 0 0 0/1 0 0 TP0MD2 TP0MD1 TP0MD0 1 1 0 1, 1, 0: Pulse width measurement mode 0: Operate with count clock selected by TP0CKS0 to TP0CKS2 bits 1: Count external event count input signal (c) TMP0 I/O control register 1 (TP0IOC1) TP0IS3 TP0IOC1 0 0 0 0 0/1 TP0IS2 0/1 TP0IS1 0/1 TP0IS0 0/1 Select valid edge of TIP00 pin input Select valid edge of TIP01 pin input (d) TMP0 I/O control register 2 (TP0IOC2) TP0EES1 TP0EES0 TP0ETS1 TP0ETS0 TP0IOC2 0 0 0 0 0/1 0/1 0 0 Select valid edge of external event count input 298 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-36. Register Setting in Pulse Width Measurement Mode (2/2) (e) TMP0 option register 0 (TP0OPT0) TP0CCS1 TP0CCS0 TP0OPT0 0 0 0 0 0 0 0 TP0OVF 0/1 Overflow flag (f) TMP0 counter read buffer register (TP0CNT) The value of the 16-bit counter can be read by reading the TP0CNT register. (g) TMP0 capture/compare registers 0 and 1 (TP0CCR0 and TP0CCR1) These registers store the count value of the 16-bit counter when the valid edge input to the TIP0a pin is detected. Remarks 1. TMP0 I/O control register 0 (TP0IOC0) is not used in the pulse width measurement mode. 2. a = 0, 1 User's Manual U16889EJ1V0UD 299 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in pulse width measurement mode Figure 7-37. Software Processing Flow in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TP0CE bit TIP00 pin input TP0CCR0 register INTTP0CC0 signal <1> <2> 0000H D0 D1 D2 0000H <1> Count operation start flow START Register initial setting TP0CTL0 register (TP0CKS0 to TP0CKS2 bits), TP0CTL1 register, TP0IOC1 register, TP0IOC2 register, TP0OPT0 register Initial setting of these registers is performed before setting the TP0CE bit to 1. Set TP0CTL0 register (TP0CE bit = 1) The TP0CKS0 to TP0CKS2 bits can be set at the same time when counting has been started (TP0CE bit = 1). <2> Count operation stop flow The counter is initialized and counting is stopped by clearing the TP0CE bit to 0. TP0CE bit = 0 STOP 300 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TP0OVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TP0OPT0 register. To accurately detect an overflow, read the TP0OVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction. (i) Operation to write 0 (without conflict with setting) (iii) Operation to clear to 0 (without conflict with setting) Overflow set signal 0 write signal Overflow flag (TP0OVF bit) L Overflow set signal 0 write signal Register access signal Overflow flag (TP0OVF bit) L Read Write (ii) Operation to write 0 (conflict with setting) (iv) Operation to clear to 0 (conflict with setting) Overflow set signal 0 write signal Overflow flag (TP0OVF bit) Overflow set signal 0 write signal Register access signal Overflow flag (TP0OVF bit) H Read Write To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set information of overflow may be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no overflow has occurred even when an overflow actually has occurred. If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is cleared to 0 with the CLR instruction, the overflow flag remains set even after execution of the clear instruction. User's Manual U16889EJ1V0UD 301 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.8 Timer output operations The following table shows the operations and output levels of the TOP00 and TOP01 pins. Table 7-4. Timer Output Control in Each Mode Operation Mode Interval timer mode External event count mode External trigger pulse output mode One-shot pulse output mode PWM output mode Free-running timer mode Pulse width measurement mode TOP01 Pin Square wave output Square wave output External trigger pulse output One-shot pulse output PWM output Square wave output (only when compare function is used) - - Square wave output TOP00 Pin Table 7-5. Truth Table of TOP00 and TOP01 Pins Under Control of Timer Output Control Bits TP0IOC0.TP0OLa Bit 0 TP0IOC0.TP0OEa Bit 0 1 TP0CTL0.TP0CE Bit x 0 1 x 0 1 Level of TOP0a Pin Low-level output Low-level output Low level immediately before counting, high level after counting is started 1 0 1 High-level output High-level output High level immediately before counting, low level after counting is started Remark a = 0, 1 302 User's Manual U16889EJ1V0UD CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.6 Eliminating Noise on Capture Trigger Input Pin (TIP0a) The TIP0a pin has a digital noise eliminator. However, this circuit is valid only when the pin is used as a capture trigger input pin; it is invalid when the pin is used as an external event count input pin or external trigger input pin. Digital noise can be eliminated by specifying the alternate function of the TIP0a pin using the PMC3, PFC3, and PFCE3 registers. The number of times of sampling can be selected from three or two by using the PaNFC.PaNFSTS bit. The sampling clock can be selected from fXX, fXX/2, fXX/4, fXX/16, fXX/32, or fXX/64, by using the PaNFC.PaNFC2 to PaNFC.PaNFC0 bits. (1) TIP0a noise elimination control register (PaNFC) This register is used to select the sampling clock and the number of times of sampling for eliminating digital noise. This register can be read or written in 8-bit or 1-bit units. Reset input clears this register to 00H. After reset: 00H R/W Address: P0NFC FFFFFB00H, P1NFC FFFFFB04H PaNFC (a = 0, 1) 0 PaNFSTS 0 0 0 PaNFC2 PaNFC1 PaNFC0 PaNFSTS 0 1 Setting of number of times of sampling for eliminating digital noise Number of times of sampling = 3 Number of times of sampling = 2 PaNFC2 PaNFC1 PaNFC0 0 0 0 0 1 1 0 0 1 1 0 0 Other than above 0 1 0 1 0 1 fXX fXX/2 fXX/4 fXX/16 fXX/32 fXX/64 Sampling clock selection Setting prohibited Cautions 1. Enable starting the 16-bit counter of TMP0 (TP0CTL.TP0CE bit = 1) after the lapse of the sampling clock period x number of times of sampling. 2. Be sure to clear bits 7, 5 to 3 to 0. User's Manual U16889EJ1V0UD 303 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Therefore, a pulse width of MT or longer must be input so that the valid edge of the capture trigger input can be accurately detected. 304 User's Manual U16889EJ1V0UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 In the V850ES/KJ1, six channels of 16-bit timer/event counter 0 are provided. 8.1 Functions 16-bit timer/event counter 0n has the following functions (n = 0 to 5). (1) Interval timer Generates an interrupt at predetermined time intervals. (2) PPG output Can output a rectangular wave with any frequency and any output pulse width. (3) Pulse width measurement Can measure the pulse width of a signal input from an external source. (4) External event counter Can measure the pulse width of a signal input from an external source. (5) Square-wave output Can output a square wave of any frequency. (6) One-shot pulse output (16-bit timer/event counters 00, 01, 04 and 05 only) Can output a one-shot pulse with any output pulse width. User's Manual U16889EJ1V0UD 305 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 8.2 Configuration 16-bit timer/event counter 0n consists of the following hardware. Table 8-1. Configuration of 16-Bit Timer/Event Counter 0n Item Timer/counters Registers Timer inputs Timer outputs Control registers Note Configuration 16-bit timer counter 0n x 1 (TM0n) 16-bit timer capture/compare register: 16 bits x 2 (CR0n0, CR0n1) 2 (TI0n0, TI0n1 pins) 1 (TO0n pin), output controller 16-bit timer mode control register n (TMC0n) Capture/compare control register n (CRC0n) 16-bit timer output control register n (TOC0n) Prescaler mode register 0n (PRM0n) Note To use the TI0n0, TI0n1, and TO0n pin functions, refer to Table 4-19 Settings When Port Pins Are Used for Alternate Functions. Remark n = 0 to 5 306 User's Manual U16889EJ1V0UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 The block diagram is shown below. Figure 8-1. Block Diagram of 16-Bit Timer/Event Counter 0n Internal bus Capture/compare control CRC0n2CRC0n1 CRC0n0 register 0n (CRC0n) Selector INTTM0n0 Noise eliminator Selector Tl0n1 16-bit timer capture/compare register 0n0 (CR0n0) Match Selector Count clockNote 16-bit timer counter 0n (TM0n) Match Clear Output controller TO0n fXX/4 Noise eliminator 2 Noise eliminator Tl0n0 16-bit timer capture/compare register 0n1 (CR0n1) Selector INTTM0n1 CRC0n2 PRM0n1 PRM0n0 Prescaler mode register 0n (PRM0n) Internal bus TMC0n3 TMC0n2 TMC0n1 OVF0n OSPT0m OSPE0m TOC0n4 LVS0n LVR0n TOC0n1 TOE0n Timer output control register 0n (TOC0n) 16-bit timer mode control register 0n (TMC0n) Note Set by the PRM0n register. Remarks 1. n = 0 to 5 m = 0, 1, 4, 5 2. fXX: Main clock frequency User's Manual U16889EJ1V0UD 307 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (1) 16-bit timer counter 0n (TM0n) The TM0n register is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the input clock. After reset: 0000H R Address: TM00 FFFFF600H, TM01 FFFFF610H, TM02 FFFFF620H, TM03 FFFFF630H, TM04 FFFFF640H, TM05 FFFFF650H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TM0n (n = 0 to 5) The count value is reset to 0000H in the following cases. <1> Reset <2> If the TMC0n.TMC0n3 and TMC0n.TMC0n2 bits are cleared (0) <3> If the valid edge of the TI0n0 pin is input in the mode in which clear & start occurs when inputting the valid edge of the TI0n0 pin <4> If the TM0n register and the CR0n0 register match each other in the mode in which clear & start occurs on a match between the TM0n register and the CR0n0 register <5> If the TOC0n.OSPT0m bit is set (1) or if the valid edge of the TI0k0 pin is input in the one-shot pulse output mode Remark n = 0 to 5 m = 0, 1, 4, 5 k = 4, 5 (2) 16-bit timer capture/compare register 0n0 (CR0n0) The CR0n0 register is a 16-bit register that combines capture register and compare register functions. The CRC0n.CRC0n0 bit is used to set whether to use the CR0n0 register as a capture register or as a compare register. The CR0n0 register can be read or written in 16-bit units. After reset, this register is cleared to 0000H. After reset: 0000H R/W Address: CR000 FFFFF602H, CR010 FFFFF612H, CR020 FFFFF622H, CR030 FFFFF632H, CR040 FFFFF642H, CR050 FFFFF652H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CR0n0 (n = 0 to 5) 308 User's Manual U16889EJ1V0UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (a) When using the CR0n0 register as a compare register The value set to the CR0n0 register and the count value set to the TM0n register are always compared and when these values match, an interrupt request signal (INTTM0n0) is generated. The values are retained until rewritten. (b) When using the CR0n0 register as a capture register The TM0n register count value is captured to the CR0n0 register by inputting a capture trigger. The valid edge of the TI0n0 pin or TI0n1 pin can be selected as the capture trigger. The valid edge of the TI0n0 pin is set with the PRM0n.ESn01 and PRM0n.ESn00 bits. The valid edge of the TI0n1 pin is set with the PRM0n.ESn11 and PRM0n.ESn10 bits. Table 8-2 shows the settings when the valid edge of the TI0n0 pin is specified as the capture trigger, and Table 8-3 shows the settings when the valid edge of the TI0n1 is specified as the capture trigger. Table 8-2. Capture Trigger of CR0n0 Register and Valid Edge of TI0n0 Pin Capture Trigger of CR0n0 Valid Edge of TI0n0 Pin ESn01 Falling edge Rising edge No capture operation Rising edge Falling edge Both rising and falling edges 0 0 1 ESn00 1 0 1 Remarks 1. n = 0 to 5 2. Setting the ESn01 and ESn00 bits to 10 is prohibited. Table 8-3. Capture Trigger of CR0n0 Register and Valid Edge of TI0n1 Pin Capture Trigger of CR0n0 Valid Edge of TI0n1 Pin ESn11 Falling edge Rising edge Both rising and falling edges Falling edge Rising edge Both rising and falling edges 0 0 1 ESn10 0 1 1 Remarks 1. n = 0 to 5 2. Setting the ESn11 and ESn10 bits to 10 is prohibited. Cautions 1. Set a value other than 0000H to the CR0n0 register in the mode in which clear & start occurs upon a match of the values of the TM0n register and CR0n0 register. However, if 0000H is set to the CR0n0 register in the free-running timer mode or the TI0n0 pin valid edge clear & start mode, an interrupt request signal (INTTM0n0) is generated when the value changes from 0000H to 0001H after an overflow (FFFFH). 2. When the P33, P35, P613, P92, and P94 pins are used as the valid edges of TI000, TI010, TI020, TI030, and TI051, they cannot be used as timer outputs (TO00 to TO03, TO05). Moreover, when used as TO00 to TO03 and TO05, these pins cannot be used as the valid edge of TI000, TI010, TI020, TI030, and TI051. 3. If, when the CR0n0 register is used as a capture register, the register read interval and capture trigger input conflict, the read data becomes undefined (but the capture data itself is normal). Moreover, when the count stop input and capture trigger input conflict, the capture data becomes undefined. 4. The CR0n0 register cannot be rewritten during timer count operation. User's Manual U16889EJ1V0UD 309 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (3) 16-bit timer capture/compare register 0n1 (CR0n1) The CR0n1 register is a 16-bit register that combines capture register and compare register functions. The CRC0n.CRC0n2 bit is used to set whether to use the CR0n1 register as a capture register or as a compare register. The CR0n1 register can be read or written in 16-bit units. After reset, this register is cleared to 0000H. After reset: 0000H R/W Address: CR001 FFFFF604H, CR011 FFFFF614H, CR021 FFFFF624H, CR031 FFFFF634H, CR041 FFFFF644H, CR051 FFFFF654H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CR0n1 (n = 0 to 5) (a) When using the CR0n1 register as a compare register The value set to the CR0n1 register and the count value of the TM0n register are always compared and when these values match, an interrupt request signal (INTTM0n1) is generated. (b) When using the CR0n1 register as a capture register The TM0n register count value is captured to the CR0n1 register by inputting a capture trigger. The valid edge of the TI0n0 pin can be selected as the capture trigger. The valid edge of the TI0n0 pin is set with the PRM0n.ESn01 and PRM0n.ESn00 bits. Table 8-4 shows the settings when the valid edge of the TI0n0 pin is specified as the capture trigger. Table 8-4. Capture Trigger of CR0n1 Register and Valid Edge of TI0n0 Pin Capture Trigger of CR0n1 Valid Edge of TI0n0 Pin ESn01 Falling edge Rising edge Both rising and falling edges Falling edge Rising edge Both rising and falling edges 0 0 1 ESn00 0 1 1 Remarks 1. n = 0 to 5 2. Setting the ESn01 and ESn00 bits to 10 is prohibited. 310 User's Manual U16889EJ1V0UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Cautions 1. If 0000H is set to the CR0n1 register, an interrupt request signal (INTTM0n1) is generated after overflow of the TM0n register, after clear & start on a match between the TM0n register and CR0n0 register, after clear by the valid edge of the TI0n0 pin, or after clear by a one-shot pulse output trigger. 2. When the P33, P35, P613, P92, and P94 pins are used as the valid edges of TI000, TI010, TI020, TI030, and TI051, they cannot be used as timer outputs (TO00 to TO03, TO05). Moreover, when used as TO00 to TO03 and TO05, these pins cannot be used as the valid edges of TI000, TI010, TI020, TI030, and TI051. 3. If, when the CR0n1 register is used as a capture register, the register read interval and capture trigger input conflict, the read data becomes undefined (but the capture data itself is normal). Moreover, when the count stop input and capture trigger input conflict, the capture data becomes undefined. 4. The CR0n1 register can be rewritten during TM0n register operation only in the PPG output mode. Refer to 8.4.2 PPG output operation. User's Manual U16889EJ1V0UD 311 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 8.3 Registers The registers that control 16-bit timer/event counter 0n are as follows. * 16-bit timer mode control register 0n (TMC0n) * Capture/compare control register 0n (CRC0n) * 16-bit timer output control register 0n (TOC0n) * Prescaler mode register 0n (PRM0n) Remark To use the TI0n0, TI0n1, and TO0n pin functions, refer to Table 4-19 Settings When Port Pins Are Used for Alternate Functions. (1) 16-bit timer mode control register 0n (TMC0n) The TMC0n register is used to set the operation mode of 16-bit timer/event counter 0n, the clear mode of the TM0n register, and the output timing, and to detect overflow. The TMC0n register can be read or written in 8-bit or 1-bit units. After reset, this register is cleared to 00H. Cautions 1. 16-bit timer/event counter 0n starts operating when a value other than 00 (operation stop mode) is set to the TMC0n.TMC0n3 and TMC0n.TMC0n2 bits. To stop the operation, set 00 to the TMC0n3 and TMC0n2 bits. 2. When the main clock is stopped and the CPU operates on the subclock, do not access the TMC0n register using an access method that causes a wait. For details, refer to 3.4.8 (2). Remark n = 0 to 5 312 User's Manual U16889EJ1V0UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 After reset: 00H R/W Address: TMC00 FFFFF606H, TMC01 FFFFF616H, TMC02 FFFFF626H, TMC03 FFFFF636H, TMC04 FFFFF646H, TMC05 FFFFF656H 5 0 4 0 3 2 1 <0> OVF0n 7 TMC0n (n = 0 to 5 m = 4, 5) 0 6 0 TMC0n3 TMC0n2 TMC0n1Note TMC0n3 TMC0n2 TMC0n1Note Selection of operation mode and clear mode Operation stop (TM0n cleared to 0) Free-running timer mode Selection of TO0n output inverse timing Unchanged Generation of interrupt Not generated 0 0 0 0 0 1 0 1 0 Match of TM0n and Generated upon CR0n0 or match of TM0n and CR0n1 match of TM0n and CR0n0 and match 0 1 1 Match of TM0m and of TM0n and CR0n1 CR0m0, match of TM0m and CR0m1, or valid edge of TI0m0 1 0 0 Clear & start with valid edge of TI0n0 Match of TM0m and CR0m0 or match of TM0m and CR0m1 Match of TM0m and CR0m0, match of TM0m and CR0m1, or valid edge of TI0m0 1 0 1 1 1 0 Clear & start upon Match of TM0n and match of TM0n and CR0n0 or match of CR0n0 1 1 1 TM0n and CR0n1 Match of TM0m and CR0m0, match of TM0m and CR0m1, or valid edge of TI0m0 OVF0n 0 1 No overflow Overflow Detection of overflow of 16-bit timer register 0n Note Be sure to clear the TMC001, TMC011, TMC021, and TMC031 bits to 0. Cautions 1. Write to bits other than the OVF0n flag after stopping the timer operation. 2. The valid edge of the TI0n0 pin is set by the PRM0n register. 3. When the mode in which the timer is cleared and started upon match of TM0n and CR0n0 is selected, the setting value of CR0n0 is FFFFH, and when the value of TM0n changes from FFFFH to 0000H, the OVF0n flag is set to 1. Remark TO0n: TI0n0: TM0n: Output pin of 16-bit timer/event counter 0n Input pin of 16-bit timer/event counter 0n 16-bit timer counter 0n CR0n0: 16-bit timer capture/compare register 0n0 CR0n1: 16-bit timer capture/compare register 0n1 User's Manual U16889EJ1V0UD 313 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 The following shows the I/O configuration of each channel and the selection of the TO0n output inversion timing (setting of the TMC0n1 bit). Table 8-5. I/O Configuration of Each Channel Channel TM00 TM01 TM02 TM03 TM04 TO04 - Output Pin - - - - TI001 TI011 TI021 TI031 TI040, TI041 TM05 TI050 TI051/TO05 1/0 Input Pin I/O Pin TI000/TO00 TI010/TO01 TI020/TO02 TI030/TO03 - Setting of TMC0n1 Bit Always clear to 0. Always clear to 0. 0 (read only) 0 (read only) 1/0 314 User's Manual U16889EJ1V0UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (2) Capture/compare control register 0n (CRC0n) The CRC0n register controls the operation of the CR0n0 and CR0n1 registers. The CRC0n register can be read or written in 8-bit or 1-bit units. After reset, CRC0n is cleared to 00H. After reset: 00H R/W Address: CRC00 FFFFF608H, CRC01 FFFFF618H, CRC02 FFFFF628H CRC03 FFFFF638H, CRC04 FFFFF648H, CRC05 FFFFF658H 5 0 4 0 3 0 2 1 0 7 CRC0n (n = 0 to 5) CRC0n2 0 1 0 6 0 CRC0n2 CRC0n1 CRC0n0 Selection of operation mode of CR0n1 register Operation as compare register Operation as capture register CRC0n1 0 1 Selection of capture trigger of CR0n0 register Capture at valid edge of TI0n1 pin Capture at inverse phase of valid edge of TI0n0 pin CRC0n0 0 1 Selection of operation mode of CR0n0 register Operation as compare register Operation as capture register Cautions 1. Before setting the CRC0n register, be sure to stop the timer operation. 2. When the mode in which the timer is cleared and started upon match of the TM0n register and CR0n0 register is selected by the TMC0n register, do not specify the CR0n0 register as the capture register. 3. When both the rising and falling edges are specified for the TI0n0 pin valid edge, capture operation is not performed. 4. To ensure reliable capture operation, a pulse longer than two cycles of the count clock selected by the PRM0n register is required. User's Manual U16889EJ1V0UD 315 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (3) 16-bit timer output control register 0n (TOC0n) The TOC0n register controls the operation of the 16-bit timer/event counter 0n output controller by setting or resetting the timer output F/F, enabling or disabling inverse output, enabling or disabling the timer of 16-bit timer/event counter 0n, enabling or disabling the one-shot pulse output operation, and selecting an output trigger for a one-shot pulse by software (16-bit timer/event counters 02 and 03 do not have a one-shot pulse output function). The TOC0n register can be read or written in 8-bit or 1-bit units. After reset, TOC0n is cleared to 00H. (1/2) After reset: 00H R/W Address: TOC00 FFFFF609H, TOC01 FFFFF619H, TOC02 FFFFF629H TOC03 FFFFF639H, TOC04 FFFFF649H, TOC05 FFFFF659H <5> 4 <3> LVS0n <2> LVR0n 1 TOC0n1 <0> TOE0n 7 TOC0n (n = 0 to 5 m = 0, 1, 4, 5 k = 4, 5) 0 <6> OSPT0mNote 1 OSPE0mNote 1 TOC0n4 OSPT0mNote 1 0 1 Output trigger for one-shot pulse by software - One-shot pulse output OSPE0mNote 1 0 1 Control of one-shot pulse output operation Successive pulse output One-shot pulse outputNote 2 TOC0n4 0 1 Control of timer output F/F upon match of CR0n1 register and TM0n register Inversion operation disabled Inversion operation enabled Notes 1. 16-bit timer/event counters 02 and 03 do not provide a one-shot pulse output function. Be sure to clear the OSPE02, OSPE03, OSPT02, and OSPT03 bits to 0. 16-bit timer/event counters 00 and 01 are the alternate-function pins of the timer I/O pins, so only a software trigger is valid for one-shot pulse output. Clear the TMC00.TMC001 and TMC01.TMC011 bits to 0. 2. The one-shot pulse output operates normally in the free-running timer mode and the mode in which clear & start occurs on the valid edge of the TI0k0 pin. In the mode in which clear & start occurs on match between the TM0m register and the CR0m0 register, one-shot pulse output is not performed because no overflow occurs. 316 User's Manual U16889EJ1V0UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (2/2) LVS0n 0 0 1 1 LVR0n 0 1 0 1 Unchanged Reset timer output F/F (0) Set timer output F/F (1) Setting prohibited Setting of status of timer output F/F TOC0n1 0 1 Control of timer output F/F upon match of CR0n0 register and TM0n register Inversion operation disabled Inversion operation enabled TOE0n 0 1 Control of timer output Output disabled (output is fixed to low level) Output enabled Cautions 1. Be sure to stop the timer operation before setting other than the TOC0n4 bit. 2. The LVS0n and LVR0n bits are 0 when read. 3. The OSPT0m bit is 0 when read because it is automatically cleared after data has been set. 4. Do not set the OSPT0m bit to 1 other than for one-shot pulse output. 5. When performing successive writes to the OSPT0m bit, place an interval between writes of two or more cycles of the count clock selected by the PRM0m register. 6. Do not set the LVS0n bit to 1 before setting the TOE0n bit. Do not set the LVS0n bit and TOE0n bit to 1 at the same time. 7. Do not set <1> and <2> below at the same time. Set as follows. <1> Set the TOC0n1, TOC0n4, TOE0n, and OSPE0m bits: Setting of timer output operation <2> Set the LVS0n and LVR0n bits: Setting of timer output F/F User's Manual U16889EJ1V0UD 317 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (4) Prescaler mode register 0n (PRM0n) The PRM0n register sets the count clock of the TM0n register and the valid edge of the TI0n0 and TI0n1 pin inputs. The PRM0n register can be read or written in 8-bit or 1-bit units. After reset, PRM0n is cleared to 00H. Cautions 1. When setting the count clock to the TI0n0 pin valid edge, do not set the mode in which clear & start occurs on TI0n0 pin valid edge and do not set the CR0n0 and CR0n1 registers as the capture register. 2. Before setting the PRM0n register, be sure to stop the timer operation. 3. If 16-bit timer/event counter 0n operation is enabled by specifying the rising edge of both edges for the valid edge of the TI0n0 pin or TI0n1 pin while the TI0n0 pin or TI0n1 pin is high level immediately after system reset, the rising edge is detected immediately after the rising edge or both edges is specified. Be careful when pulling up the TI0n0 pin or TI0n1 pin. However, the rising edge is not detected when operation is enabled after it has been stopped. 4. When the P33, P35, P613, P92, and P94 pins are used as the valid edges of TI000, TI010, TI020, TI030, and TI051, they cannot be used as timer outputs (TO00 to TO03, TO05). Moreover, when used as TO00 to TO03 and TO05, these pins cannot be used as the valid edges of TI000, TI010, TI020, TI030, and TI051. 318 User's Manual U16889EJ1V0UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (a) Prescaler mode register 00 (PRM00) After reset: 00H 7 R/W 6 Address: FFFFF607H 5 4 3 2 1 0 PRM00 ES011 ES010 ES001 ES000 0 0 PRM001 PRM000 ES011 0 0 1 1 ES010 0 1 0 1 Selection of valid edge of TI001 Falling edge Rising edge Setting prohibited Both rising and falling edges ES001 0 0 1 1 ES000 0 1 0 1 Selection of valid edge of TI000 Falling edge Rising edge Setting prohibited Both rising and falling edges PRM001 PRM000 Selection of count clockNote 1 Count clock 20 MHz fXX 16 MHz 125 ns 250 ns 500 ns - 10 MHz 200 ns 400 ns 800 ns - 0 0 1 1 0 1 0 1 fXX/2 fXX/4 fXX/8 Valid edge of TI000 Note 2 100 ns 200 ns 400 ns - Notes 1. When the internal clock is selected, set so as to satisfy the following conditions. REGC = VDD = 4.0 to 5.5 V: Count clock 10 MHz REGC = Capacity, VDD = 4.0 to 5.5 V: Count clock 5 MHz REGC = VDD = 2.7 to 4.0 V: Count clock 5 MHz 2. The external clock requires a pulse longer than two cycles of the internal clock (fXX/4). Remark fXX: Main clock frequency User's Manual U16889EJ1V0UD 319 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (b) Prescaler mode register 01 (PRM01) After reset: 00H 7 R/W 6 Address: FFFFF617H 5 4 3 2 1 0 PRM01 ES111 ES110 ES101 ES100 0 0 PRM011 PRM010 ES111 0 0 1 1 ES110 0 1 0 1 Selection of valid edge of TI011 Falling edge Rising edge Setting prohibited Both rising and falling edges ES101 0 0 1 1 ES100 0 1 0 1 Selection of valid edge of TI010 Falling edge Rising edge Setting prohibited Both rising and falling edges PRM011 PRM010 Selection of count clockNote 1 Count clock 20 MHz Setting prohibited fXX 16 MHz Setting prohibited 10 MHz 100 ns 400 ns - - 0 0 1 1 0 1 0 1 fXX fXX/4 INTWT Valid edge of TI010 Note 2 200 ns - - 250 ns - - Notes 1. When the internal clock is selected, set so as to satisfy the following conditions. REGC = VDD = 4.0 to 5.5 V: Count clock 10 MHz REGC = Capacity, VDD = 4.0 to 5.5 V: Count clock 5 MHz REGC = VDD = 2.7 to 4.0 V: Count clock 5 MHz 2. The external clock requires a pulse longer than two cycles of the internal clock (fXX/4). Remark fXX: Main clock frequency 320 User's Manual U16889EJ1V0UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (c) Prescaler mode register 02 (PRM02) After reset: 00H 7 R/W 6 Address: FFFFF627H 5 4 3 2 1 0 PRM02 ES211 ES210 ES201 ES200 0 0 PRM021 PRM020 ES211 0 0 1 1 ES210 0 1 0 1 Selection of valid edge of TI021 Falling edge Rising edge Setting prohibited Both rising and falling edges ES201 0 0 1 1 ES200 0 1 0 1 Selection of valid edge of TI020 Falling edge Rising edge Setting prohibited Both rising and falling edges PRM021 PRM020 Selection of count clockNote 1 Count clock 20 MHz fXX 16 MHz 125 ns 250 ns 500 ns - 10 MHz 200 ns 400 ns 800 ns - 0 0 1 1 0 1 0 1 fXX/2 fXX/4 fXX/8 Valid edge of TI020 Note 2 100 ns 200 ns 400 ns - Notes 1. When the internal clock is selected, set so as to satisfy the following conditions. REGC = VDD = 4.0 to 5.5 V: Count clock 10 MHz REGC = Capacity, VDD = 4.0 to 5.5 V: Count clock 5 MHz REGC = VDD = 2.7 to 4.0 V: Count clock 5 MHz 2. The external clock requires a pulse longer than two cycles of the internal clock (fXX/4). Remark fXX: Main clock frequency User's Manual U16889EJ1V0UD 321 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (d) Prescaler mode register 03 (PRM03) After reset: 00H 7 R/W 6 Address: FFFFF637H 5 4 3 2 1 0 PRM03 ES311 ES310 ES301 ES300 0 0 PRM031 PRM030 ES311 0 0 1 1 ES310 0 1 0 1 Selection of valid edge of TI031 Falling edge Rising edge Setting prohibited Both rising and falling edges ES301 0 0 1 1 ES300 0 1 0 1 Selection of valid edge of TI030 Falling edge Rising edge Setting prohibited Both rising and falling edges PRM031 PRM030 Selection of count clockNote 1 Count clock 20 MHz fXX 16 MHz 250 ns 1 s 32 s - 10 MHz 400 ns 1.6 s 51.2 s - 0 0 1 1 0 1 0 1 fXX/4 fXX/16 fXX/512 Valid edge of TI030 Note 2 200 ns 800 ns 25.6 s - Notes 1. When the internal clock is selected, set so as to satisfy the following conditions. REGC = VDD = 4.0 to 5.5 V: Count clock 10 MHz REGC = Capacity, VDD = 4.0 to 5.5 V: Count clock 5 MHz REGC = VDD = 2.7 to 4.0 V: Count clock 5 MHz 2. The external clock requires a pulse longer than two cycles of the internal clock (fXX/4). Remark fXX: Main clock frequency 322 User's Manual U16889EJ1V0UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (e) Prescaler mode register 04 (PRM04) After reset: 00H 7 R/W 6 Address: FFFFF647H 5 4 3 2 1 0 PRM04 ES411 ES410 ES401 ES400 0 0 PRM041 PRM040 ES411 0 0 1 1 ES410 0 1 0 1 Selection of valid edge of TI041 Falling edge Rising edge Setting prohibited Both rising and falling edges ES401 0 0 1 1 ES400 0 1 0 1 Selection of valid edge of TI040 Falling edge Rising edge Setting prohibited Both rising and falling edges PRM041 PRM040 Selection of count clockNote 1 Count clock 20 MHz fXX 16 MHz 125 ns 250 ns 500 ns - 10 MHz 200 ns 400 ns 800 ns - 0 0 1 1 0 1 0 1 fXX/2 fXX/4 fXX/8 Valid edge of TI040 Note 2 100 ns 200 ns 400 ns - Notes 1. When the internal clock is selected, set so as to satisfy the following conditions. REGC = VDD = 4.0 to 5.5 V: Count clock 10 MHz REGC = Capacity, VDD = 4.0 to 5.5 V: Count clock 5 MHz REGC = VDD = 2.7 to 4.0 V: Count clock 5 MHz 2. The external clock requires a pulse longer than two cycles of the internal clock (fXX/4). Remark fXX: Main clock frequency User's Manual U16889EJ1V0UD 323 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (f) Prescaler mode register 05 (PRM05) After reset: 00H 7 R/W 6 Address: FFFFF657H 5 4 3 2 1 0 PRM05 ES511 ES510 ES501 ES500 0 0 PRM051 PRM050 ES511 0 0 1 1 ES510 0 1 0 1 Selection of valid edge of TI051 Falling edge Rising edge Setting prohibited Both rising and falling edges ES501 0 0 1 1 ES500 0 1 0 1 Selection of valid edge of TI050 Falling edge Rising edge Setting prohibited Both rising and falling edges PRM051 PRM050 Selection of count clockNote 1 Count clock 20 MHz Setting prohibited fXX 16 MHz Setting prohibited 10 MHz 100 ns 400 ns 25.6 s - 0 0 1 1 0 1 0 1 fXX fXX/4 fXX/256 Valid edge of TI050 Note 2 200 ns 12.8 s - 250 ns 16 s - Notes 1. When the internal clock is selected, set so as to satisfy the following conditions. REGC = VDD = 4.0 to 5.5 V: Count clock 10 MHz REGC = Capacity, VDD = 4.0 to 5.5 V: Count clock 5 MHz REGC = VDD = 2.7 to 4.0 V: Count clock 5 MHz 2. The external clock requires a pulse longer than two cycles of the internal clock (fXX/4). Remark fXX: Main clock frequency 324 User's Manual U16889EJ1V0UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 8.4 Operation 8.4.1 Operation as interval timer 16-bit timer/event counter 0n can be made to operate as an interval timer by setting the TMC0n register and the CRC0n register as shown in Figure 8-2. Setting procedure The basic operation setting procedure is as follows. <1> Set the count clock using the PRM0n register. <2> Set the CRC0n register (refer to Figure 8-2 for the setting value). <3> Set any value to the CR0n0 register. <4> Set the TMC0n register: Start operation (refer to Figure 8-2 for the setting value). Caution The CR0n0 register cannot be rewritten during 16-bit timer/event counter 0n operation. Remarks 1. For the alternate-function pin settings, refer to Table 4-19 Settings When Port Pins Are Used for Alternate Functions. 2. For INTTM0n0 interrupt enable, refer to CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION. The interval timer repeatedly generates interrupts at the interval of the preset count value in the CR0n0 register. If the count value in the TM0n register matches the value set in the CR0n0 register, an interrupt request signal (INTTM0n0) is generated at the same time that the value of the TM0n register is cleared to 0000H and counting is continued. The count clock of 16-bit timer/event counter 0n can be selected with the PRM0n.PRM0n0 and PRM0n.PRM0n1 bits. Remark n = 0 to 5 User's Manual U16889EJ1V0UD 325 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-2. Control Register Setting Contents During Interval Timer Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 TMC0n 0 0 0 0 1 1 0/1 Note OVF0n 0 Clears & starts upon match between TM0n and CR0n0 (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 CRC0n 0 0 0 0 0 0/1 0/1 0 CR0n0 used as compare register Note Be sure to clear the TMC001, TMC011, TMC021, and TMC031 bits to 0. Remarks 1. 0/1: When these bits are reset to 0 or set to 1, other functions can be used together with the interval timer function. For details, refer to 8.3 (1) 2. n = 0 to 5 16-bit timer mode control register 0n (TMC0n) and 8.3 (2) Capture/compare control register 0n (CRC0n). Figure 8-3. Configuration of Interval Timer 16-bit timer capture/compare register 0n0 (CR0n0) INTTM0n0 Count clockNote Selector TI0n0 Noise eliminator fxx/4 16-bit timer counter 0n (TM0n) OVF0n Clear circuit Note Set with PRM0n register. Remarks 1. fXX: Main clock frequency 2. n = 0 to 5 326 User's Manual U16889EJ1V0UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-4. Timing of Interval Timer Operation t Count clock TM0n count value 0000H 0001H N 0000H 0001H Clear N N 0000H 0001H Clear N N N Timer operation enable CR0n0 INTTM0n0 N Interrupt acknowledgment Interrupt acknowledgment Interval time Interval time Remarks 1. Interval time = (N + 1) x t: N = 0001H to FFFFH 2. n = 0 to 5 User's Manual U16889EJ1V0UD 327 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 8.4.2 PPG output operation 16-bit timer/event counter 0n can be used for PPG (Programmable Pulse Generator) output by setting the TMC0n register and the CRC0n register as shown in Figure 8-5. Setting procedure The basic operation setting procedure is as follows. <1> Set the CRC0n register (refer to Figure 8-5 for the setting value). <2> Set any value to the CR0n0 register. <3> Set any value as a duty to the CR0n1 register. <4> Set the TOC0n register (refer to Figure 8-5 for the setting value). <5> Set the count clock using the PRM0n register. <6> Set the TMC0n register: Start operation (refer to Figure 8-5 for the setting value). Caution To change the duty value (CR0n1 register) during operation, refer to Remark 2 in Figure 8-7 PPG Output Operation Timing. Remarks 1. For the alternate-function pin (TO0n) settings, refer to Table 4-19 Settings When Port Pins Are Used for Alternate Functions. 2. For INTTM0n0 interrupt enable, refer to CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION. The PPG output function outputs a rectangular wave from the TO0n pin with the cycle specified by the count value set in advance to the CR0n0 register and the pulse width specified by the count value set in advance to the CR0n1 register. 328 User's Manual U16889EJ1V0UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-5. Control Register Settings in PPG Output Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 TMC0n 0 0 0 0 1 1 0 OVF0n 0 Clears and starts upon match between TM0n and CR0n0 (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 CRC0n 0 0 0 0 0 0 x 0 x: Don't care CR0n0 used as compare register CR0n1 used as compare register (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 TOC0n 0 0 0 1 LVS0n 0/1 LVR0n 0/1 TOC0n1 1 TOE0n 1 Enables TO0n output Inverts output upon match between TM0n and CR0n0 Specifies initial value of TO0n output F/F Inverts output upon match between TM0n and CR0n1 Disables one-shot pulse output (other than TM02, TM03) (d) Prescaler mode register 0n (PRM0n) ESn11 PRM0n 0/1 ESn10 0/1 ESn01 0/1 ESn00 0/1 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock Setting invalid (Setting to 10 is prohibited.) Setting invalid (Setting to 10 is prohibited.) Cautions 1. Make sure that 0000H CR0n1 < CR0n0 FFFFH is set to the CR0n0 register and CR0n1 register. 2. The cycle of the pulse generated by PPG output is (CR0n0 setting value + 1). The duty factor is (CR0n1 setting value + 1) / (CR0n0 setting value + 1) Remark n = 0 to 5 User's Manual U16889EJ1V0UD 329 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-6. Configuration of PPG Output 16-bit capture/compare register 0n0 (CR0n0) Selector Count clockNote TI0k0 Noise eliminator fXX/4 16-bit timer counter 0n (TM0n) Clear circuit Output controller TO0n 16-bit capture/compare register 0n1 (CR0n1) Note The count clock is set by the PRM0n register. Remark n = 0 to 5 k = 4, 5 330 User's Manual U16889EJ1V0UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-7. PPG Output Operation Timing t Count clock TM0n count value N 0000H 0001H Clear Value loaded to CR0n0 Value loaded to CR0n1 TO0n Pulse width: (M + 1) x t 1 cycle: (N + 1) x t N M M-1 M N-1 N 0000H 0001H Clear Caution The CR0n0 register cannot be rewritten during 16-bit timer/event counter 0n operation. Remarks 1. 0000H M < N FFFFH 2. Change the pulse width during 16-bit timer/event counter 0n operation (rewrite CR0n1 register) as follows in a PPG output operation. <1> Disable the timer output inversion operation based on a match of the TM0n and CR0n1 registers (TOC0n4 bit = 0). <2> Disable the INTTM0n1 interrupt (TM0MKn1 bit =1). <3> Rewrite the CR0n1 register. <4> Wait for a cycle of the TM0n register count clock. <5> Enable the timer output inversion operation based on a match of the TM0n and CR0n1 registers (TOC0n4 bit = 1). <6> Clear the interrupt request flag of INTTM0n1 (TM0IFn1 bit = 0). <7> Enable the INTTM0n1 interrupt (TM0MKn1 bit = 0). 3. n = 0 to 5 User's Manual U16889EJ1V0UD 331 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 8.4.3 Pulse width measurement The TM0n register can be used to measure the pulse widths of the signals input to the TI0n0 and TI0n1 pins. Measurement can be carried out with 16-bit timer/event counter 0n used in the free-running timer mode or by restarting the timer in synchronization with the edge of the signal input to the TI0n0 pin. When an interrupt is generated, read the valid capture register value. After confirming the TMC0n.OVF0n flag, clear (0) it by software and measure the pulse width. Setting procedure The basic operation setting procedure is as follows. <1> Set the CRC0n register (refer to Figures 8-9, 8-12, 8-14, and 8-16 for the setting value). <2> Set the count clock using the PRM0n register. <3> Set the TMC0n register: Start operation (refer to Figures 8-9, 8-12, 8-14, and 8-16 for the setting value). Caution When using two capture registers, set the TI0n0 and TI0n1 pins. Remarks 1. For the alternate-function pin (TI0n0, TI0n1) settings, refer to Table 4-19 Settings When Port Pins Are Used for Alternate Functions. 2. For INTTM0n0 and INTTM0n1 interrupt enable, refer to CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION. Figure 8-8. CR0n1 Capture Operation with Rising Edge Specified Count clock TM0n TI0n0 Rising edge detection CR0n1 INTTM0n1 N N-3 N-2 N-1 N N+1 Remarks 1. n = 0 to 5 2. The valid edge is detected through sampling at a count clock cycle selected with the PRM0n register, and the capture operation is not performed until the valid edge is detected twice. As a result, noise with a short pulse width can be eliminated. 332 User's Manual U16889EJ1V0UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (1) Pulse width measurement with free-running timer operation and one capture register If the edge specified by the PRM0n register is input to the TI0n0 pin when 16-bit timer/event counter 0n is operated in the free-running timer mode (refer to Figure 8-9), the value of the TM0n register is loaded to the CR0n1 register and an external interrupt request signal (INTTM0n1) is generated. The valid edge is specified by the PRM0n.ESn00 and PRM0n.ESn01 bits. The rising edge, falling edge, or both the rising and falling edges can be selected. The valid edge is detected through sampling at a count clock cycle selected with the PRM0n register, and the capture operation is not performed until the valid edge is detected twice. As a result, noise with a short pulse width can be eliminated. Remark n = 0 to 5 User's Manual U16889EJ1V0UD 333 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-9. Control Register Settings for Pulse Width Measurement with Free-Running Timer Operation and One Capture Register (When TI0n0 Pin and CR0n1 Registers Are Used) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n 0 0 0 0 0 TMC0n2 TMC0n1 1 0/1 Note OVF0n 0 Free-running timer mode (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n 0 0 0 0 0 1 0/1 CRC0n0 0 CR0n0 used as compare register CR0n1 used as capture register (c) Prescaler mode register 0n (PRM0n) ESn11 PRM0n 0/1 ESn10 0/1 ESn01 1 ESn00 1 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (Setting to 11 is prohibited.) Specifies both edges for pulse detection Setting invalid (Setting to 10 is prohibited.) Note Be sure to clear the TMC001, TMC011, TMC021, and TMC031 bits to 0. Remarks 1. 0/1: When these bits are reset to 0 or set to 1, other functions can be used together with the pulse width measurement function. For details, refer to 8.3 (1) 2. n = 0 to 5 16-bit timer mode control register 0n (TMC0n) and 8.3 (2) Capture/compare control register 0n (CRC0n). 334 User's Manual U16889EJ1V0UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-10. Configuration for Pulse Width Measurement with Free-Running Timer Operation Selector Count clockNote 16-bit timer counter 0n (TM0n) OVF0n TI0n0 16-bit timer capture/compare register 0n1 (CR0n1) INTTM0n1 Internal bus Note The count clock is set with the PRM0n register. Remark n = 0 to 5 Figure 8-11. Timing of Pulse Width Measurement with Free-Running Timer Operation and One Capture Register (with Both Edges Specified) t Count clock TM0n count value TI0n0 pin input D0 D1 D2 D3 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D3 Value loaded to CR0n1 INTTM0n1 OVF0n Cleared by instruction (D1 - D0) x t (10000H - D1 + D2) x t (D3 - D2) x t Remark n = 0 to 5 User's Manual U16889EJ1V0UD 335 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (2) Measurement of two pulse widths with free-running timer operation The pulse widths of two signals respectively input to the TI0n0 pin and the TI0n1 pin can be simultaneously measured when 16-bit timer/event counter 0n is used in the free-running timer mode (refer to Figure 8-12). When the edge specified by the PRM0n.ESn00 and PRM0n.ESn01 bits is input to the TI0n0 pin, the value of the TM0n register is loaded to the CR0n1 register and an external interrupt request signal (INTTM0n1) is generated. When the edge specified by the PRM0n.ESn10 and PRM0n.ESn11 bits is input to the TI0n1 pin, the value of the TM0n register is loaded to the CR0n0 register and an external interrupt request signal (INTTM0n0) is generated. The edges of the TI0n0 and TI0n1 pins are specified by the PRM0n.ESn00 and PRM0n.ESn01 bits and the PRM0n.ESn10 and PRM0n.ESn11 bits, respectively. Specify both rising and falling edges. The valid edge of the TI0n0 pin is detected through sampling at the count clock cycle selected with the PRM0n register, and the capture operation is not performed until the valid level is detected twice. As a result, noise with a short pulse width can be eliminated. Remark n = 0 to 5 336 User's Manual U16889EJ1V0UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-12. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Timer Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 TMC0n 0 0 0 0 0 1 0/1Note OVF0n 0 Free-running timer mode (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 CRC0n 0 0 0 0 0 1 0 1 CR0n0 used as capture register Captures to CR0n0 at valid edge of TI0n1 pin CR0n1 used as capture register (c) Prescaler mode register 0n (PRM0n) ESn11 PRM0n 1 ESn10 1 ESn01 1 ESn00 1 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (Setting to 11 is prohibited.) Specifies both edges for pulse detection. Specifies both edges for pulse detection. Note Be sure to clear the TMC001, TMC011, TMC021, and TMC031 bits to 0. Remarks 1. 0/1: When these bits are reset to 0 or set to 1, other functions can be used together with the pulse width measurement function. For details, refer to 8.3 (1) 16-bit timer mode control register 0n (TMC0n). 2. n = 0 to 5 User's Manual U16889EJ1V0UD 337 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 * Capture operation (free-running timer mode) The following figure illustrates the operation of the capture register when the capture trigger is input. Figure 8-13. Timing of Pulse Width Measurement with Free-Running Timer Operation (with Both Edges Specified) t Count clock TM0n count value TI0n0 pin input Value loaded to CR0n1 INTTM0n1 TI0n1 pin input Value loaded to CR0n0 INTTM0n0 OVF0n Cleared by instruction (D1 - D0) x t (10000H - D1 + D2) x t (10000H - D1 + (D2 + 1)) x t (D3 - D2) x t D1 D2 + 1 D0 D1 D2 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D2 + 1 D2 + 2 D3 Remark n = 0 to 5 (3) Pulse width measurement with free-running timer operation and two capture registers When 16-bit timer/event counter 0n is used in the free-running timer mode (refer to Figure 8-14), the pulse width of the signal input to the TI0n0 pin can be measured. When the edge specified by the PRM0n.ESn00 and PRM0n.ESn01 bits is input to the TI0n0 pin, the value of the TM0n register is loaded to the CR0n1 register and an external interrupt request signal (INTTM0n1) is generated. The value of the TM0n register is also loaded to the CR0n0 register when an edge inverse to the one that triggers capturing to the CR0n1 register is input. The valid edge of the TI0n0 pin is detected through sampling at a count clock cycle selected with the PRM0n register, and the capture operation is not performed until the valid edge is detected twice. As a result, noise with a short pulse width can be eliminated. 338 User's Manual U16889EJ1V0UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-14. Control Register Settings for Pulse Width Measurement with Free-Running Timer Operation and Two Capture Registers (with Rising Edge Specified) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 TMC0n 0 0 0 0 0 1 0/1 Note OVF0n 0 Free-running timer mode (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 CRC0n 0 0 0 0 0 1 1 1 CR0n0 used as capture register Captures to CR0n0 at edge inverse to valid edge of TI0n0 pin CR0n1 used as capture register (c) Prescaler mode register 0n (PRM0n) ESn11 PRM0n 0/1 ESn10 0/1 ESn01 0 ESn00 1 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (Setting to 11 is prohibited.) Specifies rising edge of pulse width detection Setting invalid (Setting to 10 is prohibited.) Note Be sure to clear the TMC001, TMC011, TMC021, and TMC031 bits to 0. Remarks 1. 0/1: When these bits are reset to 0 or set to 1, other functions can be used together with the pulse width measurement function. For details, refer to 8.3 (1) 16-bit timer mode control register 0n (TMC0n). 2. n = 0 to 5 User's Manual U16889EJ1V0UD 339 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-15. Timing of Pulse Width Measurement with Free-Running Timer Operation and Two Capture Registers (with Rising Edge Specified) t Count clock TM0n count value TI0n0 pin input Value loaded to CR0n1 Value loaded to CR0n0 INTTM0n1 OVF0n Cleared by instruction (D1 - D0) x t (10000H - D1 + D2) x t (D3 - D2) x t D0 D1 D2 D3 0000H 0001H D0 D0 + 1 D1 D1 + 1 FFFFH 0000H D2 D2 + 1 D3 Remark n = 0 to 5 (4) Pulse width measurement by restarting When the valid edge of the TI0n0 pin is detected, the pulse width of the signal input to the TI0n0 pin can be measured by clearing the TM0n register and then resuming counting after loading the count value of the TM0n register to the CR0n1 register (refer to Figure 8-17). The edge is specified by the PRM0n.ESn00 and PRM0n.ESn01 bits. specified. The valid edge is detected through sampling at a count clock cycle selected with the PRM0n register and the capture operation is not performed until the valid level is detected twice. As a result, noise with a short pulse can be eliminated. The rising or falling edge can be 340 User's Manual U16889EJ1V0UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-16. Control Register Settings for Pulse Width Measurement by Restarting (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 TMC0n 0 0 0 0 1 0 0/1 Note OVF0n 0 Clears and starts at valid edge of TI0n0 pin (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 CRC0n 0 0 0 0 0 1 1 1 CR0n0 used as capture register Captures to CR0n0 at edge inverse to valid edge of TI0n0 pin CR0n1 used as capture register (c) Prescaler mode register 0n (PRM0n) ESn11 PRM0n 0/1 ESn10 0/1 ESn01 0 ESn00 1 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock (Setting to 11 is prohibited.) Specifies rising edge of pulse width detection Setting invalid (Setting to 10 is prohibited.) Note Be sure to clear the TMC001, TMC011, TMC021, and TMC031 bits to 0. Remarks 1. 0/1: When these bits are reset to 0 or set to 1, other functions can be used together with the pulse width measurement function. For details, refer to 8.3 (1) 16-bit timer mode control register 0n (TMC0n). 2. n = 0 to 5 User's Manual U16889EJ1V0UD 341 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-17. Timing of Pulse Width Measurement by Restarting (with Rising Edge Specified) t Count clock TM0n count clock TI0n0 pin input Value loaded to CR0n1 Value loaded to CR0n0 INTTM0n1 (D1 + 1) x t (D2 + 1) x t D0 D1 D2 0000H 0001H D0 0000H 0001H D1 D2 0000H 0001H Remark n = 0 to 5 342 User's Manual U16889EJ1V0UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 8.4.4 Operation as external event counter Setting procedure The basic operation setting procedure is as follows. <1> Set the CRC0n register (refer to Figure 8-18 for the setting value). <2> Set the count clock using the PRM0n register. <3> Set any value (except for 0000H) to the CR0n0 register. <4> Set the TMC0n register: Start operation (refer to Figure 8-18 for the setting value). Remarks 1. For the alternate-function pin (TI0n0) settings, refer to Table 4-19 Settings When Port Pins Are Used for Alternate Functions. 2. For INTTM0n0 interrupt enable, refer to CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION. The external event counter counts the number of clock pulses input to the TI0n0 pin from an external source by using the TM0n register. Each time the valid edge specified by the PRM0n register has been input, the TM0n register is incremented. When the count value of the TM0n register matches the value of the CR0n0 register, the TM0n register is cleared to 0000H and an interrupt request signal (INTTM0n0) is generated. Set the CR0n0 register to a value other than 0000H (one-pulse count operation is not possible). The edge is specified by the PRM0n.ESn00 and PRM0n.ESn01 bits. The rising, falling, or both the rising and falling edges can be specified. The valid edge is detected through sampling at a count clock cycle of fXX/4, and the capture operation is not performed until the valid level is detected twice. As a result, noise with a short pulse width can be eliminated. Cautions 1. When using 16-bit timer/event counters 00 to 03 as external event counters, the timer outputs (TO00 to TO03) cannot be used. 2. The value of the CR0n0 and CR0n1 registers cannot be changed during timer count operation. Remark n = 0 to 5 User's Manual U16889EJ1V0UD 343 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-18. Control Register Settings in External Event Count Mode (with Rising Edge Specified) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n 0 0 0 0 1 TMC0n2 TMC0n1 1 0/1 Note OVF0n 0 Clears and starts on match between TM0n and CR0n0 (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 CRC0n 0 0 0 0 0 0/1 0/1 0 CR0n0 used as compare register (C) Prescaler mode register 0n (PRM0n) ESn11 PRM0n 0/1 ESn10 0/1 ESn01 0 ESn00 1 3 0 2 0 PRM0n1 PRM0n0 1 1 Selects external clock Specifies rising edge of external event count input Setting invalid (Setting to 10 is prohibited.) Note Be sure to clear the TMC001, TMC011, TMC021, and TMC031 bits to 0. Remarks 1. 0/1: When these bits are reset to 0 or set to 1, other functions can be used together with the external event counter function. For details, refer to 8.3 (1) 16-bit timer mode control register 0n (TMC0n) and 8.3 (2) Capture/compare control register 0n (CRC0n). 2. n = 0 to 5 344 User's Manual U16889EJ1V0UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-19. Configuration of External Event Counter 16-bit timer capture/compare register 0n0 (CR0n0) Match Clear Count clock Note INTTM0n0 Selector 16-bit timer counter 0n (TM0n) OVF0n fxx/4 TI0n0 valid edge Noise eliminator 16-bit timer capture/compare register 0n1 (CR0n1) Internal bus Note Set with the PRM0n register. Remark n = 0 to 5 Figure 8-20. Timing of External Event Counter Operation (with Rising Edge Specified) TI0n0 pin input TM0n count value CR0n0 INTTM0n0 Count start 0000H 0001H 0002H 0003H 0004H 0005H N N-1 N 0000H 0001H 0002H 0003H Cautions 1. Read the TM0n register when reading the count value of the external event counter. 2. Counting is not possible at the first valid edge after the external event count mode is entered. Remark n = 0 to 5 User's Manual U16889EJ1V0UD 345 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 8.4.5 Square-wave output operation Setting procedure The basic operation setting procedure is as follows. <1> Set the count clock using the PRM0n register. <2> Set the CRC0n register (refer to Figure 8-21 for the setting value). <3> Set the TOC0n register (refer to Figure 8-21 for the setting value). <4> Set any value (except for 0000H) to the CR0n0 register. <5> Set the TMC0n register: Start operation (refer to Figure 8-21 for the setting value). Remarks 1. For the alternate-function pin (TO0n) settings, refer to Table 4-19 Settings When Port Pins Are Used for Alternate Functions. 2. For INTTM0n0 interrupt enable, refer to CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION. 16-bit timer/event counter 0n can be used to output a square wave with any frequency at an interval specified by the count value set in advance to the CR0n0 register. By setting the TOC0n.TOE0n and TOC0n.TOC0n1 bits to 11, the output status of the TO0n pin is inverted at an interval set in advance to the CR0n0 register. In this way, a square wave of any frequency can be output. Caution The value of the CR0n0 and CR0n1 registers cannot be changed during timer count operation. 346 User's Manual U16889EJ1V0UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-21. Control Register Settings in Square-Wave Output Mode (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 TMC0n 0 0 0 0 1 1 0 OVF0n 0 Clears and starts upon match between TM0n and CR0n0 (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n 0 0 0 0 0 0/1 0/1 CRC0n0 0 CR0n0 used as compare register (c) 16-bit timer output control register 0n (TOC0n) OSPT0n OSPE0n TOC0n4 TOC0n 0 0 0 0 LVS0n 0/1 LVR0n 0/1 TOC0n1 1 TOE0n 1 Enables TO0n output Inverts output upon match between TM0n and CR0n0 Specifies initial value of TO0n output F/F Does not invert output upon match between TM0n and CR0n1 Disables one-shot pulse output (other than TM02 and TM03) (d) Prescaler mode register 0n (PRM0n) ESn11 PRM0n 0/1 ESn10 0/1 ESn01 0/1 ESn00 0/1 3 0 2 0 PRM0n1 PRM0n0 0/1 0/1 Selects count clock Setting invalid (Setting to 10 is prohibited.) Setting invalid (Setting to 10 is prohibited.) Remarks 1. For details, refer to 8.3 (2) Capture/compare control register 0n (CRC0n) and 8.3 (3) 16-bit timer output control register 0n (TOC0n). 2. n = 0 to 5 User's Manual U16889EJ1V0UD 347 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-22. Timing of Square-Wave Output Operation Count clock TM0n count value CR0n0 INTTM0n0 TO0n pin output 0000H 0001H 0002H N N-1 N 0000H 0001H 0002H N-1 N 0000H Remark n = 0 to 5 348 User's Manual U16889EJ1V0UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 8.4.6 One-shot pulse output operation The one-shot pulse output is valid only for 16-bit timer/event counters 00, 01, 04, and 05. 16-bit timer/event counter 0n can output a one-shot pulse in synchronization with a software trigger or an external trigger (TI0k0 pin input). Setting procedure The basic operation setting procedure is as follows. <1> Set the count clock using the PRM0m register. <2> Set the CRC0m register (refer to Figures 8-23 and 8-25 for the setting value). <3> Set the TOC0m register (refer to Figures 8-23 and 8-25 for the setting value). <4> Set any value to the CR0m0 and CR0m1 registers. <5> Set the TMC0m register: Start operation (refer to Figures 8-23 and 8-25 for the setting value). Remarks 1. For the alternate-function pin (TO0m) settings, refer to Table 4-19 Settings When Port Pins Are Used for Alternate Functions. 2. For INTTM0m0 interrupt enable, refer to CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION. (1) One-shot pulse output with software trigger (16-bit timer/event counters 00, 01, 04, and 05 only) A one-shot pulse can be output from the TO0m pin by setting the TMC0m, CRC0m, and TOC0m registers as shown in Figure 8-23, and by setting the TOC0m.OSPT0m bit to 1 by software. By setting the OSPT0m bit to 1, 16-bit timer/event counter 0m is cleared and started, and its output becomes active at the count value (N) set in advance to the CR0m1 register. After that, the output becomes inactive at the count value (M) set in advance to the CR0m0 registerNote. Even after the one-shot pulse has been output, 16-bit timer/event counter 0m continues its operation. To stop 16-bit timer/event counter 0m, the TMC0m.TMC0m3 and TMC0m.TMC0m2 bits must be cleared to 00. Note The case where N < M is described here. When N > M, the output becomes active with the CR0m0 register and inactive with the CR0m1 register. Cautions 1. Do not set the OSPT0m bit while the one-shot pulse is being output. To output the oneshot pulse again, wait until the current one-shot pulse output is completed. 2. The value of the CR0m0 and CR0m1 registers cannot be changed during timer count operation. Remark m = 0, 1, 4, 5 k = 4, 5 User's Manual U16889EJ1V0UD 349 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-23. Control Register Settings for One-Shot Pulse Output with Software Trigger (1/2) (a) 16-bit timer mode control register 0m (TMC0m) TMC0m3 TMC0m2 TMC0m1 TMC0m 0 0 0 0 0 1 0 OVF0m 0 Free-running timer mode (b) Capture/compare control register 0m (CRC0m) CRC0m2 CRC0m1 CRC0m0 CRC0m 0 0 0 0 0 0 0/1 0 CR0m0 used as compare register CR0m1 used as compare register (c) 16-bit timer output control register 0m (TOC0m) OSPT0m OSPE0m TOC0m4 TOC0m 0 0 1 1 LVS0m 0/1 LVR0m 0/1 TOC0m1 1 TOE0m 1 Enables TO0m output Inverts output upon match between TM0m and CR0m0 Specifies initial value of TO0m output F/F Inverts output upon match between TM0m and CR0m1 Sets one-shot pulse output mode Set to 1 for output 350 User's Manual U16889EJ1V0UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-23. Control Register Settings for One-Shot Pulse Output with Software Trigger (2/2) (d) Prescaler mode register 0m (PRM0m) ESm11 PRM0m 0/1 ESm10 0/1 ESm01 0/1 ESm00 0/1 3 0 2 0 PRM0m1 PRM0m0 0/1 0/1 Selects count clock Setting invalid (Setting to 10 is prohibited.) Setting invalid (Setting to 10 is prohibited.) Caution Do not set 0000H to the CR0m0 and CR0m1 registers. Remarks 1. For details, refer to 8.3 (2) Capture/compare control register 0n (CRC0n) and 8.3 (3) 16-bit timer output control register 0n (TOC0n). 2. m = 0, 1, 4, 5 Figure 8-24. Timing of One-Shot Pulse Output Operation with Software Trigger Set TMC0m register to 04H Count clock TM0m count 0000H 0001H CR0m1 set value CR0m0 set value OSPT0m INTTM0m1 INTTM0m0 TO0m pin output N M N N+1 N M 0000H N-1 N N M M-1 M M+1 M+2 N M Caution 16-bit timer counter 0m starts operating as soon as a value other than 00 (operation stop mode) is set to the TMC0m3 and TMC0m2 bits. Remark m = 0, 1, 4, 5 N 351 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (2) One-shot pulse output with external trigger (16-bit timer/event counters 04 and 05 only) A one-shot pulse can be output from the TO0k pin by setting the TMC0k, CRC0k, and TOC0k registers as shown in Figure 8-25, and by using the valid edge of the TI0k0 pin as an external trigger. The valid edge of the TI0k0 pin is specified by the PRM0k.ESk00 and PRM0k.ESk01 bits. The rising, falling, or both the rising and falling edges can be specified. When the valid edge of the TI0k0 pin is detected, 16-bit timer/event counter 0k is cleared and started, and the output becomes active at the count value set in advance to the CR0k1 register. After that, the output becomes inactive at the count value set in advance to the CR0k0 registerNote. Note The case where N < M is described here. When N > M, the output becomes active with the CR0k0 register and inactive with the CR0k1 register. Cautions 1. Even if the external trigger is generated again while the one-shot pulse is output, it is ignored. 2. The value of the CR0k0 and CR0k1 registers cannot be changed during timer count operation. Remark k = 4, 5 352 User's Manual U16889EJ1V0UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-25. Control Register Settings for One-Shot Pulse Output with External Trigger (with Rising Edge Specified) (1/2) (a) 16-bit timer mode control register 0k (TMC0k) TMC0k3 TMC0k 0 0 0 0 1 TMC0k2 TMC0k1 0 0 OVF0k 0 Clears and starts at valid edge of TI0k0 pin (b) Capture/compare control register 0k (CRC0k) CRC0k2 CRC0k1 CRC0k 0 0 0 0 0 0 0/1 CRC0k0 0 CR0k0 used as compare register CR0k1 used as compare register (c) 16-bit timer output control register 0k (TOC0k) OSPT0k OSPE0k TOC0k4 TOC0k 0 0 1 1 LVS0k 0/1 LVR0k 0/1 TOC0k1 1 TOE0k 1 Enables TO0k output Inverts output upon match between TM0k and CR0k0 Specifies initial value of TO0k output F/F Inverts output upon match between TM0k and CR0k1 Sets one-shot pulse output mode User's Manual U16889EJ1V0UD 353 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-25. Control Register Settings for One-Shot Pulse Output with External Trigger (with Rising Edge Specified) (2/2) (d) Prescaler mode register 0k (PRM0k) ESk11 PRM0k 0/1 ESk10 0/1 ESk01 0 ESk00 1 3 0 2 0 PRM0k1 PRM0k0 0/1 0/1 Selects count clock (Setting to 11 is prohibited.) Specifies rising edge of pulse width detection. Setting invalid (Setting to 10 is prohibited.) Caution Do not set the CR0k0 and CR0k1 registers to 0000H. Remarks 1. For details, refer to 8.3 (2) Capture/compare control register 0n (CRC0n) and 8.3 (3) 16-bit timer output control register 0n (TOC0n). 2. k = 4, 5 Figure 8-26. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) Set TMC0k to 08H Count clock TM0k count value 0000H 0001H CR0k1 set value CR0k0 set value TI0k0 pin input INTTM0k1 INTTM0k0 TO0k pin output N M 0000H N M N N+1 N+2 N M M-2 M-1 M N M M+1 M+2 Caution 16-bit timer/event counter 0k starts operating as soon as a value other than 00 (operation stop mode) is set to the TMC0k2 and TMC0k3 bits. Remark k = 4, 5 N User's Manual U16889EJ1V0UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 8.4.7 Cautions (1) Error on starting timer An error of up to 1 clock occurs before the match signal is generated after the timer has been started. This is because the count of the TM0n register is started asynchronously to the count pulse. Figure 8-27. Count Start Timing of TM0n Register Count pulse TM0n count value 0000H Timer start 0001H 0002H 0003H 0004H Remark n = 0 to 5 (2) Setting CR0n0 and CR0n1 registers (in the mode in which clear & start occurs upon match between TM0n register and CR0n0 register) Set the CR0n0 and CR0n1 registers to a value other than 0000H (when using these registers as external event counters, one-pulse count operation is not possible). Remark n = 0 to 5 (3) Data hold timing of capture register <1> If the valid edge of the TI0n0 pin is input while the CR0n1 register is read, the CR0n1 register performs capture operation, but the read value at this time is not guaranteed. However, the interrupt request signal (INTTM0n1) is generated as a result of detection of the valid edge. Figure 8-28. Data Hold Timing of Capture Register Count pulse TM0n count value Edge input INTTM0n1 Capture read signal CR0n1 capture value X Capture operation N+1 Capture operation is performed but read value is not guaranteed N N+1 N+2 M M+1 M+2 Remark n = 0 to 5 User's Manual U16889EJ1V0UD 355 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 <2> The values of the CR0n0 and CR0n1 registers are not guaranteed after 16-bit timer/event counter 0n has stopped. (4) Setting valid edge Before setting the valid edge of the TI0n0 pin, stop the timer operation by clearing the TMC0n.TMC0n2 and TMC0n.TMC0n3 bits to 00. Set the valid edge by using the PRM0n.ESn00 and PRM0n.ESn01 bits. Remark n = 0 to 5 (5) Re-triggering one-shot pulse (a) One-shot pulse output by software (16-bit timer/event counters 00, 01, 04, 05) When a one-shot pulse is output, do not set the OSPT0m bit to 1. Do not output the one-shot pulse again until the INTTM0m0 signal, which occurs upon match with the CR0m0 register, or the INTTM0m1 signal, which occurs upon match with the CR0m1 register, occurs. Remark m = 0, 1, 4, 5 (b) One-shot pulse output with external trigger (16-bit timer/event counters 04, 05) If the external trigger occurs again while a one-shot pulse is output, it is ignored. 356 User's Manual U16889EJ1V0UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (6) Operation of OVF0n flag (a) Setting of OVF0n flag The TMC0n.OVF0n flag is set to 1 in the following case in addition to when the TM0n register overflows. Select the mode in which clear & start occurs upon match between the TM0n register and the CR0n0 register. Set the CR0n0 register to FFFFH When the TM0n register is cleared from FFFFH to 0000H upon match with the CR0n register Figure 8-29. Operation Timing of OVF0n Flag Count pulse CR0n0 TM0n OVF0n INTTM0n0 FFFEH FFFFH FFFFH 0000H 0001H Remark n = 0 to 5 (b) Clearing of OVF0n flag After the TM0n register overflows, clearing OVF0n flag is invalid and set (1) again even if the OVF0n flag is cleared (0) before the next count clock is counted (before TM0n register becomes 0001H). Remark n = 0 to 5 User's Manual U16889EJ1V0UD 357 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (7) Timer operation (a) CR0n1 register capture Even if the TM0n register is read, the read data cannot be captured into the CR0n1 register. (b) TI0n0, TI0n1 pin acknowledgment Regardless of the CPU's operation mode, if the timer is stopped, signals input to the TI0n0 and TI0n1 pins are not acknowledged. (c) One-shot pulse output (16-bit timer/event counters 00, 01, 04, 05) One-shot pulse output operates normally in either the free-running timer mode or the mode in which clear & start occurs on the valid edge of the TI0k0 pin. Because no overflow occurs in the mode in which clear & start occurs upon match between the TM0m register and the CR0m0 register, one-shot pulse output is not possible. Remark n = 0 to 5 m = 0, 1, 4, 5 k = 4, 5 (8) Capture operation (a) If valid edge of TI0n0 is specified for count clock If the valid edge of TI0n0 is specified for the count clock, the capture register that specified TI0n0 as the trigger does not operate normally. (b) If both rising and falling edges are selected for valid edge of TI0n0 If both the rising and falling edges are selected for the valid edge of TI0n0, capture operation is not performed. (c) To ensure that signals from TI0n1 and TI0n0 are correctly captured For the capture trigger to capture the signals from TI0n1 and TI0n0 correctly, a pulse longer than two of the count clocks selected by the PRM0n register is required. (d) Interrupt request input Although a capture operation is performed at the falling edge of the count clock, an interrupt request signal (INTTM0n0, INTTM0n1) is generated at the rising edge of the next count clock. Remark n = 0 to 5 358 User's Manual U16889EJ1V0UD CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (9) Compare operation When set to the compare mode, the CR0n0 and CR0n1 registers do not perform capture operation even if a capture trigger is input. Caution The value of the CR0n0 register cannot be changed during timer operation. The value of the CR0n1 register cannot be changed during timer operation other than in the PPG output mode. To change the CR0n1 register in the PPG output mode, refer to 8.4.2 PPG output operation. Remark n = 0 to 5 (10) Edge detection (a) Sampling clock for noise elimination The sampling clock for noise elimination differs depending on whether the valid edge of TI0n0 is used for the count clock or as a capture trigger. In the former case, sampling is performed using fXX/4, and in the latter case, sampling is performed using the count clock selected by the PRM0n register. The first capture operation does not start until the valid edges are sampled and two valid levels are detected, thus eliminating noise with a short pulse width. Remarks 1. fXX: Main clock frequency 2. n = 0 to 5 User's Manual U16889EJ1V0UD 359 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 In the V850ES/KJ1, two channels of 8-bit timer/event counter 5 are provided. 9.1 Functions 8-bit timer/event counter 5n has the following two modes (n = 0, 1). * Mode using 8-bit timer/event counter alone (individual mode) * Mode using cascade connection (16-bit resolution: cascade connection mode) These two modes are described below. (1) Mode using 8-bit timer/event counter alone (individual mode) 8-bit timer/event counter 5n operates as an 8-bit timer/event counter. The following functions can be used. * Interval timer * External event counter * Square-wave output * PWM output (2) Mode using cascade connection (16-bit resolution: cascade connection mode) 8-bit timer/event counter 5n operates as a 16-bit timer/event counter by connecting the TM5n register in cascade. The following functions can be used. * Interval timer with 16-bit resolution * External event counter with 16-bit resolution * Square-wave output with 16-bit resolution The block diagram of 8-bit timer/event counter 5n is shown next. 360 User's Manual U16889EJ1V0UD CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 Figure 9-1. Block Diagram of 8-Bit Timer/Event Counter 5n Internal bus Mask circuit 8-bit timer compare register 5n (CR5n) Match Selector Selector INTTM5n TI5n Count clockNote 8-bit timer counter 5n (TM5n) OVF S INV Q R Selector TO5n Clear 3 Selector S R Q Invert level TCL5n2 TCL5n1 TCL5n0 Timer clock selection register 5n (TCL5n) TCE5n TMC5n6 TMC5n4 LVS5n LVR5n TMC5n1 TOE5n 8-bit timer mode control register 5n (TMC5n) Internal bus Note The count clock is set by the TCL5n register. Remark n = 0, 1 9.2 Configuration 8-bit timer/event counter 5n consists of the following hardware. Table 9-1. Configuration of 8-Bit Timer/Event Counter 5n Item Timer registers 8-bit timer counter 5n (TM5n) 16-bit timer counter 5 (TM5): Only when using cascade connection Registers 8-bit timer compare register 5n (CR5n) 16-bit timer compare register 5 (CR5): Only when using cascade connection Timer output Control registers Note Configuration 1 (TO5n pin) Timer clock selection register 5n (TCL5n) 8-bit timer mode control register 5n (TMC5n) 16-bit timer mode control register 5 (TMC5): Only when using cascade connection Note When using the functions of the TI5n and TO5n pins, refer to Table 4-19 Settings When Port Pins Are Used for Alternate Functions. Remark n = 0, 1 User's Manual U16889EJ1V0UD 361 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 (1) 8-bit timer counter 5n (TM5n) The TM5n register is an 8-bit read-only register that counts the count pulses. The counter is incremented in synchronization with the rising edge of the count clock. Through cascade connection, the TM5n registers can be used as a 16-bit timer. When using the TM50 register and the TM51 register in cascade as a 16-bit timer, these registers can be read only in 16-bit units. Therefore, read these registers twice and compare the values, taking into consideration that the reading occurs during a count change. After reset: 00H 7 TM5n (n = 0, 1) R 6 Address: TM50 FFFFF5C0H, TM51 FFFFF5C1H 5 4 3 2 1 0 The count value is reset to 00H in the following cases. <1> Reset <2> When the TMC5n.TCE5n bit is cleared (0) <3> The TM5n register and CR5n register match in the mode in which clear & start occurs on a match between the TM5n register and the CR5n register Caution When connected in cascade, these registers become 0000H even when the TCE50 bit in the lowest timer (TM50) is cleared. Remark n = 0, 1 362 User's Manual U16889EJ1V0UD CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 (2) 8-bit timer compare register 5n (CR5n) The CR5n register can be read and written in 8-bit units. In a mode other than the PWM mode, the value set to the CR5n register is always compared to the count value of the TM5n register, and if the two values match, an interrupt request signal (INTTM5n) is generated. In the PWM mode, TM5n register overflow causes the TO5n pin output to change to the active level, and when the values of the TM5n register and the CR5n register match, the TO5n pin output changes to the inactive level. The value of the CR5n register can be set in the range of 00H to FFH. When using the TM50 register and TM51 register in cascade as a 16-bit timer, the CR50 register and CR51 register operate as 16-bit timer compare register 5 (CR5). The counter value and register value are compared in 16-bit lengths, and if they match, an interrupt request signal (INTTM50) is generated. After reset: 00H 7 CR5n (n = 0, 1) R/W 6 Address: CR50 FFFFF5C2H, CR51 FFFFF5C3H 5 4 3 2 1 0 Cautions 1. In the mode in which clear & start occurs upon a match of the TM5n register and CR5n register (TMC5n.TMC5n6 bit = 0), do not write a different value to the CR5n register during the count operation. 2. In the PWM mode, set the CR5n register rewrite interval to three or more count clocks (clock selected with the TCL5n register). 3. Before changing the value of the CR5n register when using a cascade connection, be sure to stop the timer operation. Remark n = 0, 1 User's Manual U16889EJ1V0UD 363 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 9.3 Registers The following two registers are used to control 8-bit timer/event counter 5n. * Timer clock selection register 5n (TCL5n) * 8-bit timer mode control register 5n (TMC5n) Remark To use the functions of the TI5n and TO5n pins, refer to Table 4-19 Settings When Port Pins Are Used for Alternate Functions. (1) Timer clock selection register 5n (TCL5n) The TCL5n register sets the count clock of 8-bit timer/event counter 5n and the valid edge of the TI5n pin input. The TCL5n register can be read or written in 8-bit units. After reset, this register is cleared to 00H. After reset: 00H 7 TCL5n (n = 0, 1) 0 R/W 6 0 Address: TCL50 FFFFF5C4H, TCL51 FFFFF5C5H 5 0 4 0 3 0 2 TCL5n2 1 TCL5n1 0 TCL5n0 TCL5n2 TCL5n1 TCL5n0 Clock Count clock selectionNote fXX 20 MHz 10 MHz - - 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Falling edge of TI5n Rising edge of TI5n fXX fXX/2 fXX/4 fXX/64 fXX/256 INTTM010 - - Setting prohibited 100 ns 100 ns 200 ns 3.2 s 12.8 s - 200 ns 0.4 s 6.4 s 25.6 s - Note When the internal clock is selected, set so as to satisfy the following conditions. REGC = VDD = 4.0 to 5.5 V: Count clock 10 MHz REGC = Capacity, VDD = 4.0 to 5.5 V: Count clock 5 MHz REGC = VDD = 2.7 to 4.0 V: Count clock 5 MHz Caution Before overwriting the TCL5n register with different data, stop the timer operation. Remark When the TM5n register is connected in cascade, the TCL51 register settings are invalid. 364 User's Manual U16889EJ1V0UD CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 (2) 8-bit timer mode control register 5n (TMC5n) The TMC5n register performs the following six settings. * Controls counting by the TM5n register * Selects the operation mode of the TM5n register * Selects the individual mode or cascade connection mode * Sets the status of the timer output flip-flop * Controls the timer output flip-flop or selects the active level in the PWM (free-running timer) mode * Controls timer output The TMC5n register can be read or written in 8-bit or 1-bit units. After reset, this register is cleared to 00H. User's Manual U16889EJ1V0UD 365 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 After reset: 00H <7> TMC5n (n = 0, 1) TCE5n 0 1 TCE5n R/W 6 TMC5n6 Address: TMC50 FFFFF5C6H, TMC51 FFFFF5C7H 5 0 4 TMC514 Note <3> LVS5n <2> LVR5n 1 TMC5n1 <0> TOE5n Control of count operation of 8-bit timer/event counter 5n Counting is disabled after the counter is cleared to 0 (counter disabled) Start count operation TMC5n6 0 1 Selection of operation mode of 8-bit timer/event counter 5n Mode in which clear & start occurs on match between TM5n register and CR5n register PWM (free-running timer) mode TMC514 Selection of individual mode or cascade connection mode for 8-bit timer/event counter 51 0 1 Individual mode Cascade connection mode (connected with 8-bit timer/event counter 50) LVS5n 0 0 1 1 LVR5n 0 1 0 1 Unchanged Setting of status of timer output F/F Reset timer output F/F to 0 Set timer output F/F to 1 Setting prohibited TMC5n1 Other than PWM (free-running timer) mode (TMC5n6 bit = 0) Controls timer F/F 0 1 Disable inversion operation Enable inversion operation PWM (free-running timer) mode (TMC5n6 bit = 1) Selects active level High active Low active TOE5n 0 1 Timer output control Disable output (TO5n pin is low level) Enable output Note Bit 4 of the TMC50 register is fixed to 0. Cautions 1. Because the TO51 and TI51 pins are alternate functions of the same pin, only one can be used at one time. 2. The LVS5n and LVR5n bit settings are valid in modes other than the PWM mode. 3. Do not set <1> to <4> below at the same time. Set as follows. <1> Set the TMC5n1, TMC5n6, and TMC514Note bits: <2> Set the TOE5n bit for timer output enable: <3> Set the LVS5n and LVR5n bits (Caution 2): <4> Set the TCE5n bit Remarks 1. In the PWM mode, the PWM output is set to the inactive level by the TCE5n bit = 0. 2. When the LVS5n and LVR5n bits are read, 0 is read. 3. The values of the TMC5n6, LVS5n, LVR5n, TMC5n1, and TOE5n bits are reflected to the TO5n output regardless of the TCE5n bit value. Setting of operation mode Timer output enable Setting of timer output F/F 366 User's Manual U16889EJ1V0UD CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 9.4 Operation 9.4.1 Operation as interval timer 8-bit timer/event counter 5n operates as an interval timer that repeatedly generates interrupts at the interval of the count value preset in the CR5n register. If the count value in the TM5n register matches the value set in the CR5n register, the value of the TM5n register is cleared to 00H and counting is continued, and at the same time, an interrupt request signal (INTTM5n) is generated. Setting method <1> Set each register. * TCL5n register: * CR5n register: Selects the count clock (t). Compare value (N) between the TM5n register and CR5n register (TMC5n register = 0000xx00B, x: don't care). <2> When the TMC5n.TCE5n bit is set to 1, the count operation starts. <3> When the values of the TM5n register and CR5n register match, the INTTM5n signal is generated (TM5n register is cleared to 00H). <4> Then, the INTTM5n signal is repeatedly generated at the same interval. To stop counting, set the TCE5n bit = 0. Interval time = (N + 1) x t: N = 00H to FFH Caution During interval timer operation, do not rewrite the value of the CR5n register. Remark n = 0, 1 Figure 9-2. Timing of Interval Timer Operation (1/2) * TMC5n register: Stops count operation and selects the mode in which clear & start occurs on a match Basic operation t Count clock TM5n count value 00H 01H N 00H Clear N 01H N 00H Clear N N 01H N Count start CR5n TCE5n INTTM5n N Interrupt acknowledgment Interrupt acknowledgment Interval time Interval time Remark n = 0, 1 User's Manual U16889EJ1V0UD 367 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 Figure 9-2. Timing of Interval Timer Operation (2/2) When CR5n register = 00H t Count clock TM5n count value 00H CR5n TCE5n INTTM5n Interval time 00H 00H 00H 00H Remark n = 0, 1 When CR5n register = FFH t Count clock TM5n count value 00H CR5n TCE5n INTTM5n Interrupt acknowledgment Interval time Interrupt acknowledgment FFH 01H FEH FFH FFH 00H FEH FFH FFH 00H Remark n = 0, 1 368 User's Manual U16889EJ1V0UD CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 9.4.2 Operation as external event counter The external event counter counts the number of clock pulses input to the TI5n pin from an external source by using the TM5n register. Each time the valid edge specified by the TCL5n register is input to the TI5n pin, the TM5n register is incremented. Either the rising edge or the falling edge can be specified as the valid edge. When the count value of the TM5n register matches the value of the CR5n register, the TM5n register is cleared to 00H and an interrupt request signal (INTTM5n) is generated. Setting method <1> Set each register. * TCL5n register: Selects the TI5n pin input edge. Falling edge of TI5n pin TLC5n register = 00H Rising edge of TI5n pin TCL5n register = 01H * CR5n register: Compare value (N) between the TM5n register and CR5n register, disables timer output F/F inversion operation, and disables timer output. (TMC5n register = 0000xx00B, x: don't care) * For the alternate-function pin settings, refer to Table 4-19 Settings When Port Pins Are Used for Alternate Functions. <2> When the TMC5n.TCE5n bit is set to 1, the counter counts the number of pulses input from the TI5n pin. <3> When the values of the TM5n register and CR5n register match, the INTTM5n signal is generated (TM5n register is cleared to 00H). <4> Then, the INTTM5n signal is generated each time the values of the TM5n register and CR5n register match. INTTM5n signal is generated when the valid edge of TI5n pin is input N + 1 times: N = 00H to FFH * TMC5n register: Stops count operation, selects the mode in which clear & start occurs on a match Caution During external event counter operation, do not rewrite the value of the CR5n register. Remark n = 0, 1 Figure 9-3. Timing of External Event Counter Operation (with Rising Edge Specified) TI5n TM5n count value 00H 01H 02H 03H 04H 05H N-1 N 00H 01H 02H 03H Count start CR5n N TCE5n INTTM5n Remark n = 0, 1 User's Manual U16889EJ1V0UD 369 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 9.4.3 Square-wave output operation A square wave with any frequency can be output at an interval determined by the value preset in the CR5n register. By setting the TMC5n.TOE5n bit to 1, the output status of the TO5n pin is inverted at an interval determined by the count value preset in the CR5n register. In this way, a square wave of any frequency can be output (duty = 50%) (n = 0, 1). Setting method <1> Set each register. * TCL5n register: * CR5n register: Selects the count clock (t). Compare value (N) between the TM5n register and CR5n register, sets initial value of timer output, enables timer output F/F inversion operation, and enables timer output. (TMC5n register = 00001011B or 00000111B) * For the alternate-function pin settings, refer to Table 4-19 Settings When Port Pins Are Used for Alternate Functions. <2> When the TMC5n.TCE5n bit is set to 1, counting starts. <3> When the values of the TM5n register and CR5n register match, the timer output F/F is inverted. Moreover, the INTTM5n signal is generated and the TM5n register is cleared to 00H. <4> Then, the timer output F/F is inverted during the same interval and a square wave is output from the TO5n pin. * TMC5n register: Stops count operation, selects the mode in which clear & start occurs on a match Frequency = 1/2t(N + 1): N = 00H to FFH Caution Do not rewrite the value of the CR5n register during square-wave output. 370 User's Manual U16889EJ1V0UD CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 Figure 9-4. Timing of Square-Wave Output Operation t Count clock TM5n count value 00H 01H N 00H Clear N 01H N 00H Clear N N 01H N Count start CR5n TCE5n INTTM5n N Interrupt acknowledgment TO5nNote Interval time Interrupt acknowledgment Interval time Note The initial value of the TO5n pin output can be set using the TMC5n.LVS5n and TMC5n.LVR5n bits. Remark n = 0, 1 User's Manual U16889EJ1V0UD 371 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 9.4.4 8-bit PWM output operation By setting the TMC5n.TMC5n6 bit to 1, 8-bit timer/event counter 5n performs PWM output. Pulses with a duty factor determined by the value set in the CR5n register are output from the TO5n pin. Set the width of the active level of the PWM pulse in the CR5n register. The active level can be selected using the TMC5n.TMC5n1 bit. The count clock can be selected using the TCL5n register. PWM output can be enabled/disabled by the TMC5n.TOE5n bit. Caution The CR5n register rewrite interval must be three or more operation clocks (set by the TCL5n register). Use method <1> Set each register. * TCL5n register: * CR5n register: Selects the count clock (t). Compare value (N) unchanged, sets active level, and enables timer output. (TMC5n register = 01000001B or 01000011B) * For the alternate-function pin settings, refer to Table 4-19 Settings When Port Pins Are Used for Alternate Functions. <2> When the TMC5n.TCE5n bit is set to 1, counting starts. PWM output operation <1> When counting starts, PWM output (output from the TO5n pin) outputs the inactive level until an overflow occurs. <2> When an overflow occurs, the active level set by setting method <1> is output. The active level is output until the value of the CR5n register and the count value of the TM5n register match. An interrupt request signal (INTTM5n) is generated. <3> When the value of the CR5n register and the count value of the TM5n register match, the inactive level is output and continues to be output until an overflow occurs again. <4> Then, steps <2> and <3> are repeated until counting is stopped. <5> When counting is stopped by clearing TCE5n bit to 0, PWM output becomes inactive. Cycle = 256t, active level width = Nt, duty = N/256: N = 00H to FFH * TMC5n register: Stops count operation, selects PWM mode, and leave timer output F/F Remarks 1. n = 0, 1 2. For the detailed timing, refer to Figure 9-5 Timing of PWM Output Operation and Figure 9-6 Timing of Operation Based on CR5n Register Transitions. 372 User's Manual U16889EJ1V0UD CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 (a) Basic operation of PWM output Figure 9-5. Timing of PWM Output Operation Basic operation (active level = H) t Count clock TM5n count value CR5n TCE5n INTTM5n TO5n Active level Inactive level Active level 00H 01H N FFH 00H 01H 02H N N+1 FFH 00H 01H 02H M 00H When CR5n register = 00H t Count clock TM5n count value CR5n TCE5n INTTM5n TO5n Inactive level Inactive level 00H 01H 00H FFH 00H 01H 02H N N + 1N + 2 FFH 00H 01H 02H M 00H When CR5n register = FFH t Count clock TM5n count value CR5n TCE5n INTTM5n TO5n Inactive level Active level Inactive level Active level Inactive level 00H 01H FFH FFH 00H 01H 02H N N + 1N + 2 FFH 00H 01H 02H M 00H Remark n = 0, 1 User's Manual U16889EJ1V0UD 373 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 (b) Operation based on CR5n register transitions Figure 9-6. Timing of Operation Based on CR5n Register Transitions When the value of the CR5n register changes from N to M before the rising edge of the FFH clock The value of the CR5n register is transferred at the overflow that occurs immediately after. t Count clock TM5n count value CR5n TCE5n INTTM5n TO5n <2> <1> CR5n transition (N M) H N N-1N-2 N FFH 00H 01H 02H M M M-1M-2 FFH 00H 01H 02H M M-1M-2 When the value of the CR5n register changes from N to M after the rising edge of the FFH clock The value of the CR5n register is transferred at the second overflow. t Count clock TM5n count value CR5n TCE5n INTTM5n TO5n <1> CR5n transition (N M) <2> H N N-1N-2 N FFH 00H 01H 02H 03H N N N-1N-2 FFH 00H 01H 02H M M M-1M-2 Caution In the case of reload from the CR5n register between <1> and <2>, the value that is actually used differs (Read value: M; Actual value of CR5n register: N). Remark n = 0, 1 374 User's Manual U16889EJ1V0UD CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 9.4.5 Operation as interval timer (16 bits) The 16-bit resolution timer/event counter mode is selected by setting the TMC51.TMC514 bit to 1. 8-bit timer/event counter 5n operates as an interval timer by repeatedly generating interrupts using the count value preset in 16-bit timer compare register 5 (CR5) as the interval. Setting method <1> Set each register. * TCL50 register: * CR50 register: * CR51 register: * TMC50, TMC51 register: Selects the count clock (t) (The TCL51 register does not need to be set in cascade connection) Compare value (N) ... Lower 8 bits (settable from 00H to FFH) Compare value (N) ... Higher 8 bits (settable from 00H to FFH) Selects the mode in which clear & start occurs on a match between TM5 register and CR5 register (x: don't care) TMC50 register = 0000xx00B TMC51 register = 0001xx00B <2> Set the TMC51.TCE51 bit to 1. Then set the TMC50.TCE50 bit to 1 to start the count operation. <3> When the values of the TM5 register and CR5 register connected in cascade match, the INTTM50 signal is generated (the TM5 register is cleared to 0000H). <4> The INTTM50 signal is then generated repeatedly at the same interval. Interval time = (N + 1) x t: N = 0000H to FFFFH Cautions 1. To write using 8-bit access during cascade connection, set the TCE51 bit to 1 at operation start and then set the TCE50 bit to 1. When operation is stopped, clear the TCE50 bit to 0 and then clear the TCE51 bit to 0. 2. During cascade connection, TI50 input, TO50 output, and the INTTM50 signal are used. Do not use TI51 input, TO51 output, and the INTTM51 signal; mask them instead (for details, refer to CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION). Clear the LVS51, LVR51, TMC511, and TOE51 bits to 0. 3. Do not change the value of the CR5 register during timer operation. User's Manual U16889EJ1V0UD 375 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 Figure 9-7 shows a timing example of the cascade connection mode with 16-bit resolution. Figure 9-7. Cascade Connection Mode with 16-Bit Resolution t Count clock TM50 count value 00H TM51 count value 00H CR50 CR51 TCE50 TCE51 INTTM50 Interval time Operation enabled, count start Interrupt occurrence, counter cleared Operation stopped N M 01H N N+1 FFH 00H 01H FFH 00H 02H FFH 00H 01H M-1 M N 00H 01H 00H A 00H B 00H 376 User's Manual U16889EJ1V0UD CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 9.4.6 Operation as external event counter (16 bits) The 16-bit resolution timer/event counter mode is selected by setting the TMC51.TMC514 bit to 1. The external event counter counts the number of clock pulses input to the TI50 pin from an external source using 16-bit timer counter 5 (TM5). Setting method <1> Set each register. * TCL50 register: Selects the TI50 pin input edge. (The TCL51 register does not have to be set during cascade connection.) Falling edge of TI50 pin TCL50 register = 00H Rising edge of TI50 pin TCL50 register = 01H * CR50 register: * CR51 register: Compare value (N) ... Lower 8 bits (settable from 00H to FFH) Compare value (N) ... Higher 8 bits (settable from 00H to FFH) between the TM5 register and CR5 register, disables timer output F/F inversion, and disables timer output. (x: don't care) TMC50 register = 0000xx00B TMC51 register = 0001xx00B * For the alternate-function pin settings, refer to Table 4-19 Settings When Port Pins Are Used for Alternate Functions. <2> Set the TMC51.TCE51 bit to 1. Then set the TMC50.TCE50 bit to 1 and count the number of pulses input from the TI50 pin. <3> When the values of the TM5 register and CR5 register connected in cascade match, the INTTM50 signal is generated (the TM5 register is cleared to 0000H). <4> The INTTM50 signal is then generated each time the values of the TM5 register and CR5 register match. INTTM50 signal is generated when the valid edge of TI50 pin is input N + 1 times: N = 0000H to FFFFH * TMC50, TMC51 registers: Stops count operation, selects the clear & stop mode entered on a match Cautions 1. During external event counter operation, do not rewrite the value of the CR5n register. 2. To write using 8-bit access during cascade connection, set the TCE51 bit to 1 and then set the TCE50 bit to 1. When operation is stopped, clear the TCE50 bit to 0 and then clear the TCE51 bit to 0 (n = 0, 1). 3. During cascade connection, TI50 input and the INTTM50 signal are used. Do not use TI51 input, TO51 output, and the INTTM51 signal; mask them instead (for details, refer to CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION). Clear the LVS51, LVR51, TMC511, and TOE51 bits to 0. 4. Do not change the value of the CR5 register during external event counter operation. User's Manual U16889EJ1V0UD 377 CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 9.4.7 Square-wave output operation (16-bit resolution) The 16-bit resolution timer/event counter mode is selected by setting the TMC51.TMC514 bit to 1. 8-bit timer/event counter 5n outputs a square wave of any frequency using the interval preset in 16-bit timer compare register 5 (CR5). Setting method <1> Set each register. * TCL50 register: * CR50 register: * CR51 register: Selects the count clock (t) (The TCL51 register does not have to be set in cascade connection) Compare value (N) ... Lower 8 bits (settable from 00H to FFH) Compare value (N) ... Higher 8 bits (settable from 00H to FFH) match between the TM5 register and CR5 register. LVS50 1 0 LVR50 0 1 Timer Output F/F Status Settings High-level output Low-level output * TMC50, TCM51 registers: Stops count operation, selects the mode in which clear & start occurs on a Enables timer output F/F inversion, and enables timer output. TMC50 register = 00001011B or 00000111B TMC51 register = 00010000B * For the alternate-function pin settings, refer to Table 4-19 Settings When Port Pins Are Used for Alternate Functions. <2> Set the TMC51.TCE51 bit to 1. Then set the TMC50.TCE50 bit to 1 to start the count operation. <3> When the values of the TM5 register and the CR5 register connected in cascade match, the TO50 timer output F/F is inverted. Moreover, the INTTM50 signal is generated and the TM5 register is cleared to 0000H. <4> Then, the timer output F/F is inverted during the same interval and a square wave is output from the TO50 pin. Frequency = 1/2t(N + 1): N = 0000H to FFFFH Caution Do not write a different value to the CR5 register during operation. 378 User's Manual U16889EJ1V0UD CHAPTER 9 8-BIT TIMER/EVENT COUNTER 5 9.4.8 Cautions (1) Error on starting timer An error of up to 1 clock occurs before the match signal is generated after the timer has been started. This is because the TM5n register is started asynchronously to the count pulse. Figure 9-8. Count Start Timing of TM5n Register Count pulse TM5n count value 00H Timer start 01H 02H 03H 04H Remark n = 0, 1 User's Manual U16889EJ1V0UD 379 CHAPTER 10 8-BIT TIMER H In the V850ES/KJ1, two channels of 8-bit timer H are provided. 10.1 Functions 8-bit timer Hn has the following functions (n = 0, 1). * Interval timer * PWM output * Square ware output * Carrier generator mode 10.2 Configuration 8-bit timer Hn consists of the following hardware. Table 10-1. Configuration of 8-Bit Timer Hn Item Timer registers Register Configuration 8-bit timer counter Hn: 1 each 8-bit timer H compare register n0 (CMPn0): 1 each 8-bit timer H compare register n1 (CMPn1): 1 each Timer outputs Control registers Note 1 each (TOHn pin) 8-bit timer H mode register n (TMHMDn) 8-bit timer H carrier control register n (TMCYCn) Note To use the TOHn pin function, refer to Table 4-19 Settings When Port Pins Are Used for Alternate Functions. Remark n = 0, 1 380 User's Manual U16889EJ1V0UD CHAPTER 10 8-BIT TIMER H The block diagram is shown below. Figure 10-1. Block Diagram of 8-Bit Timer Hn Internal bus 8-bit timer H mode register n (TMHMDn) TMHEn CKSHn2 CKSHn1 CKSHn0 TMMDn1TMMDn0 TOLEVn TOENn 8-bit timer H compare register n1 (CMPn1) 8-bit timer H compare register n0 (CMPn0) 8-bit timer H carrier control register n (TMCYCn) RMCn NRZBn NRZn Reload/ interrupt control INTTM5n 3 2 Decoder Selector TOHn Match fXX fXX/2 fXX/22 fXX/24 fXX/26 fXX/210 fXT Interrupt generator F/F R Output controller Level inversion Selector Carrier generator mode signal PWM mode signal 8-bit timer counter Hn Clear Timer H enable signal 1 0 INTTMHn Remark n = 0, 1 User's Manual U16889EJ1V0UD 381 CHAPTER 10 8-BIT TIMER H (1) 8-bit timer H compare register n0 (CMPn0) The CMPn0 register can be read or written in 8-bit units. After reset, CMPn0 is cleared to 00H. After reset: 00H 7 CMPn0 (n = 0, 1) R/W 6 Address: CMP00 FFFFF582H, CMP10 FFFFF592H 5 4 3 2 1 0 Caution Rewriting the CMPn0 register during timer count operation is prohibited. (2) 8-bit timer H compare register n1 (CMPn1) The CMPn1 register can be read or written in 8-bit units. After reset, CMPn1 is cleared to 00H. After reset: 00H 7 CMPn1 (n = 0, 1) R/W 6 Address: CMP01 FFFFF583H, CMP11 FFFFF593H 5 4 3 2 1 0 The CMPn1 register can be rewritten during timer count operation. In the carrier generator mode, after the CMPn1 register is set, if the count value of 8-bit timer counter Hn and the set value of the CMPn1 register match, an interrupt request signal (INTTMHn) is generated. At the same time, the value of 8-bit timer counter Hn is cleared to 00H. If the set value of the CMPn1 register is rewritten during timer operation, the reload timing is when the count value of 8-bit timer counter Hn and the set value of the CMPn1 register match. If the transfer timing and write to the CMPn1 register from the CPU conflict, transfer is not performed. Caution In the PWM output mode and carrier generator mode, be sure to set the CMPn1 register when starting the timer count operation (TMHMDn.TMHEn bit = 1) after the timer count operation was stopped (TMHEn bit = 0) (be sure to set again even if setting the same value to the CMPn1 register). 382 User's Manual U16889EJ1V0UD CHAPTER 10 8-BIT TIMER H 10.3 Registers The registers that control 8-bit timer Hn are as follows. * 8-bit timer H mode register n (TMHMDn) * 8-bit timer H carrier control register n (TMCYCn) Remarks 1. To use the TOHn pin function, refer to Table 4-19 Alternate Functions. 2. n = 0, 1 (1) 8-bit timer H mode register n (TMHMDn) The TMHMDn register controls the mode of 8-bit timer Hn. TMHMDn register can be read or written in 8-bit or 1-bit units. After reset, TMHMDn is cleared to 00H. Remark n = 0, 1 Settings When Port Pins Are Used for User's Manual U16889EJ1V0UD 383 CHAPTER 10 8-BIT TIMER H (a) 8-bit timer H mode register 0 (TMHMD0) After reset: 00H <7> TMHMD0 TMHE0 R/W 6 Address: FFFFF580H 5 4 3 2 <1> <0> TOEN0 CKSH02 CKSH01 CKSH00 TMMD01 TMMD00 TOLEV0 TMHE0 0 1 8-bit timer H0 operation enable Stop timer count operation (8-bit timer counter H0 = 00H) Enable timer count operation (Counting starts when clock is input) CKSH02 CKSH01 CKSH00 Count clock 0 0 0 0 1 1 0 0 1 1 0 0 Other than above 0 1 0 1 0 1 fXX fXX/2 fXX/4 fXX/16 fXX/64 fXX/1024 Note Selection of count clock fXX = 20 MHz fXX = 16.0 MHz fXX = 10.0 MHz Setting prohibited Setting prohibited 100 ns 100 ns 200 ns 800 ns 1.6 s 51.2 s 125 ns 250 ns 1 s 4 s 64 s 200 ns 400 ns 1.6 s 6.4 s 102.4 s Setting prohibited TMMD01 TMMD00 0 0 1 1 0 1 0 1 8-bit timer H0 operation mode Interval timer mode Carrier generator mode PWM output mode Setting prohibited TOLEV0 0 1 Low level High level Timer output level control (default) TOEN0 0 1 Disable output Enable output Timer output control Note Set so as to satisfy the following conditions. REGC = VDD = 4.0 to 5.5 V: Count clock 10 MHz REGC = Capacity, VDD = 4.0 to 5.5 V: Count clock 5 MHz REGC = VDD = 2.7 to 4.0 V: Count clock 5 MHz Cautions 1. When the TMHE0 bit = 1, setting bits other than those of the TMHMD0 register is prohibited. 2. In the PWM output mode and carrier generator mode, be sure to set the CMP01 register when starting the timer count operation (TMHE0 bit = 1) after the timer count operation was stopped (TMHE0 bit = 0) (be sure to set again even if setting the same value to the CMP01 register). 3. When using the carrier generator mode, set 8-bit timer H0 count clock frequency to six times 8-bit timer/event counter 50 count clock frequency or higher. 384 User's Manual U16889EJ1V0UD CHAPTER 10 8-BIT TIMER H (b) 8-bit timer H mode register 1 (TMHMD1) After reset: 00H <7> TMHMD1 TMHE1 R/W 6 Address: FFFFF590H 5 4 3 2 <1> <0> TOEN1 CKSH12 CKSH11 CKSH10 TMMD11 TMMD10 TOLEV1 TMHE1 0 1 8-bit timer H1 operation enable Stop timer count operation (8-bit timer counter H1 = 00H) Enable timer count operation (Counting starts when clock is input) CKSH12 CKSH11 CKSH10 Count clock 0 0 0 0 1 1 0 0 1 1 0 0 Other than above 0 1 0 1 0 1 fXX fXX/2 fXX/4 fXX/16 fXX/64 Note Selection of count clock fXX = 20.0 MHz fXX = 16.0 MHz fXX = 10.0 MHz Setting prohibited Setting prohibited 100 ns 100 ns 200 ns 800 ns 1.6 s 125 ns 250 ns 1 s 4 s 200 ns 400 ns 1.6 s 6.4 s fXT (subclock) Setting prohibited TMMD11 TMMD10 0 0 1 1 0 1 0 1 8-bit timer H1 operation mode Interval timer mode Carrier generator mode PWM output mode Setting prohibited TOLEV1 0 1 Low level High level Timer output level control (default) TOEN1 0 1 Disable output Enable output Timer output control Note Set so as to satisfy the following conditions. REGC = VDD = 4.0 to 5.5 V: Count clock 10 MHz REGC = Capacity, VDD = 4.0 to 5.5 V: Count clock 5 MHz REGC = VDD = 2.7 to 4.0 V: Count clock 5 MHz Cautions 1. When the TMHE1 bit = 1, setting bits other than those of the TMHMD1 register is prohibited. 2. In the PWM output mode and carrier generator mode, be sure to set the CMP11 register when starting the timer count operation (TMHE1 bit = 1) after the timer count operation was stopped (TMHE1 bit = 0) (be sure to set again even if setting the same value to the CMP11 register). 3. When using the carrier generator mode, set 8-bit timer H1 count clock frequency to six times 8-bit timer/event counter 51 count clock frequency or higher. User's Manual U16889EJ1V0UD 385 CHAPTER 10 8-BIT TIMER H (2) 8-bit timer H carrier control register n (TMCYCn) This register controls the 8-bit timer Hn remote control output and carrier pulse output status. TMCYCn register can be read or written in 8-bit or 1-bit units. The NRZn bit is a read-only bit. After reset, TMCYCn is cleared to 00H. Remark n = 0, 1 After reset: 00H 7 TMCYCn (n = 0, 1) RMCn 0 0 1 1 0 R/W 6 0 Address: TMCYC0 FFFFF581H, TMCYC1 FFFFF591H 5 0 4 0 3 0 2 RMCn 1 NRZBn <0> NRZn NRZBn 0 1 0 1 Low-level output Remote control output High-level output Low-level output Carrier pulse output NRZn 0 1 Carrier pulse output status flag Carrier output disabled status (low-level status) Carrier output enable status 386 User's Manual U16889EJ1V0UD CHAPTER 10 8-BIT TIMER H 10.4 Operation 10.4.1 Operation as interval timer/square wave output When the count value of 8-bit timer counter Hn and the set value of the CMPn0 register match, an interrupt request signal (INTTMHn) is generated and 8-bit timer counter Hn is cleared to 00H. The CMPn1 register cannot be used in the interval timer mode. Even if the CMPn1 register is set, this has no effect on the timer output because matches between 8-bit timer counter Hn and the CMPn1 register are not detected. A square wave of the desired frequency (duty = 50%) is output from the TOHn pin, by setting the TMHMDn.TOENn bit to 1. (1) Usage method The INTTMHn signal is repeatedly generated in the same interval. <1> Set each register. Figure 10-2. Register Settings in Interval Timer Mode (i) 8-bit timer H mode register n (TMHMDn) settings TMHEn TMHMDn 0 CKSHn2 CKSHn1 CKSHn0 TMMDn1 TMMDn0 TOLEVn 0/1 0/1 0/1 0 0 0/1 TOENn 0/1 Sets timer output Sets timer output level inversion Sets interval timer mode Selects count clock (fCNT) Stops count operation (ii) CMPn0 register settings * Compare value (N) <2> When the TMHEn bit is set to 1, counting starts. User's Manual U16889EJ1V0UD 387 CHAPTER 10 8-BIT TIMER H <3> When the count value of 8-bit timer counter Hn and the set value of the CMPn0 register match, the INTTMHn signal is generated and 8-bit timer counter Hn is cleared to 00H. Interval time = (N + 1)/fCNT <4> Then, the INTTMHn signal is generated in the same interval. To stop the count operation, clear the TMHEn bit to 0. (2) Timing chart The timing in the interval timer mode is as follows. Figure 10-3. Timing of Interval Timer/Square Wave Output Operation (1/2) Basic operation Count clock Count start 8-bit timer counter Hn count value 00H 01H N 00H Clear CMPn0 N 01H N 00H Clear 01H 00H TMHEn INTTMHn Interval time TOHn <1> <2> Level inversion, match interrupt occurrence, 8-bit timer counter clear <3> <2> Level inversion, match interrupt occurrence, 8-bit timer counter clear <1> When the TMHEn bit is set to 1, the count operation is enabled. The count clock starts counting no more than one clock after operation has been enabled. <2> When the count value of 8-bit timer counter Hn and the set value of the CMPn0 register match, the value of 8-bit timer counter Hn is cleared, the TOHn output level is inverted, and the INTTMHn signal is output. <3> The INTTMHn signal and TOHn output become inactive when the TMHEn bit is cleared to 0 during 8-bit timer Hn operation. If the level is already inactive, it remains unchanged. Remark n = 0, 1 388 User's Manual U16889EJ1V0UD CHAPTER 10 8-BIT TIMER H Figure 10-3. Timing of Interval Timer/Square Wave Output Operation (2/2) Operation when CMPn0 = FFH Count clock Count start 8-bit timer counter Hn count value 00H 01H FEH FFH 00H Clear CMPn0 FFH FEH FFH 00H Clear TMHEn INTTMHn TOHn Interval time Operation when CMPn0 = 00H Count clock Count start 8-bit timer counter Hn count value 00H CMPn0 00H TMHEn INTTMHn TOHn Interval time Remark n = 0, 1 User's Manual U16889EJ1V0UD 389 CHAPTER 10 8-BIT TIMER H 10.4.2 PWM output mode operation In the PWM output mode, a pulse of any duty and cycle can be output. The CMPn0 register controls the timer output (TOHn) cycle. Rewriting the CMPn0 register during timer operation is prohibited. The CMPn1 register controls the timer output (TOHn) duty. The CMPn1 register can be rewritten during timer operation. The operation in the PWM output mode is as follows. After timer counting starts, when the count value of 8-bit timer counter Hn and the set value of the CMPn0 register match, the TOHn output becomes active and 8-bit timer counter Hn is cleared to 00H. When the count value of 8-bit timer counter Hn and the set value of the CMPn1 register match, TOHn output becomes inactive. (1) Usage method In the PWM output mode, a pulse of any duty and cycle can be output. <1> Set each register. Figure 10-4. Register Settings in PWM Output Mode (i) 8-bit timer H mode register n (TMHMDn) settings TMHEn CKSHn2 CKSHn1 CKSHn0 TMMDn1 TMMDn0 TOLEVn 0/1 0/1 0/1 1 0 0/1 TOENn 1 TMHMDn 0 Enables timer output Sets timer output level inversion Selects PWM output mode Selects count clock (fCNT) Stops count operation (ii) CMPn0 register setting * Compare value (N): Sets cycle (ii) CMPn1 register setting * Compare value (M): Sets duty Remarks 1. n = 0, 1 2. 00H CMPn1 (M) < CMPn0 (N) FFH <2> When the TMHEn bit is set to 1, counting starts. 390 User's Manual U16889EJ1V0UD CHAPTER 10 8-BIT TIMER H <3> After the count operation is enabled, the first compare register to be compared is the CMPn0 register. When the count value of 8-bit timer counter Hn and the set value of the CMPn0 register match, 8-bit timer counter Hn is cleared, an interrupt request signal (INTTMHn) is generated, and the TOHn output becomes active. At the same time, the register that is compared with 8-bit timer counter Hn changes from the CMPn0 register to the CMPn1 register. <4> When the count value of 8-bit timer counter Hn and the set value of the CMPn1 register match, the TOHn output becomes inactive, and at the same time the register that is compared with 8-bit timer counter Hn changes from the CMPn1 register to the CMPn0 register. At this time, 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated. <5> A pulse of any duty can be obtained through the repetition of steps <3> and <4> above. <6> To stop the count operation, clear the TMHEn bit to 0. Designating the set value of the CMPn0 register as (N), the set value of the CMPn1 register as (M), and the count clock frequency as fCNT, the PWM pulse output cycle and duty are as follows. PWM pulse output cycle = (N + 1)/fCNT Duty = inactive width: Active width = (M + 1) : (N + 1) Cautions 1. In the PWM output mode, three operating clocks (signal selected by CKSHn0 to CKSHn2 bits) are required for actual transfer of the new value to the register after the CMPn1 register has been rewritten. 2. Be sure to set the CMPn1 register when starting the timer count operation (TMHEn bit = 1) after the timer count operation was stopped (TMHEn bit = 0) (be sure to set again even if setting the same value to the CMPn1 register). User's Manual U16889EJ1V0UD 391 CHAPTER 10 8-BIT TIMER H (2) Timing chart The operation timing in the PWM output mode is as follows. Caution The set value (M) of the CMPn1 register and the set value (N) of the CMPn0 register must always be set within the following range. 00H CMPn1 (M) < CMPn0 (N) FFH Figure 10-5. Operation Timing in PWM Output Mode (1/4) Basic operation Count clock 8-bit timer counter Hn count value 00H 01H A5H 00H 01H 02H A5H 00H 01H 02H A5H 00H CMPn0 A5H CMPn1 01H TMHEn INTTMHn TOHn (TOLEVn = 0) <1> TOHn (TOLEVn = 1) <2> <3> <4> <1> When the TMHEn bit is set to 1, counting starts. At this time TOHn output stays inactive (TOLEVn bit = 0). <2> When the count value of 8-bit timer counter Hn and the set value of the CMPn0 register match, the TOHn output level is inverted, 8-bit timer counter Hn is cleared, and the INTTMHn signal is output. <3> When the count value of 8-bit timer counter Hn and the set value of the CMPn1 register match, the TOHn output level is inverted. At this time, the value of 8-bit timer counter Hn is not cleared and the INTTMHn signal is not output. <4> When the TMHEn bit is cleared to 0 during 8-bit timer Hn operation, the INTTMHn signal and TOHn output becomes inactive. Remark n = 0, 1 392 User's Manual U16889EJ1V0UD CHAPTER 10 8-BIT TIMER H Figure 10-5. Operation Timing in PWM Output Mode (2/4) Operation when CMPn0 = FFH, CMPn1 = 00H Count clock 8-bit timer counter Hn count value 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H FFH 00H CMPn0 FFH CMPn1 00H TMHEn INTTMHn TOHn (TOLEVn = 0) Operation when CMPn0 = FFH, CMPn1 = FEH Count clock 8-bit timer counter Hn count value 00H 01H FEH FFH 00H 01H FEH FFH 00H 01H FEH FFH 00H CMPn0 FFH CMPn1 FEH TMHEn INTTMHn TOHn (TOLEVn = 0) Remark n = 0, 1 User's Manual U16889EJ1V0UD 393 CHAPTER 10 8-BIT TIMER H Figure 10-5. Operation Timing in PWM Output Mode (3/4) Operation when CMPn0 = 01H, CMPn1 = 00H Count clock 8-bit timer counter Hn count value 00H 01H 00H 01H 00H 00H 01H 00H 01H CMPn0 01H CMPn1 00H TMHEn INTTMHn TOHn (TOLEVn = 0) Remark n = 0, 1 394 User's Manual U16889EJ1V0UD CHAPTER 10 8-BIT TIMER H Figure 10-5. Operation Timing in PWM Output Mode (4/4) Operation based on CMPn1 transitions (CMPn1 = 01H 03H, CMPn0 = A5H) Count clock 8-bit timer counter Hn count value 00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H CMPn0 A5H CMPn1 01H 01H (03H) 03H <2> <2>' TMHEn INTTMHn TOHn (TOLEVn = 0) <1> <3> <4> <5> <6> <1> When the TMHEn bit is set to 1, counting starts. At this time, the TOHn output remains inactive (TOLEVn bit = 0). <2> The set value of the CMPn1 register can be changed during count operation. asynchronous to the count clock. <3> When the count value of 8-bit timer counter Hn and the set value of the CMPn0 register match, 8-bit timer counter Hn is cleared, the TOHn output becomes active, and the INTTMHn signal is generated. <4> Even if the value of the CMPn1 register is changed, that value is latched and not transferred to the register. When the count value of 8-bit timer counter Hn and the set value of the CMPn1 register prior to the change match, the changed value is transferred to the CMPn1 register and the value of the CMPn1 register is changed (<2>'). However, three or more count clocks are required from the time the value of the CMPn1 register is changed until it is transferred to the register. Even if a match signal is generated within three count clocks, the changed value cannot be transferred to the register. <5> When the count value of 8-bit timer counter Hn matches the changed set value of the CMPn1 register, the TOHn output becomes inactive. 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated. <6> When the TMHEn bit is cleared to 0 during 8-bit timer Hn operation, the INTTMHn signal and TOHn output become inactive. This operation is User's Manual U16889EJ1V0UD 395 CHAPTER 10 8-BIT TIMER H 10.4.3 Carrier generator mode operation The carrier clock generated by 8-bit timer Hn is output using the cycle set with 8-bit timer/event counter 5n. In the carrier generator mode, 8-bit timer/event counter 5n is used to control the extent to which the carrier pulse of 8-bit timer Hn is output, and the carrier pulse is output from the TOHn output. (1) Carrier generation In the carrier generator mode, the CMPn0 register generates a waveform with the low-level width of the carrier pulse and the CMPn1 register generates a waveform with the high-level width of the carrier pulse. During 8-bit timer Hn operation, the CMPn1 register can be rewritten, but rewriting of the CMPn0 register is prohibited. (2) Carrier output control Carrier output control is performed with the interrupt request signal (INTTM5n) of 8-bit timer/event counter 5n and the TMCYCn.NRZBn and TMCYCn.RMCn bits. The output relationships are as follows. RMCn Bit 0 0 1 1 NRZBn Bit 0 1 0 1 Output Low level output High level output Low level output Carrier pulse output Remark n = 0, 1 396 User's Manual U16889EJ1V0UD CHAPTER 10 8-BIT TIMER H To control carrier pulse output during count operation, the TMCYCn.NRZn and TMCYCn.NRZBn bits have a master and slave bit configuration. The NRZn bit is read-only while the NRZBn bit can be read and written. The INTTM5n signal is synchronized with the 8-bit timer Hn clock and output as the INTTM5Hn signal. The INTTM5Hn signal becomes the data transfer signal of the NRZn bit and the value of the NRZBn bit is transferred to the NRZn bit. The transfer timing from the NRZBn bit to the NRZn bit is as follows. Figure 10-6. Transfer Timing TMHEn 8-bit timer Hn count clock INTTM5n INTTM5Hn <1> NRZn 0 <2> NRZBn 1 0 1 1 0 RMCn <1> The INTTM5n signal is synchronized with the count clock of 8-bit timer Hn and is output as the INTTM5Hn signal. <2> The value of the NRZBn bit is transferred to the NRZn bit at the second clock from the rising edge of the INTTM5Hn signal. Cautions 1. Do not rewrite the NRZBn bit again until at least the second clock after it has been rewritten, or else transfer from the NRZBn bit to the NRZn bit is not guaranteed. 2. When using 8-bit timer/event counter 5n in the carrier generator mode, an interrupt occurs at the timing of <1>. An interrupt occurs at a different timing when it is used in other than the carrier generator mode. Remark n = 0, 1 User's Manual U16889EJ1V0UD 397 CHAPTER 10 8-BIT TIMER H (3) Usage method Any carrier clock can be output from the TOHn pin. <1> Set each register. Figure 10-7. Register Settings in Carrier Generator Mode * 8-bit timer H mode register n (TMHMDn) TMHEn TMHMDn 0 CKSHn2 CKSHn1 CKSHn0 TMMDn1 TMMDn0 TOLEVn 0/1 0/1 0/1 0 1 0/1 TOENn 1 Enables timer output Sets timer output level inversion Selects carrier generator mode Selects count clock (fCNT) Stops count operation * CMPn0 register: * CMPn1 register: * TMCYCn register: Compare value Compare value RMCn = 1 ... Remote control output enable bit NRZBn = 0/1 ... Carrier output enable bit * TCL5n, TMC5n registers: Refer to 9.3 Registers. Remark n = 0, 1 <2> When the TMHEn bit is set to 1, 8-bit timer Hn count operation starts. <3> When the TMC5n.TCE5n bit is set to 1, 8-bit timer/event counter 5n count operation starts. <4> After the count operation is enabled, the first compare register to be compared is the CMPn0 register. When the count value of 8-bit timer counter Hn and the set value of the CMPn0 register match, the INTTMHn signal is generated, 8-bit timer counter Hn is cleared, and at the same time, the register that is compared with 8-bit timer counter Hn changes from the CMPn0 register to the CMPn1 register. <5> When the count value of 8-bit timer counter Hn and the set value of the CMPn1 register match, the INTTMHn signal is generated, 8-bit timer counter Hn is cleared, and at the same time, the register that is compared with 8-bit timer counter Hn changes from the CMPn1 register to the CMPn0 register. <6> The carrier clock is obtained through the repetition of steps <4> and <5> above. <7> The INTTM5n signal is synchronized with 8-bit timer Hn and output as the INTTM5Hn signal. This signal becomes the data transfer signal of the NRZBn bit and the value of the NRZBn bit is transferred to the NRZn bit. <8> When the NRZn bit becomes high level, the carrier clock is output from the TOHn pin. <9> Any carrier clock can be obtained through the repetition of the above steps. To stop the count operation, clear the TMHEn bit to 0. 398 User's Manual U16889EJ1V0UD CHAPTER 10 8-BIT TIMER H Designating the set value of the CMPn0 register as (N), the set value of the CMPn1 register as (M), and the count clock frequency as fCNT, the carrier clock output cycle and duty are as follows. Carrier clock output cycle = (N + M + 2)/fCNT Duty = High level width: Carrier clock output width = (M + 1) : (N + M + 2) Caution Be sure to set the CMPn1 register when starting the timer count operation (TMHEn bit = 1) after the timer count operation was stopped (TMHEn bit = 0) (be sure to set again even if setting the same value to the CMPn1 register). (4) Timing chart The carrier output control timing is as follows. Cautions 1. Set the values of the CMPn0 and CMPn1 registers in the range of 01H to FFH. 2. In the carrier generator mode, three operating clocks (signal selected by the TMHMDn.CKSHn0 to TMHMDn.CKSHn2 bits) are required for actual transfer of the new value to the register after the CMPn1 register has been rewritten. 3. Be sure to perform the TMCYCn.RMCn bit setting before the start of the count operation. 4. When using the carrier generator mode, set the 8-bit timer Hn count clock frequency to six times the 8-bit timer/event counter 5n count clock frequency or higher. User's Manual U16889EJ1V0UD 399 CHAPTER 10 8-BIT TIMER H Figure 10-8. Carrier Generator Mode (1/3) Operation when CMPn0 = N, CMPn1 = N is set 8-bit timer Hn count clock 8-bit timer counter Hn count value 00H N 00H N 00H N 00H N 00H N 00H N CMPn0 CMPn1 TMHEn INTTMHn <1> <2> N N <3> <4> Carrier clock 8-bit timer 5n count clock TM5n count value CR5n TCE5n <5> 00H 01H L 00H 01H L 00H 01H L 00H 01H L 00H 01H L INTTM5n INTTM5Hn NRZBn NRZn Carrier clock TOHn 0 0 1 1 0 <6> 1 0 1 0 0 <7> <1> When the TMHEn bit = 0 and the TCE5n bit = 0, the operation of 8-bit timer Hn is stopped. <2> When the TMHEn bit is set to 1, 8-bit timer Hn starts counting. The carrier clock is maintained inactive at this time. <3> When the count value of 8-bit timer counter Hn and the set value of the CMPn0 register match, the first INTTMHn signal is generated, the carrier clock signal is inverted, and the register that is compared with 8-bit timer counter Hn changes from the CMPn0 register to the CMPn1 register. 8-bit timer counter Hn is cleared to 00H. <4> When the count value of 8-bit timer counter Hn and the set value of the CMPn1 register match, the INTTMHn signal is generated, the carrier clock signal is inverted, and the register that is compared with 8-bit timer counter Hn changes from the CMPn1 register to the CMPn0 register. 8-bit timer counter Hn is cleared to 00H. A carrier clock with a duty of 50% is generated through the repetition of steps <3> and <4>. <5> The INTTM5n signal is synchronized with 8-bit timer Hn and output as the INTTM5Hn signal. <6> The INTTM5Hn signal becomes the data transfer signal of the NRZBn bit, and the value of the NRZBn bit is transferred to the NRZn bit. <7> The TOHn output is made low level by clearing the NRZn bit = 0. Remark n = 0, 1 User's Manual U16889EJ1V0UD 400 CHAPTER 10 8-BIT TIMER H Figure 10-8. Carrier Generator Mode (2/3) Operation when CMPn0 = N, CMPn1 = M is set 8-bit timer Hn count clock 8-bit timer counter Hn count value CMPn0 CMPn1 TMHEn INTTMHn <1> <2> Carrier clock 8-bit timer 5n count clock TM5n count value CR5n TCE5n <5> INTTM5n INTTM5Hn NRZBn NRZn Carrier clock <6> TOHn <7> 0 0 1 1 0 0 1 1 0 0 00H 01H L 00H 01H L 00H 01H L L 00H 01H L 00H 01H 00H N 00H 01H M 00H N N 00H 01H M 00H N 00H M <3> <4> <1> When the TMHEn bit = 0 and the TCE5n bit = 0, the operation of 8-bit timer Hn is stopped. <2> When the TMHEn bit is set to 1, 8-bit timer Hn starts counting. The carrier clock is maintained inactive at this time. <3> When the count value of 8-bit timer counter Hn and the set value of the CMPn0 register match, the first INTTMHn signal is generated, the carrier clock signal is inverted, and the register that is compared with 8-bit timer counter Hn changes from the CMPn0 register to the CMPn1 register. 8-bit timer counter Hn is cleared to 00H. <4> When the count value of 8-bit timer counter Hn and the set value of the CMPn1 register match, the INTTMHn signal is generated, the carrier clock signal is inverted, and the register that is compared with 8-bit timer counter Hn changes from the CMPn1 register to the CMPn0 register. 8-bit timer counter Hn is cleared to 00H. A carrier clock with a fixed duty (other than 50%) is generated through the repetition of steps <3> and <4>. <5> The INTTM5n signal is generated. This signal is synchronized with 8-bit timer Hn and output as the INTTM5Hn signal. <6> The carrier is output from the rising edge of the first carrier clock by setting the NRZn bit = 1. <7> By setting the NRZn bit = 0, the TOHn output is also maintained high level while the carrier clock is high level, and does not change to low level (the high level width of the carrier waveform is guaranteed through steps <6> and <7>). Remark n = 0, 1 User's Manual U16889EJ1V0UD 401 CHAPTER 10 8-BIT TIMER H Figure 10-8. Carrier Generator Mode (3/3) Operation based on CMPn1 transitions 8-bit timer Hn count clock 8-bit timer counter Hn count value 00H 01H N 00H 01H M 00H N 00H 01H L 00H CMPn0 <3> CMPn1 M M (L) N <3>' L TMHEn INTTMHn <2> Carrier clock <1> <4> <5> <1> When the TMHEn bit is set to 1, counting starts. The carrier clock is maintained inactive at this time. <2> When the count value of 8-bit timer counter Hn and the set value of the CMPn0 register match, 8-bit timer counter Hn is cleared to 00H and the INTTMHn signal is output. <3> The CMPn1 register can be rewritten during 8-bit timer Hn operation, but the changed value (L) is latched. The value of the CMPn1 register is changed when the count value of 8-bit timer counter Hn and the value of the CMPn1 register prior to the change (M) match (<3>'). <4> When the count value of 8-bit timer counter Hn and the value (M) of the CMPn1 register match, the INTTMHn signal is output, the carrier signal is inverted, and 8-bit timer counter Hn is cleared to 00H. <5> The timing at which the count value of 8-bit timer counter Hn and the value of the CMPn1 register match again is the changed value (L). Remark n = 0, 1 402 User's Manual U16889EJ1V0UD CHAPTER 11 INTERVAL TIMER, WATCH TIMER The V850ES/KJ1 includes interval timer BRG and a watch timer. Interval timer BRG can also be used as the source clock of the watch timer. The watch timer can also be used as interval timer WT. Two interval timer channels and one watch timer channel can be used at the same time. 11.1 Interval Timer BRG 11.1.1 Functions Interval timer BRG has the following functions. * Interval timer BRG: An interrupt request signal (INTBRG) is generated at a specified interval. * Generation of count clock for watch timer: When the main clock is used as the count clock for the watch timer, a count clock (fBRG) is generated. 11.1.2 Configuration The following shows the block diagram of interval timer BRG. Figure 11-1. Block Diagram of Interval Timer BRG fX Clock control 3-bit prescaler fX/8 fX/4 fX/2 fX Selector fBGCS Clear INTBRG 8-bit counter Match Output fBRG control Count clock for watch timer 2 PRSCM register BGCE TODIS BGCS1 BGCS0 PRSM register Internal bus Remark fX: fBGCS: fBRG: Main clock oscillation frequency Interval timer BRG count clock frequency Watch timer count clock frequency INTBRG: Interval timer BRG interrupt request signal User's Manual U16889EJ1V0UD 403 CHAPTER 11 INTERVAL TIMER, WATCH TIMER (1) Clock control The clock control controls supply/stop of the operation clock of interval timer BRG. (2) 3-bit prescaler The 3-bit prescaler divides fX to generate fX/2, fX/4, and fX/8. (3) Selector The selector selects the count clock (fBGCS) for interval timer BRG from fX, fX/2, fX/4, and fX/8. (4) 8-bit counter The 8-bit counter counts the count clock (fBGCS). (5) Output control The output control controls supply of the count clock (fBRG) for the watch timer. (6) PRSCM register The PRSCM register is an 8-bit compare register that sets the interval time. (7) PRSM register The PRSM register controls the operation of interval timer BRG, the selector, and clock supply to the watch timer. 404 User's Manual U16889EJ1V0UD CHAPTER 11 INTERVAL TIMER, WATCH TIMER 11.1.3 Registers Interval timer BRG includes the following registers. (1) Interval timer BRG mode register (PRSM) PRSM controls the operation of interval timer BRG, selection of count clock, and clock supply to the watch timer. This register can be read or written in 8-bit or 1-bit units. After reset, PRSM is cleared to 00H. After reset: 00H R/W Address: FFFFF8B0H <> PRSM 0 0 0 BGCE 0 TODIS BGCS1 BGCS0 BGCE 0 1 Control of interval timer operation Operation stopped, 8-bit counter cleared to 01H Operate TODIS 0 1 Control of clock supply for watch timer Clock for watch timer not supplied Clock for watch timer supplied BGCS1 BGCS0 Selection of input clock (fBGCS)Note 10 MHz 5 MHz 200 ns 400 ns 800 ns 1.6 s 4 MHz 250 ns 500 ns 1 s 2 s 0 0 1 1 0 1 0 1 fX fX/2 fX/4 fX/8 100 ns 200 ns 400 ns 800 ns Note Set these bits so that the following conditions are satisfied. VDD = 4.0 to 5.5 V: fBGCS 10 MHz VDD = 2.7 to 4.0 V: fBGCS 5 MHz Cautions 1. Do not change the values of the TODIS, BGCS1, and BGCS0 bits while interval timer BRG is operating (BGCE bit = 1). Set the TODIS, BGCS1, and BGCS0 bits before setting (1) the BGCE bit. 2. When the BGCE bit is cleared (to 0), the 8-bit counter is cleared. User's Manual U16889EJ1V0UD 405 CHAPTER 11 INTERVAL TIMER, WATCH TIMER (2) Interval timer BRG compare register (PRSCM) PRSCM is an 8-bit compare register. This register can be read or written in 8-bit units. After reset, PRSCM is cleared to 00H. After reset: 00H R/W Address: FFFFF8B1H PRSCM PRSCM7 PRSCM6 PRSCM5 PRSCM4 PRSCM3 PRSCM2 PRSCM1 PRSCM0 Caution Do not rewrite the PRSCM register while interval timer BRG is operating (PRSM.BGCE bit = 1). before setting (1) the BGCE bit. Set the PRSCM register 406 User's Manual U16889EJ1V0UD CHAPTER 11 INTERVAL TIMER, WATCH TIMER 11.1.4 Operation (1) Operation of interval timer BRG Set the count clock by using the BGCS1 and BGCS0 bits of PRSM and the 8-bit compare value by using the PRSCM register. When the PRSM.BGCE bit is set (1), interval timer BRG starts operating. Each time the count value of the 8-bit counter and the set value in the PRSCM register match, an interrupt request signal (INTBRG) is generated. At the same time, the 8-bit counter is cleared to 00H and counting is continued. The interval time can be obtained from the following equation. Interval time = 2m x N/fX Remark m: Division value (set values of BGCS1 and BGCS0 bits) = 0 to 3 N: Set value in PRSCM register = 1 to 256 (when the set value in the PRSCM register is 00H, N = 256) fX: Main clock oscillation frequency (2) Count clock supply for watch timer Set the count clock by using the BGCS1 and BGCS0 bits of PRSM and the 8-bit compare value by using the PRSCM register, so that the count clock frequency (fBRG) of the watch timer is 32.768 kHz. Set (1) the PRSM.TODIS bit at the same time. When the PRSM.BGCE bit is set (1), fBRG is supplied to the watch timer. fBRG is obtained from the following equation. fBRG = fX/(2m+ 1 x N) To set fBRG to 32.768 kHz, perform the following calculation to set the BGCS1 and BGCS0 bits and the PRSCM register. <1> Set N = fX/65,536 (round off the decimal) to set m = 0. <2> If N is even, N = N/2 and m = m + 1 <3> Repeat step <2> until N is even or m = 3 <4> Set N to the PRSCM register and m to the BGCS1 and BGCS0 bits. Example: When fX = 4.00 MHz <1> N = 4,000,000/65,536 = 61 (round off the decimal), m = 0 <2>, <3> Since N is odd, the values remain as N = 61, m = 0 <4> The set value in the PRSCM register: 3DH (61), the set values in the BGCS1 and BGCS0 bits: 00 Remark m: Divided value (set value in the BGCS1 and BGCS0 bits) = 0 to 3 N: Set value in PRSCM register = 1 to 256 (when the set value in the PRSCM register is 00H, N = 256) fX: Main clock oscillation frequency User's Manual U16889EJ1V0UD 407 CHAPTER 11 INTERVAL TIMER, WATCH TIMER 11.2 Watch Timer 11.2.1 Functions The watch timer has the following functions. * Watch timer: An interrupt request signal (INTWT) is generated at time intervals of 0.5 or 0.25 seconds by using the main clock or subclock. * Interval timer: An interrupt request signal (INTWTI) is generated at the preset time interval. The watch timer and interval timer functions can be used at the same time. 11.2.2 Configuration The following shows the block diagram of the watch timer. Figure 11-2. Block Diagram of Watch Timer Clear Selector Selector 5-bit counter Selector INTWT fBRG fXT fW 11-bit prescaler fW/24 fW/25 fW/26 fW/27 fW/28 fW/210 fW/211 fW/29 Clear Selector INTWTI 3 WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM0 Watch timer operation mode register (WTM) Internal bus Remark fBRG: fXT: fW: INTWT: Frequency of count clock from interval timer BRG Subclock frequency Watch timer clock frequency Watch timer interrupt request signal INTWTI: Interval timer interrupt request signal 408 User's Manual U16889EJ1V0UD CHAPTER 11 INTERVAL TIMER, WATCH TIMER (1) 11-bit prescaler The 11-bit prescaler generates a clock of fW/24 to fW/211 by dividing fW. (2) 5-bit counter The 5-bit counter generates the watch timer interrupt request signal (INTWT) at intervals of 24/fW, 25/fW, 213/fW, or 214/fW by counting fW or fW/29. (3) Selectors The watch timer has the following four selectors. * Selector that selects the main clock (the clock from interval timer BRG (fBRG)) or the subclock (fXT) as the clock for the watch timer. * Selector that selects fW or fW/29 as the count clock frequency of the 5-bit counter * Selector that selects 24/fW or 213/fW, or 25/fW or 214/fW as the INTWT signal generation time interval. * Selector that selects the generation time interval of the interval timer WT interrupt request signal (INTWTI) from 24/fW to 211/fW. (4) 8-bit counter The 8-bit counter counts the count clock (fBGCS). (5) WTM register The WTM register is an 8-bit register that controls the operation of the watch timer/interval timer WT and sets the interval of interrupt request signal generation. 11.2.3 Registers The watch timer includes the following register. (1) Watch timer operation mode register (WTM) This register enables or disables the count clock and operation of the watch timer, sets the interval time of the 11-bit prescaler, controls the operation of the 5-bit counter, and sets the timer of watch timer interrupt request signal (INTWT) generation. The WTM register can be read or written in 8-bit or 1-bit units. After reset, WTM is cleared to 00H. User's Manual U16889EJ1V0UD 409 CHAPTER 11 INTERVAL TIMER, WATCH TIMER After reset: 00H R/W Address: FFFFF680H <> <> WTM0 WTM WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 WTM6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 WTM5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WTM4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Selection of interval time of prescaler 24/fW (488 s: fW = fXT) 25/fW (977 s: fW = fXT) 26/fW (1.95 ms: fW = fXT) 27/fW (3.91 ms: fW = fXT) 28/fW (7.81 ms: fW = fXT) 29/fW (15.6 ms: fW = fXT) 210/fW (31.3 ms: fW = fXT) 211/fW (62.5 ms: fW = fXT) 24/fW (488 s: fW = fBRG) 25/fW (977 s: fW = fBRG) 26/fW (1.95 ms: fW = fBRG) 27/fW (3.91 ms: fW = fBRG) 28/fW (7.81 ms: fW = fBRG) 29/fW (15.6 ms: fW = fBRG) 210/fW (31.3 ms: fW = fBRG) 211/fW (62.5 ms: fW = fBRG) WTM7 0 0 0 0 1 1 1 1 WTM3 0 0 1 1 0 0 1 1 WTM2 0 1 0 1 0 1 0 1 Selection of set time of watch flag 214/fW (0.5 s: fW = fXT) 213/fW (0.25 s: fW = fXT) 25/fW (977 s: fW = fXT) 24/fW (488 s: fW = fXT) 214/fW (0.5 s: fW = fBRG) 213/fW (0.25 s: fW = fBRG) 25/fW (977 s: fW = fBRG) 24/fW (488 s: fW = fBRG) WTM1 0 1 Control of 5-bit counter operation Clear after operation stops Start WTM0 0 1 Watch timer operation enable Stop operation (clear both prescaler and 5-bit counter) Enable operation Caution Rewrite the WTM2 to WTM7 bits while both the WTM0 and WTM1 bits are 0. Remarks 1. fW: Watch timer clock frequency 2. Values in parentheses apply when fW = 32.768 kHz 410 User's Manual U16889EJ1V0UD CHAPTER 11 INTERVAL TIMER, WATCH TIMER 11.2.4 Operation (1) Operation as watch timer The watch timer generates an interrupt request at fixed time intervals. The watch timer operates using time intervals of 0.25 or 0.5 seconds with the subclock (32.768 kHz). The count operation starts when the WTM.WTM0 and WTM.WTM1 bits are set to 11. When these bits are cleared to 00, the 10-bit prescaler and 5-bit counter are cleared and the count operation stops. The 5-bit counter can be cleared to synchronize the time by clearing the WTM1 bit to 0 when the watch timer and interval timer WT operate simultaneously. At this time, an error of up to 15.6 ms may occur in the watch timer, but interval timer WT is not affected. (2) Operation as interval timer The watch timer can also be used as an interval timer that repeatedly generates an interrupt request signal (INTWTI) at intervals specified by a count value set in advance. The interval time can be selected by the WTM.WTM4 to WTM.WTM7 bits. Table 11-1. Interval Time of Interval Timer WTM7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 WTM6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 WTM5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WTM4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 x 1/fW 4 Interval Time 488 s (operating at fW = fXT = 32.768 kHz) 977 s (operating at fW = fXT = 32.768 kHz) 1.95 ms (operating at fW = fXT = 32.768 kHz) 3.91 ms (operating at fW = fXT = 32.768 kHz) 7.81 ms (operating at fW = fXT = 32.768 kHz) 15.6 ms (operating at fW = fXT = 32.768 kHz) 31.3 ms (operating at fW = fXT = 32.768 kHz) 62.5 ms (operating at fW = fXT = 32.768 kHz) 488 s (operating at fW = fBRG = 32.768 kHz) 977 s (operating at fW = fBRG = 32.768 kHz) 1.95 ms (operating at fW = fBRG = 32.768 kHz) 3.91 ms (operating at fW = fBRG = 32.768 kHz) 7.81 ms (operating at fW = fBRG = 32.768 kHz) 15.6 ms (operating at fW = fBRG = 32.768 kHz) 31.3 ms (operating at fW = fBRG = 32.768 kHz) 62.5 ms (operating at fW = fBRG = 32.768 kHz) 2 x 1/fW 5 2 x 1/fW 6 2 x 1/fW 7 2 x 1/fW 8 2 x 1/fW 9 2 x 1/fW 10 2 x 1/fW 11 2 x 1/fW 4 2 x 1/fW 5 2 x 1/fW 6 2 x 1/fW 7 2 x 1/fW 8 2 x 1/fW 9 2 x 1/fW 10 2 x 1/fW 11 Remark fW: Watch timer clock frequency User's Manual U16889EJ1V0UD 411 CHAPTER 11 INTERVAL TIMER, WATCH TIMER Figure 11-3. Operation Timing of Watch Timer/Interval Timer 5-bit counter 0H Start Count clock fW or fW/29 Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTI Interval time (T) nT Interval time (T) nT Overflow Overflow Remarks 1. Assuming that the interrupt time of the watch timer is set to 0.5 seconds. 2. fW: Watch timer clock frequency Values in parentheses apply when count clock fW = 32.768 kHz. n: Number of interval timer WT operations 11.3 Cautions (1) Operation as watch timer Some time is required before the first watch timer interrupt request (INTWT) is generated after operation is enabled (WTM.WTM1 and WTM.WTM0 bits = 11). Figure 11-4. Example of Generation of Watch Timer Interrupt Request (INTWT) (When Interrupt Period = 0.5 s) It takes 0.515625 (max.) seconds for the first INTWT to be generated (29 x 1/32768 = 0.015625 (max.) s longer). INTWT is then generated every 0.5 seconds. WTM0, WTM1 0.515625 s 0.5 s 0.5 s INTWT 412 User's Manual U16889EJ1V0UD CHAPTER 11 INTERVAL TIMER, WATCH TIMER (2) When watch timer and interval timer BRG operate simultaneously When using the subclock as the count clock for the watch timer, the interval time of interval timer BRG can be set to any value. Changing the interval time does not affect the watch timer (before changing the interval time, stop operation). When using the main clock as the count clock for the watch timer, set the interval time of interval timer BRG to approximately 65,536 Hz. Do not change this value. (3) When interval timer BRG and interval timer WT operate simultaneously When using the subclock as the count clock for interval timer WT, the interval times of interval timers BRG and WT can be set to any values. They can also be changed later (before changing the value, stop operation). When using the main clock as the count clock for interval timer WT, the interval time of interval timer BRG can be set to any value, but cannot be changed later (it can be changed only when interval timer WT stops operation). The interval time of interval timer WT can be set to x 25 to x 212 of the set value of interval timer BRG. It can also be changed later. (4) When watch timer and interval timer WT operate simultaneously The interval time of interval timer WT can be set to a value between 488 s and 62.5 ms. It cannot be changed later. Do not stop interval timer WT (clear (0) the WTM.WTM0 bit) while the watch timer is operating. If the WTM0 bit is set (1) after it had been cleared (0), the watch timer will have a discrepancy of up to 0.5 or 0.25 seconds. (5) When watch timer, interval timer BRG, and interval timer WT operate simultaneously When using the subclock as the count clock for the watch timer, the interval times of interval timers BRG and WT can be set to any values. The interval time of interval timer BRG can be changed later (before changing the value, stop operation). When using the main clock as the count clock for the watch timer, set the interval time of interval timer BRG to approximately 65,536 Hz. It cannot be changed later. The interval time of interval timer WT can be set to a value between 488 s and 62.5 ms. It cannot be changed later. Do not stop interval timer BRG (clear (0) the PRSM.BGCE bit) or interval timer WT (clear (0) the WTM.WTM0 bit) while the watch timer is operating. User's Manual U16889EJ1V0UD 413 CHAPTER 12 WATCHDOG TIMER FUNCTIONS 12.1 Watchdog Timer 1 12.1.1 Functions Watchdog timer 1 has the following operation modes. * Watchdog timer * Interval timer The following functions are realized from the above-listed operation modes. * Generation of non-maskable interrupt request signal (INTWDT1) upon overflow of watchdog timer 1Note * Generation of system reset signal (WDTRES1) upon overflow of watchdog timer 1 * Generation of maskable interrupt request signal (INTWDTM1) upon overflow of interval timer Note For non-maskable interrupt servicing due to non-maskable interrupt request signal (INTWDT1, INTWDT2), refer to 20.10 Cautions. Remark Select whether to use watchdog timer 1 in the watchdog timer 1 mode or the interval timer mode with the WDTM1 register. 414 User's Manual U16889EJ1V0UD CHAPTER 12 WATCHDOG TIMER FUNCTIONS Figure 12-1. Block Diagram of Watchdog Timer 1 Internal bus Watchdog timer mode register 1 (WDTM1) RUN1 WDTM14 WDTM13 Watchdog timer clock selection register (WDCS) WDCS2 WDCS1 WDCS0 2 Clear fXW Prescaler fXW/221 fXW/219 fXW/218 Selector 3 fXW/217 fXW/216 fXW/2 fXW/2 15 14 INTWDTM1 Output controller INTWDT1 WDTRES1 fXW/213 Remark INTWDTM1: Request signal for maskable interrupt through watchdog timer 1 overflow INTWDT1: fXW = fX: Request signal for non-maskable interrupt through watchdog timer 1 overflow Watchdog timer 1 clock frequency WDTRES1: Reset signal through watchdog timer 1 overflow User's Manual U16889EJ1V0UD 415 CHAPTER 12 WATCHDOG TIMER FUNCTIONS 12.1.2 Configuration Watchdog timer 1 consists of the following hardware. Table 12-1. Configuration of Watchdog Timer 1 Item Control register Configuration Watchdog timer clock selection register (WDCS) Watchdog timer mode register 1 (WDTM1) 12.1.3 Registers The registers that control watchdog timer 1 are as follows. * Watchdog timer clock selection register (WDCS) * Watchdog timer mode register 1 (WDTM1) (1) Watchdog timer clock selection register (WDCS) This register sets the overflow time of watchdog timer 1 and the interval timer. The WDCS register can be read or written in 8-bit or 1-bit units. After reset, WDCS is cleared to 00H. After reset: 00H R/W Address: FFFFF6C1H WDCS 0 0 0 0 0 WDCS2 WDCS1 WDCS0 WDCS2 WDCS1 WDCS0 Overflow time of watchdog timer 1/interval timer fXW 4 MHz 5 MHz 1.638 ms 3.277 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 419.4 ms 10 MHz 0.819 ms 1.638 ms 3.277 ms 6.554 ms 13.11 ms 26.2 ms 52.43 ms 209.7 ms 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 2 /fXW 2 /fXW 2 /fXW 216/fXW 2 /fXW 2 /fXW 2 /fXW 221/fXW 19 18 17 15 14 13 2.048 ms 4.096 ms 8.192 ms 16.38 ms 32.77 ms 65.54 ms 131.1 ms 524.3 ms Remark fXW = fX: Watchdog timer 1 clock frequency 416 User's Manual U16889EJ1V0UD CHAPTER 12 WATCHDOG TIMER FUNCTIONS (2) Watchdog timer mode register 1 (WDTM1) This register sets the watchdog timer 1 operation mode and enables/disables count operations. This register is a special register that can be written only in a special sequence (refer to 3.4.7 Special registers). The WDTM1 register can be read or written in 8-bit or 1-bit units. After reset, WDTM1 is cleared to 00H. Caution When the main clock is stopped and the CPU is operating on the subclock, do not access the WDTM1 register using an access method that causes a wait. For details, refer to 3.4.8 (2). After reset: 00H <> WDTM1 RUN1 R/W Address: FFFFF6C2H 0 0 WDTM14 WDTM13 0 0 0 RUN1 0 1 Selection of operation mode of watchdog timer 1Note 1 Stop counting Clear counter and start counting WDTM14 WDTM13 Selection of operation mode of watchdog timer 1Note 2 0 0 1 0 1 0 Interval timer mode (Upon overflow, maskable interrupt INTWDTM1 is generated.) Watchdog timer mode 1Note 3 (Upon overflow, non-maskable interrupt INTWDT1 is generated.) Watchdog timer mode 2 (Upon overflow, reset operation WDTRES1 is started.) 1 1 Notes 1. Once the RUN1 bit is set (to 1), it cannot be cleared (to 0) by software. Therefore, when counting is started, it cannot be stopped except reset. 2. Once the WDTM13 and WDTM14 bits are set (to 1), they cannot be cleared (to 0) by software and can be cleared only by reset. 3. For non-maskable interrupt servicing due to non-maskable interrupt request signal (INTWDT1), refer to 20.10 Cautions. User's Manual U16889EJ1V0UD 417 CHAPTER 12 WATCHDOG TIMER FUNCTIONS 12.1.4 Operation (1) Operation as watchdog timer 1 Watchdog timer 1 operation to detect a program loop is selected by setting the WDTM1.WDTM14 bit to 1. The count clock (program loop detection time interval) of watchdog timer 1 can be selected using the WDCS.WDCS0 to WDCS.WDCS2 bits. The count operation is started by setting the WDTM1.RUN1 bit to 1. When, after the count operation is started, the RUN1 bit is again set to 1 within the set program loop detection time interval, watchdog timer 1 is cleared and the count operation starts again. If the program loop detection time is exceeded without RUN1 bit being set to 1, reset signal (WDTRES1) through the value of the WDTM1.WDTM13 bit or a non-maskable interrupt request signal (INTWDT1) is generated. The count operation of watchdog timer 1 stops in the STOP mode and IDLE mode. Set the RUN1 bit to 1 before the STOP mode or IDLE mode is entered in order to clear watchdog timer 1. Because watchdog timer 1 operates in the HALT mode, make sure that an overflow will not occur during HALT. Cautions 1. When the subclock is selected for the CPU clock, the count operation of watchdog timer 1 is stopped (the value of watchdog timer 1 is maintained). 2. For non-maskable interrupt servicing due to the INTWDT1 signal, refer to 20.10 Cautions. Table 12-2. Program Loop Detection Time of Watchdog Timer 1 Clock Program Loop Detection Time fXW = 4 MHz 2 /fXW 2 /fXW 2 /fXW 2 /fXW 2 /fXW 2 /fXW 2 /fXW 2 /fXW 21 19 18 17 16 15 14 13 fXW = 5 MHz 1.638 ms 3.277 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 419.4 ms fXW = 10 MHz 0.819 ms 1.683 ms 3.277 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 209.7 ms 2.048 ms 4.096 ms 8.192 ms 16.38 ms 32.77 ms 65.54 ms 131.1 ms 524.3 ms Remark fXW = fX: Watchdog timer 1 clock frequency 418 User's Manual U16889EJ1V0UD CHAPTER 12 WATCHDOG TIMER FUNCTIONS (2) Operation as interval timer Watchdog timer 1 can be made to operate as an interval timer that repeatedly generates interrupts using the count value set in advance as the interval, by clearing the WDTM1.WDTM14 bit to 0. When watchdog timer 1 operates as an interval timer, the interrupt mask flag (WDTMK) and priority specification flags (WDTPR0 to WDTPR2) of the WDTIC register are valid and maskable interrupt request signals (INTWDTM1) can be generated. The default priority of the INTWDTM1 signal is set to the highest level among the maskable interrupt request signals. The interval timer continues to operate in the HALT mode, but it stops operating in the STOP mode and the IDLE mode. Cautions 1. Once the WDTM14 bit is set to 1 (thereby selecting the watchdog timer 1 mode), the interval timer mode is not entered as long as reset is not performed. 2. When the subclock is selected for the CPU clock, the count operation of the watchdog timer 1 stops (the value of the watchdog timer is maintained). Table 12-3. Interval Time of Interval Timer Clock fXW = 4 MHz 2 /fXW 2 /fXW 2 /fXW 2 /fXW 2 /fXW 2 /fXW 2 /fXW 2 /fXW 21 19 18 17 16 15 14 13 Interval Time fXW = 5 MHz 1.638 ms 3.277 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 419.4 ms fXW = 10 MHz 0.819 ms 1.638 ms 3.277 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 209.7 ms 2.048 ms 4.096 ms 8.192 ms 16.38 ms 32.77 ms 65.54 ms 131.1 ms 524.3 ms Remark fXW = fX: Watchdog timer 1 clock frequency User's Manual U16889EJ1V0UD 419 CHAPTER 12 WATCHDOG TIMER FUNCTIONS 12.2 Watchdog Timer 2 12.2.1 Functions Watchdog timer 2 has the following functions. * Default start watchdog timerNote 1 Reset mode: Reset operation upon overflow of watchdog timer 2 (generation of WDTRES2 signal) Non-maskable interrupt request mode: NMI operation upon overflow of watchdog timer 2 (generation of INTWDT2 signal)Note 2 * Input selectable from main clock and subclock as the source clock Notes 1. Watchdog timer 2 automatically starts in the reset mode following reset release. When watchdog timer 2 is not used, either stop its operation before reset is executed through this function, or clear once watchdog timer 2 and stop it within the next interval time. Also, write to the WDTM2 register for verification purposes only once, even if the default settings (reset mode, interval time: fXX/225) need not be changed. 2. For non-maskable interrupt servicing due to a non-maskable interrupt request signal (INTWDT2), refer to 20.10 Cautions. Figure 12-2. Block Diagram of Watchdog Timer 2 fXX/29 fXT Clock input controller 2 fXX/218 to fXX/225 16-bit Selector counter or fXT/29 to fXT/216 Clear 3 Output controller INTWDT2 WDTRES2 (internal reset signal) 3 Watchdog timer enable register (WDTE) 0 WDM21 WDM20 WDCS24 WDCS23 WDCS22 WDCS21 WDCS20 Watchdog timer mode register 2 (WDTM2) Internal bus Remark fXX: fXT: INTWDT2: Main clock frequency Subclock frequency Non-maskable interrupt request signal through watchdog timer 2 WDTRES2: Watchdog timer 2 reset signal 420 User's Manual U16889EJ1V0UD CHAPTER 12 WATCHDOG TIMER FUNCTIONS 12.2.2 Configuration Watchdog timer 2 consists of the following hardware. Table 12-4. Configuration of Watchdog Timer 2 Item Control register Configuration Watchdog timer mode register 2 (WDTM2) Watchdog timer enable register (WDTE) 12.2.3 Registers (1) Watchdog timer mode register 2 (WDTM2) This register sets the overflow time and operation clock of watchdog timer 2. The WDTM2 register can be read or written in 8-bit units. This register can be read any number of times, but it can be written only once following reset release. After reset, WDTM2 is set to 67H. Caution When the main clock is stopped and the CPU is operating on the subclock, do not access the WDTM2 register using an access method that causes a wait. For details, refer to 3.4.8 (2). After reset: 67H R/W Address: FFFFF6D0H WDTM2 0 WDM21 WDM20 WDCS24 WDCS23 WDCS22 WDCS21 WDCS20 WDM21 0 0 1 WDM20 0 1 - Selection of operation mode of watchdog timer 2 Stops operation Non-maskable interrupt request mode (generation of INTWDT2) Reset mode (generation of WDTRES2) Cautions 1. To stop the operation of watchdog timer 2, write "1FH" to the WDTM2 register. 2. For details about bits WDCS0 to WDCS4, refer to Table 12-5 Watchdog Timer 2 Clock Selection. 3. If the WDTM2 register is written twice after a reset, an overflow signal is forcibly output. User's Manual U16889EJ1V0UD 421 CHAPTER 12 WATCHDOG TIMER FUNCTIONS Table 12-5. Watchdog Timer 2 Clock Selection WDCS24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 WDCS23 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x WDCS22 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 x WDCS21 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 x WDCS20 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 x Selected Clock 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXX 2 /fXT 2 /fXT 2 /fXT 2 /fXT 2 /fXT 2 /fXT 2 /fXT 2 /fXT 16 15 14 13 12 11 10 9 25 24 23 22 21 20 19 18 fXX = 20 MHz 13.1 ms 26.2 ms 52.4 ms 104.9 ms 209.7 ms 419.4 ms 838.9 ms 1677.7 ms fXX = 16 MHz 16.4 ms 32.8 ms 65.5 ms 131.1 ms 262.1 ms 524.3 ms 1048.6 ms 2097.2 ms fXX = 10 MHz 26.2 ms 52.4 ms 104.9 ms 209.7 ms 419.4 ms 838.9 ms 1677.7 ms 3355.4 ms 15.625 ms (fXT = 32.768 kHz) 31.25 ms (fXT = 32.768 kHz) 62.5 ms (fXT = 32.768 kHz) 125 ms (fXT = 32.768 kHz) 250 ms (fXT = 32.768 kHz) 500 ms (fXT = 32.768 kHz) 1000 ms (fXT = 32.768 kHz) 2000 ms (fXT = 32.768 kHz) Operation stopped (2) Watchdog timer enable register (WDTE) The counter of watchdog timer 2 is cleared and counting restarted by writing "ACH" to the WDTE register. The WDTE register can be read or written in 8-bit units. After reset, WDTE is set to 9AH. After reset: 9AH R/W Address: FFFFF6D1H WDTE Cautions 1. When a value other than "ACH" is written to the WDTE register, an overflow signal is forcibly output. 2. When a 1-bit memory manipulation instruction is executed for the WDTE register, an overflow signal is forcibly output. 3. The read value of the WDTE register is always "9AH" (value that differs from written value "ACH"). 422 User's Manual U16889EJ1V0UD CHAPTER 12 WATCHDOG TIMER FUNCTIONS 12.2.4 Operation Watchdog timer 2 automatically starts in the reset mode following reset release. The WDTM2 register can be written to only once following reset through byte access. To use watchdog timer 2, write the operation mode and the interval time to the WDTM2 register using 8-bit memory manipulation instructions. After this is done, the operation of watchdog timer 2 cannot be stopped. The watchdog timer 2 program loop detection time interval can be selected by the WDTM2.WDCS24 to WDTM2.WDCS20 bits. Writing ACH to the WDTE register clears the counter of watchdog timer 2 and starts the count operation again. After the count operation starts, write ACH to the WDTE register within the set program loop detection time interval. If the program loop detection time is exceeded without ACH being written to the WDTE register, a reset signal (WDTRES2) or non-maskable interrupt request signal (INTWDT2) is generated depending on the set value of the WDTM2.WDM21 and WDTM2.WDM20 bits. To not use watchdog timer 2, write 1FH to the WDTM2 register. For non-maskable interrupt servicing when the non-maskable interrupt request mode is set, refer to 20.10 Cautions. If the main clock is selected as the source clock of watchdog timer 2, the watchdog timer stops operation in the IDLE/STOP mode. Therefore, clear watchdog timer 2 by writing ACH to the WDTE register before the IDLE/STOP mode is set. Because watchdog timer 2 operates in the HALT mode or when the subclock is selected as its source clock in the IDLE/STOP mode, exercise care that the timer does not overflow in the HALT mode. User's Manual U16889EJ1V0UD 423 CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.1 Function The real-time output function (RTO) transfers preset data to the RTBLn and RTBHn registers, and then transfers this data with hardware to an external device via the real-time output latches, upon occurrence of a timer interrupt. The pins through which the data is output to an external device constitute a port called a real-time output port. Because RTO can output signal without jitter, it is suitable for controlling a stepping motor. In the V850ES/KJ1, two 6-bit real-time output port channels are provided. The real-time output port can be set in the port mode or real-time output port mode in 1-bit units. The block diagram of RTO is shown below. Figure 13-1. Block Diagram of RTO Internal bus Real-time buffer register nH (RTBHn) Real-time output latch nH 2 RTPOUTn4, RTPOUTn5 Real-time buffer register nL (RTBLn) Real-time output latch nL 4 RTPOUTn0 to RTPOUTn3 INTTM000 (INTTM020Note) Transfer trigger (H) INTTM50 INTTM51 Selector Transfer trigger (L) 2 4 RTPOEn RTPEGn BYTEn EXTRn RTPMn5 RTPMn4 RTPMn3 RTPMn2 RTPMn1 RTPMn0 Real-time output port control register n (RTPCn) Real-time output port mode register n (RTPMn) Note When n = 0, INTTM000 When n = 1, INTTM020 424 User's Manual U16889EJ1V0UD CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.2 Configuration RTO consists of the following hardware. Table 13-1. Configuration of RTO Item Registers Control registers Configuration Real-time output buffer register n (RTBLn, RTBHn) Real-time output port mode register n (RTPMn) Real-time output port control register n (RTPCn) (1) Real-time output buffer register n (RTBLn, RTBHn) RTBLn and RTBHn are 4-bit registers that hold output data in advance. These registers are mapped to independent addresses in the peripheral I/O register area. They can be read or written in 8-bit or 1-bit units. If an operation mode of 4 bits x 1 channel or 2 bits x 1 channel is specified (RTPCn.BYTEn bit = 0), data can be individually set to the RTBLn and RTBHn registers. The data of both these registers can be read at once by specifying the address of either of these registers. If an operation mode of 6 bits x 1 channel is specified (BYTEn bit = 1), 8-bit data can be set to both the RTBLn and RTBHn registers by writing the data to either of these registers. Moreover, the data of both these registers can be read at once by specifying the address of either of these registers. Table 13-2 shows the operation when the RTBLn and RTBHn registers are manipulated. After reset: 00H R/W Address: RTBL0 FFFFF6E0H, RTBL1 FFFFF6F0 RTBH0 FFFFF6E2H, RTBH1 FFFFF6F2 RTBLn RTBHn 0 0 RTBHn5 RTBHn4 RTBLn3 RTBLn2 RTBLn1 RTBLn0 Cautions 1. When writing to bits 6 and 7 of the RTBHn register, always write 0. 2. When the main clock is stopped and the CPU is operating on the subclock, do not access the RTBLn and RTBHn registers using an access method that causes a wait. For details, refer to 3.4.8 (2). Remark n = 0, 1 User's Manual U16889EJ1V0UD 425 CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) Table 13-2. Operation During Manipulation of RTBLn and RTBHn Registers Operation Mode Register to Be Manipulated 4 bits x 1 channel, 2 bits x 1 channel 6 bits x 1 channel RTBLn RTBHn RTBLn RTBHn Higher 4 bits RTBHn RTBHn RTBHn RTBHn Read Lower 4 bits RTBLn RTBLn RTBLn RTBLn Write Higher 4 bits Invalid RTBHn RTBHn RTBHn Note Lower 4 bits RTBLn Invalid RTBLn RTBLn Note After setting the real-time output port, set output data to the RTBLn and RTBHn registers by the time a realtime output trigger is generated. 13.3 Registers RTO is controlled using the following two types of registers. * Real-time output port mode register n (RTPMn) * Real-time output port control register n (RTPCn) (1) Real-time output port mode register n (RTPMn) This register selects the real-time output port mode or port mode in 1-bit units. The RTPMn register can be read or written in 8-bit or 1-bit units. After reset, RTPMn is cleared to 00H. After reset: 00H R/W Address: RTPM0 FFFFF6E4H, RTPM1 FFFFF6F4H RTPMn (n = 0, 1) 0 0 RTPMn5 RTPMn4 RTPMn3 RTPMn2 RTPMn1 RTPMn0 RTPMnm 0 1 Control of real-time output port (m = 0 to 5) Real-time output disabled Real-time output enabled Cautions 1. To reflect real-time output signals (RTPOUTn0 to RTPOUTn5) to the pins (RTPn0 to RTPn5), set them to the real-time output port with the PMC5, PMC6, PFC5, and PFC6 registers. 2. By enabling real-time output operation (RTPCn.RTPOEn bit = 1), the bits specified as real-time output enabled perform real-time output, and the bits specified as real-time output disabled output 0. 3. If real-time output is disabled (RTPOEn bit = 0), real-time output signals (RTPOUTn0 to RTPOUTn5) all output 0, regardless of the RTPMn register setting. 426 User's Manual U16889EJ1V0UD CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) (2) Real-time output port control register n (RTPCn) RTPCn are registers used to set the operation mode and output trigger of the real-time output port. The relationship between the operation mode and output trigger of the real-time output port is as shown in Tables 13-3 and 13-4. The RTPCn register can be read or written in 8-bit or 1-bit units. After reset, RTPCn is cleared to 00H. After reset: 00H <> RTPCn (n = 0, 1) R/W Address: RTPC0 FFFFF6E5H, RTPC1 FFFFF6F5H RTPOEn RTPEGn BYTEn EXTRnNote 1 0 0 0 0 RTPOEn 0 1 Control of real-time output operation Disables operationNote 2 Enables operation RTPEGn 0 1 Valid edge of INTTM000 (n = 0), INTTM020 (n = 1) signal Falling edgeNote 3 Rising edge BYTEn 0 1 Specification of channel configuration for real-time output 4 bits x 1 channel, 2 bits x 1 channel 6 bits x 1 channel Notes 1. For the EXTRn bit, refer to Tables 13-3 and 13-4. 2. When real-time output operation is disabled (RTPOEn bit = 0), real-time output signals (RTPOUTn0 to RTPOUTn5) all output 0. 3. The INTTM000 and INTTM020 signals are output for 1 clock of the count clock selected with the respective timers. Caution Perform the settings for the RTPEGn, BYTEn, and EXTRn bits only when the RTPOEn bit = 0. Table 13-3. Operation Modes and Output Triggers of Real-Time Output Port (n = 0) BYTE0 0 EXTR0 0 1 1 0 1 Operation Mode 4 bits x 1 channel, 2 bits x 1 channel 6 bits x 1 channel RTBH0 (RTP04, RTP05) INTTM51 INTTM50 INTTM50 INTTM000 RTBL0 (RTP00 to RTP03) INTTM50 INTTM000 Table 13-4. Operation Modes and Output Triggers of Real-Time Output Port (n = 1) BYTE1 0 EXTR1 0 1 1 0 1 Operation Mode 4 bits x 1 channel, 2 bits x 1 channel 6 bits x 1 channel RTBH1 (RTP14, RTP15) INTTM50 INTTM51 INTTM51 INTTM020 RTBL1 (RTP10 to RTP13) INTTM51 INTTM020 User's Manual U16889EJ1V0UD 427 CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.4 Operation If the real-time output operation is enabled by setting the RTPCn.RTPOEn bit to 1, the data of the RTBHn and RTBLn registers is transferred to the real-time output latch in synchronization with the generation of the selected transfer trigger (set by the RTPCn.EXTRn and RTPCn.BYTEn bits). Of the transferred data, only the data of the bits specified as real-time output enabled by the RTPMn register is output from bits RTPOUTn0 to RTPOUTn5. The bits specified as real-time output disabled by the RTPMn register output 0. If the real-time output operation is disabled by clearing the RTPOEn bit to 0, the RTPOUTn0 to RTPOUTn5 signals output 0 regardless of the setting of the RTPMn register. Figure 13-2. Example of Operation Timing of RTO0 (When EXTR0 Bit = 0, BYTE0 Bit = 0) INTTM51 (internal) INTTM50 (internal) CPU operation A B A B A B A B RTBH0 D01 D02 D03 D04 RTBL0 D11 D12 D13 D14 RT output latch 0 (H) D01 D02 D03 D04 RT output latch 0 (L) D11 D12 D13 D14 A: Software processing by INTTM51 interrupt request signal (write to RTBH0 register) B: Software processing by INTTM50 interrupt request signal (write to RTBL0 register) Remark For the operation during standby, refer to CHAPTER 22 STANDBY FUNCTION. 428 User's Manual U16889EJ1V0UD CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.5 Usage (1) Disable real-time output. Clear the RTPCn.RTPOEn bit to 0. (2) Perform initialization as follows. * Specify the real-time output port mode or port mode in 1-bit units. Set the RTPMn register. * Channel configuration: Select the trigger and valid edge. Set the RTPCn.EXTRn, RTPCn.BYTEn, and RTPCn.RTPEGn bits. * Set the initial values to the RTBHn and RTBLn registersNote 1. (3) Enable real-time output. Set the RTPOEn bit to 1. (4) Set the next output value to the RTBHn and RTBLn registers by the time the selected transfer trigger is generatedNote 2. (5) Set the next real-time output value to the RTBHn and RTBLn registers through interrupt servicing corresponding to the selected trigger. Notes 1. If write to the RTBHn and RTBLn registers is performed when the RTPOEn bit = 0, that value is transferred to real-time output latches nH and nL, respectively. 2. Even if write is performed to the RTBHn and RTBLn registers when the RTPOEn bit = 1, data transfer to real-time output latches nH and nL is not performed. Caution To reflect the real-time output signals (RTPOUTn0 to RTPOUTn5) to the pins, set the real-time output ports (RTPn0 to RTPn5) with the PMC5, PMC6, PFC5, and PFC6 registers. 13.6 Cautions (1) Prevent the following conflicts by software. * Conflict between real-time output disable/enable switching (RTPOEn bit) and selected real-time output trigger * Conflict between write to the RTBHn and RTBLn registers in the real-time output enabled status and the selected real-time output trigger. (2) Before performing initialization, disable real-time output (RTPOEn bit = 0). (3) Once real-time output has been disabled (RTPOEn bit = 0), be sure to initialize the RTBHn and RTBLn registers before enabling real-time output again (RTPOEn bit = 0 1). User's Manual U16889EJ1V0UD 429 CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) 13.7 Security Function A circuit that sets the pin outputs to high impedance as a security function for when malfunctions of a stepping motor controlled by RTO occur is provided on chip. It forcibly resets the pins allocated to RTP00 to RTP05 via external interrupt INTP0 pin edge detection, and the pins allocated to RTP10 to RTP15 via INTP1 pin edge detection, placing them in the high-impedance state. The ports (P50 to 55, P60 to 65 pins) placed in high impedance by INTP0Note 1 and INTP1Note 1 pins are initializedNote 2, so settings for these ports must be performed again. Notes 1. Regardless of the port settings, P50 to 55 and P60 to 65 pins are all placed in high impedance via INTPn. 2. The bits that are initialized are all the bits corresponding to P50 to 55 and P60 to 65 pins of the following registers. * P5, P6L registers * PM5, PM6L registers * PMC5, PMC6L registers * PU5, PU6L registers * PFC5 register * PF5 register The block diagram of the security function is shown below. Figure 13-3. Block Diagram of Security Function INTPn Edge detection INTC EVDD R RTOSTn RTPOUTn0 to RTPOUTn5 RTPn0 to RTPn5 6 Remark n = 0, 1 This function is set with the PLLCTL.RTOST1 and PLLCTL.RTOST0 bits. 430 User's Manual U16889EJ1V0UD CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO) (1) PLL control register (PLLCTL) The PLLCTL register is an 8-bit register that controls the RTO security function and PLL. This register can be read or written in 8-bit or 1-bit units. After reset, PLLCTL is set to 01H. After reset: 01H R/W Address: FFFFF806H <> <> <> Note <> PLLONNote PLLCTL 0 0 0 0 RTOST1 RTOST0 SELPLL RTOSTn 0 1 Control of RTPn0 to RTPn5 security function INTPn pin is not used as trigger for security function INTPn pin is used as trigger for security function Note For details on the SELPLL and PLLON bits, refer to CHAPTER 6 CLOCK GENERATION FUNCTION. Cautions 1. Before outputting a value to the real-time output ports (RTPn0 to RTPn5), select the INTPn pin interrupt edge detection and then set the RTOST0 and RTOST1 bits. 2. To set again the ports (P50 to P55, P60 to P65 pins) as real-time output ports after placing them in high impedance via the INTPn pin, first cancel the security function. [Procedure to set ports again] <1> Cancel the security function and enable port setting by clearing the RTOSTn bit to 0. <2> Set the RTOSTn bit to 1 (only if required) <3> Set again as real-time output port. 3. Be sure to clear bits 4 to 7 to 0. Remark n = 0, 1 User's Manual U16889EJ1V0UD 431 CHAPTER 14 A/D CONVERTER 14.1 Function The A/D converter converts analog input signals into digital values with a resolution of 10 bits and has a 16channel (ANI0 to ANI15) configuration. The A/D converter has the following functions. (1) 10-bit resolution A/D conversion 1 analog input channel is selected from ANI0 to ANI15, and an A/D conversion operation with resolution of 10 bits is repeatedly executed. Every time A/D conversion is completed, an interrupt request signal (INTAD) is generated. (2) Power fail detection function This is a function to detect low voltage in a battery. The results of A/D conversion (the value in the ADCRH register) and the PFT register are compared, and INTAD signal is generated only when the comparison conditions match. 432 User's Manual U16889EJ1V0UD CHAPTER 14 A/D CONVERTER 14.2 Configuration The A/D converter consists of the following hardware. Figure 14-1. Block Diagram of A/D Converter AVREF0 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 ANI12 ANI13 ANI14 ANI15 ADCS bit Sample & hold circuit Voltage comparator AVSS Successive approximation register (SAR) Tap selector Selector AVSS INTAD Controller Comparator 4 A/D conversion result register (ADCR/ADCRH) Power fail comparison threshold register (PFT) ADS3 ADS2 ADS1 ADS0 ADCS FR2 FR1 FR0 ADCS2 PFEN PFCM Analog input channel specification register (ADS) A/D converter mode register (ADM) Internal bus Power fail comparison mode register (PFM) Table 14-1. Registers of A/D Converter Used by Software Item Registers Configuration A/D conversion result register (ADCR) A/D conversion result register H (ADCRH): Only higher 8 bits can be read Power fail comparison threshold register (PFT) A/D converter mode register (ADM) Analog input channel specification register (ADS) Power fail comparison mode register (PFM) User's Manual U16889EJ1V0UD 433 CHAPTER 14 A/D CONVERTER (1) ANI0 to ANI15 pins These are analog input pins for the 16 channels of the A/D converter. They are used to input analog signals to be converted into digital signals. Pins other than those selected as analog input by the ADS register can be used as input ports. (2) Sample & hold circuit The sample & hold circuit samples the analog input signals selected by the input circuit and sends the sampled data to the voltage comparator. This circuit holds the sampled analog input voltage during A/D conversion. (3) Series resistor string The series resistor string is connected between AVREF0 and AVSS and generates a voltage for comparison with the analog input signal. (4) Voltage comparator The voltage comparator compares the value that is sampled and held with the output voltage of the series resistor string. (5) Successive approximation register (SAR) This register compares the sampled analog voltage value with the voltage value from the series resistor string, and converts the comparison result starting from the most significant bit (MSB). When the least significant bit (LSB) has been converted to a digital value (end of A/D conversion), the contents of the SAR register are transferred to the ADCR register. The SAR register cannot be read or written directly. (6) A/D conversion result register (ADCR), A/D conversion result register H (ADCRH) Each time A/D conversion ends, the conversion results are loaded from the successive approximation register and the results of A/D conversion are held in the higher 10 bits of this register (the lower 6 bits are fixed to 0). (7) Controller The controller compares the A/D conversion results (the value of the ADCRH register) with the value of the PFT register when A/D conversion ends or the power fail detection function is used. It generates INTAD signal only when the comparison conditions match. (8) AVREF0 pin This is the analog power supply pin/reference voltage input pin of the A/D converter. Always use the same potential as the VDD pin even when not using the A/D converter. The signals input to the ANI0 to ANI15 pins are converted into digital signals based on the voltage applied across AVREF0 and AVSS. (9) AVSS pin This is the ground potential pin of the A/D converter. Always use the same potential as the VSS pin even when not using the A/D converter. 434 User's Manual U16889EJ1V0UD CHAPTER 14 A/D CONVERTER (10) A/D converter mode register (ADM) This register sets the conversion time of the analog input to be converted to a digital signal and the conversion operation start/stop. (11) Analog input channel specification register (ADS) This register specifies the input port for the analog voltage to be converted to a digital signal. (12) Power fail comparison mode register (PFM) This register sets the power fail monitoring mode. (13) Power fail comparison threshold register (PFT) This register sets the threshold to be compared with the ADCR register. 14.3 Registers The A/D converter is controlled by the following registers. * A/D converter mode register (ADM) * Analog input channel specification register (ADS) * Power fail comparison mode register (PFM) * Power fail comparison threshold register (PFT) * A/D conversion result register, A/D conversion result register H (ADCR, ADCRH) User's Manual U16889EJ1V0UD 435 CHAPTER 14 A/D CONVERTER (1) A/D converter mode register (ADM) This register sets the conversion time of the analog input signal to be converted into a digital signal as well as conversion start and stop. The ADM register can be read or written in 8-bit or 1-bit units. After reset, ADM is cleared to 00H. After reset: 00H <> ADM ADCS R/W Address: FFFFF200H <> 0 FR2 FR1 FR0 0 0 ADCS2 ADCS 0 1 Control of A/D conversion operation Conversion operation stopped Conversion operation enabled FR2 FR1 FR0 Conversion timeNote 1 Selection of conversion time fXX 20 MHz 16 MHz 18.0 s 10 MHz 28.8 s 24.0 s 14.4 s 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 288/fXX 240/fXX 192/fXX Setting prohibited 15.0 s Setting prohibited Setting prohibited 19.2 s Setting prohibited Setting prohibited 14.4 s Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited 144/fXX 120/fXX 96/fXX Setting prohibited Setting prohibited Setting prohibited Setting prohibited ADCS2 0 1 Control of reference voltage generator for boosting operationNote 2 Reference voltage generator operation stopped Reference voltage generator operation stopped Notes 1. Setting the conversion time (time actually required for A/D conversion) as follows is prohibited. AVREF0 4.0 V: Less than 14 s AVREF0 < 4.0 V: Less than 17 s 2. The operation of the reference voltage generator for boosting is controlled by the ADCS2 bit and it takes 17 s (14 s when AVREF0 4.0 V) after operation is started until it is stabilized. Therefore the ADCS bit is set to 1 (A/D conversion is started) at least 17 s (14 s when AVREF0 4.0 V) after if the ADCS2 bit was set to 1 (reference voltage generator for boosting is on), the first conversion result is valid. Cautions 1. Be sure to clear bits 6, 2, and 1 to 0. 2. Changing bits FR0 to FR2 while the ADCS bit = 1 is prohibited (write access to the ADM register is enabled and rewriting of bits FR0 to FR2 is prohibited). 3. When the main clock is stopped and the CPU is operating on the subclock, do not access the ADM register using an access method that causes a wait. For details, refer to 3.4.8 (2). Remark fXX: Main clock frequency 436 User's Manual U16889EJ1V0UD CHAPTER 14 A/D CONVERTER Table 14-2. Setting of ADCS Bit and ADCS2 Bit ADCS 0 0 1 1 ADCS2 0 1 0 1 A/D Conversion Operation Stopped status (DC power consumption path does not exist) Conversion standby mode (only the reference voltage generator for boosting consumes power) Conversion mode (reference voltage generator stops operation Conversion mode (reference voltage generator is operating) Note ) Note The data obtained by the first conversion must not be used. Figure 14-2. Operation Sequence Reference voltage generator for boosting: Operating ADCS2 Comparator control Conversion operation ADCS Conversion standby Conversion operation Conversion stop Note Note 17 s (14 s when AVREF0 4.0 V) or more are required for the operation of the reference voltage generator for boosting between when the ADCS2 bit is set (1) and when the ADCS bit is set (1). User's Manual U16889EJ1V0UD 437 CHAPTER 14 A/D CONVERTER (2) Analog input channel specification register (ADS) This register specifies the analog voltage input port for A/D conversion. The ADS register can be read or written in 8-bit or 1-bit units. After reset, ADS is cleared to 00H. After reset: 00H R/W Address: FFFFF201H ADS 0 0 0 0 ADS3 ADS2 ADS1 ADS0 ADS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ADS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ADS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ADS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Specification of analog input channel ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 ANI12 ANI13 ANI14 ANI15 Cautions 1. Be sure to clear bits 7 to 4 to 0. 2. When the main clock is stopped and the CPU is operating on the subclock, do not access the ADS register using an access method that causes a wait. For details, refer to 3.4.8 (2). 438 User's Manual U16889EJ1V0UD CHAPTER 14 A/D CONVERTER (3) A/D conversion result register, A/D conversion result register H (ADCR, ADCRH) The ADCR and ADCRH registers store the A/D conversion results. These registers are read-only in 16-bit or 8-bit units. However, specify the ADCR register for 16-bit access, and the ADCRH register for 8-bit access. In the ADCR register, the 10 bits of conversion results are read in the higher 10 bits and 0 is read in the lower 6 bits. In the ADCRH register, the higher 8 bits of the conversion results are read. After reset, these registers are undefined. After reset: Undefined R Address: FFFFF204H ADCR AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 0 0 0 0 0 0 After reset: Undefined 7 ADCRH AD9 6 AD8 R Address: FFFFF205H 5 AD7 4 AD6 3 AD5 2 AD4 1 AD3 0 AD2 Caution When the main clock is stopped and the CPU is operating on the subclock, do not access the ADCR and ADCRH registers using an access method that causes a wait. For details, refer to 3.4.8 (2). User's Manual U16889EJ1V0UD 439 CHAPTER 14 A/D CONVERTER The following shows the relationship between the analog input voltage input to the analog input pins (ANI0 to ANI15) and A/D conversion results (ADCR register). SAR = INT ( VIN AVREF0 x 1024 + 0.5) ADCRNote = SAR x 64 Or, (SAR - 0.5) x INT ( ): VIN: AVREF0: ADCR: AVREF0 1024 VIN < (SAR + 0.5) x AVREF0 1024 Function that returns the integer part of the value in parentheses Analog input voltage Voltage of AVREF0 pin Value in the ADCR register Note The lower 6 bits of the ADCR register are fixed to 0. The following shows the relationship between the analog input voltage and A/D conversion results. Figure 14-3. Relationship Between Analog Input Voltage and A/D Conversion Results SAR ADCR 1023 FFC0H 1022 FF80H A/D conversion results 1021 FF40H 3 00C0H 2 0080H 1 0040H 0 0000H 1 1 3 2 5 3 2048 1024 2048 1024 2048 1024 2043 1022 2045 1023 2047 1 2048 1024 2048 1024 2048 Input voltage/AVREF0 440 User's Manual U16889EJ1V0UD CHAPTER 14 A/D CONVERTER (4) Power fail comparison mode register (PFM) This register sets the power fail monitoring mode. The PFM register compares the value in the PFT register with the value of the ADCRH register. The PFM register can be read or written in 8-bit or 1-bit units. After reset, PFM is cleared to 00H. After reset: 00H <> PFM PFEN R/W <> PFCM Address: FFFFF202H 0 0 0 0 0 0 PFEN 0 1 Selection of power fail comparison enable/disable Power fail comparison disabled Power fail comparison enabled PFCM 0 1 Selection of power fail comparison mode Interrupt request signal (INTAD) generated when ADCR PFT Interrupt request signal (INTAD) generated when ADCR < PFT Caution When the main clock is stopped and the CPU is operating on the subclock, do not access the PFM register using an access method that causes a wait. For details, refer to 3.4.8 (2). (5) Power fail comparison threshold register (PFT) The PFT register sets the comparison value in the power fail comparison mode. The 8-bit data set in the PFT register is compared with the value of the ADCRH register. The PFT register can be read or written in 8-bit units. After reset, PFT is cleared to 00H. After reset: 00H 7 PFT R/W 6 Address: FFFFF203H 5 4 3 2 1 0 Caution When the main clock is stopped and the CPU is operating on the subclock, do not access the PFT register using an access method that causes a wait. For details, refer to 3.4.8 (2). User's Manual U16889EJ1V0UD 441 CHAPTER 14 A/D CONVERTER 14.4 Operation 14.4.1 Basic operation <1> Select the channel whose analog signal is to be converted into a digital signal using the ADS register. <2> Set (1) the ADM.ADCS2 bit and wait 17 s (14 s when AVREF0 4.0 V) or longer. <3> Set the ADM.ADCS bit to 1 to start A/D conversion. (Steps <4> to <10> are executed by hardware.) <4> The sample & hold circuit samples the voltage input to the selected analog input channel. <5> After sampling for a specific time, the sample & hold circuit enters the hold status and holds the input analog voltage until it has been converted into a digital signal. <6> Set bit 9 of the successive approximation register (SAR). The tap selector sets the voltage tap of the series resistor string to (1/2) x AVREF0. <7> The voltage comparator compares the voltage difference between the voltage tap of the series resistor string and the analog input voltage. If the analog input voltage is greater than (1/2) x AVREF0, the MSB of the SAR register remains set. If the analog input voltage is less than (1/2) x AVREF0, the MSB is reset. <8> Next, bit 8 of the SAR register is automatically set and the next comparison starts. Depending on the value of bit 9 to which the result of the preceding comparison has been set, the voltage tap of the series resistor string is selected as follows. * Bit 9 = 1: (3/4) x AVREF0 * Bit 9 = 0: (1/4) x AVREF0 The analog input voltage is compared with one of these voltage taps and bit 8 of the SAR register is manipulated as follows depending on the result of the comparison. Analog input voltage voltage tap: Bit 8 = 1 Analog input voltage voltage tap: Bit 8 = 0 <9> The above steps are repeated until bit 0 of the SAR register has been manipulated. <10> When comparison of all 10 bits of the SAR register has been completed, the valid digital value remains in the SAR register, and the value of the SAR register is transferred and latched to the ADCR register. At the same time, an A/D conversion end interrupt request signal (INTAD) is generated. <11> Repeat steps <4> to <10> until the ADCS bit is cleared to 0. For another A/D conversion, start at <3>. However, when operating the A/D converter with the ADCS2 bit cleared to 0, start at <2>. 442 User's Manual U16889EJ1V0UD CHAPTER 14 A/D CONVERTER 14.4.2 A/D conversion operation * Setting the ADM.ADCS bit to 1 starts conversion of the signal input to the channel specified by the ADS register. Upon completion of the conversion, the conversion result is stored in the ADCR register and a new conversion starts. * If the ADM, ADS, PFT, or PFM register is written during conversion, conversion is interrupted and the conversion operation starts again from the beginning. * If the ADCS bit is cleared to 0 during conversion, conversion is interrupted and the conversion operation is stopped. * For whether or not the conversion end interrupt request signal (INTAD) is generated, refer to 14.4.3. 14.4.3 Power fail monitoring function The conversion end interrupt request signal (INTAD) can be controlled as follows using the PFM and PFT registers. * If the PFM.PFEN bit = 0, the INTAD signal is generated each time conversion ends. * If the PFEN bit = 1 and the PFM.PFCM bit = 0, the conversion result and the value of the PFT register are compared when conversion ends, and the INTAD signal is output only if ADCRH PFT. * If the PFEN and PFCM bits = 1, the conversion result and the value of the PFT register are compared when conversion ends and the INTAD signal is output only if ADCRH < PFT. * Because, when the PFEN bit = 1, the conversion result is overwritten after the INTAD signal has been output, unless the conversion result is read by the time the next conversion ends, in some cases it may appear as if the actual operation differs from the operation described above (refer to Figure 14-4). Figure 14-4. Power Fail Monitoring Function (PFCM Bit = 0) Conversion operation ANI0 ANI0 ANI0 ANI0 ADCRH 80H 7FH 80H PFT 80H INTAD Note Note If reading is not performed during this interval, the conversion result changes to the next conversion result. User's Manual U16889EJ1V0UD 443 CHAPTER 14 A/D CONVERTER The following describes how to set registers. * When using the A/D converter for A/D conversion <1> Set (1) the ADM.ADCS2 bit. <2> Select the channel and conversion time by setting the ADS.ADS3 to ADS.ADS0 bits and the ADM.FR2 to ADM.FR0 bits. <3> Set (1) the ADM.ADCS bit. <4> Transfer the A/D conversion data to the ADCR register. <5> An interrupt request signal (INTAD) is generated. 444 User's Manual U16889EJ1V0UD CHAPTER 14 A/D CONVERTER 14.5 Cautions (1) Power consumption in standby mode The operation of the A/D converter stops in the standby mode. At this time, the power consumption can be reduced by stopping the conversion operation (the ADM.ADCS bit = 0). Figure 14-5 shows an example of how to reduce the power consumption in the standby mode. Figure 14-5. Example of How to Reduce Power Consumption in Standby Mode AVREF0 P-ch ADCS Series resistor string AVSS (2) Input range of ANI0 to ANI15 pins Use the A/D converter with the ANI0 to ANI15 pin input voltages within the specified range. If a voltage of AVREF0 or higher or AVSS or lower (even if within the absolute maximum ratings) is input to these pins, the conversion value of the channel is undefined. Also, this may affect the conversion value of other channels. (3) Conflicting operations (a) Conflict between writing to the ADCR register and reading from ADCR register upon the end of conversion Reading the ADCR register takes precedence. After the register has been read, a new conversion result is written to the ADCR register. (b) Conflict between writing to the ADCR register and writing to the ADM register or writing to the ADS register upon the end of conversion Writing to the ADM register or ADS register takes precedence. The ADCR register is not written, and neither is the conversion end interrupt request signal (INTAD) generated. User's Manual U16889EJ1V0UD 445 CHAPTER 14 A/D CONVERTER (4) Measures against noise To keep a resolution of 10 bits, be aware of noise on the AVREF0 and ANI0 to ANI15 pins. The higher the output impedance of the analog input source, the greater the effect of noise. Therefore, it is recommended to connect external capacitors as shown in Figure 14-6 to reduce noise. Figure 14-6. Handling of Analog Input Pins If noise of AVREF0 or higher or AVSS or lower could be generated, clamp with a diode with a small VF (0.3 V or lower). Reference voltage input AVREF0 ANI0 to ANI15 C = 100 to 1000 pF AVSS VSS (5) ANI0/P70 to ANI15/P715 pins The analog input pins (ANI0 to ANI15) function alternately as input port pins (P70 to P715). When performing A/D conversion by selecting any of the ANI0 to ANI15 pins, do not execute an input instruction to port 7 during conversion. This may decrease the conversion resolution. If digital pulses are applied to the pin adjacent to the pin subject to A/D conversion, the value of the A/D conversion may differ from the expected value because of coupling noise. Therefore, do not apply pulses to the pin adjacent to the pin subject to A/D conversion. (6) Input impedance of AVREF0 pin A series resistor string of tens of k is connected between the AVREF0 pin and AVSS pin. Therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to the series resistor string between the AVREF0 pin and AVSS pin, resulting in a large reference voltage error. 446 User's Manual U16889EJ1V0UD CHAPTER 14 A/D CONVERTER (7) Interrupt request flag (ADIC.ADIF bit) Even when the ADS register is changed, the ADIF bit is not cleared (0). Therefore, if the analog input pin is changed during A/D conversion, the ADIF bit may be set (1) because A/D conversion of the previous analog input pin ends immediately before the ADS register is rewritten. In a such case, note that if the ADIF bit is read immediately after the ADS register has been rewritten, the ADIF bit is set (1) even though A/D conversion of the analog input pin after the change has not been completed. When stopping A/D conversion once and resuming it, clear the ADIF bit (0) before resuming A/D conversion. Figure 14-7. A/D Conversion End Interrupt Request Occurrence Timing ADS rewrite (ANIn conversion start) ADS rewrite (ANIm conversion start) ANIm conversion is not complete even though ADIF is set. A/D conversion ANIn ANIn ANIm ANIm ADCR ANIn ANIn ANIm ANIm INTAD Remark n = 0 to 15 m = 0 to 15 (8) Conversion results immediately after A/D conversion start If the ADM.ADCS bit is set to 1 within 17 s (14 s when AVREF0 4.0 V) after the ADM.ADCS2 bit has been set to 1, or if the ADCS bit is set to 1 with the ADCS2 bit cleared to 0, the converted value immediately after the A/D conversion operation has started may not satisfy the rating. Take appropriate measures such as polling the A/D conversion end interrupt request signal (INTAD) and discarding the first conversion result. (9) Reading A/D conversion result register (ADCR) When the ADM or ADS register has been written, the contents of the ADCR register may become undefined. When the conversion operation is complete, read the conversion results before writing to the ADM or ADS register. A correct conversion result may not be able to be read at a timing other than the above. When the CPU is operating on the subclock and main clock oscillation (fX) is stopped, do not read the ADCR register. User's Manual U16889EJ1V0UD 447 CHAPTER 14 A/D CONVERTER (10) A/D converter sampling time and A/D conversion start delay time The A/D converter sampling time differs depending on the set value of the ADM register. A delay time exists until actual sampling is started after A/D converter operation is enabled. When using a set in which the A/D conversion time must be strictly observed, care is required for the contents shown in Figure 14-8 and Table 14-3. Figure 14-8. Timing of A/D Converter Sampling and A/D Conversion Start Delay ADCS 1 or ADS rewrite ADCS Sampling timing INTAD Wait period A/D Sampling conversion time start delay time Sampling time Conversion time Conversion time Table 14-3. A/D Converter Sampling Time and A/D Conversion Start Delay Time (ADM Register Set Value) FR2 FR1 FR0 Conversion Time Sampling Time A/D Conversion Start Delay Time Note 2 MIN. 0 0 0 1 1 1 0 0 1 0 0 1 Other than above 0 1 0 0 1 0 288/fXX 240/fXX 192/fXX 144/fXX 120/fXX 96/fXX Setting prohibited 40/fXX 32/fXX 24/fXX 20/fXX 16/fXX 12/fXX - 32/fXX 28/fXX 24/fXX 16/fXX 14/fXX 12/fXX - MAX. 36/fXX 32/fXX 28/fXX 18/fXX 16/fXX 14/fXX - Note 3 MIN. 11/fXX 11/fXX 10/fXX 9/fXX 9/fXX 11/fXX - MAX. 12/fXX 12/fXX 11/fXX 10/fXX 10/fXX 12/fXX - Note 1 Notes 1. The A/D conversion start delay time is the time after the wait period. For the wait function, refer to 3.4.8 (2) Access to special on-chip peripheral I/O register. 2. PD703216, 703216Y, 703217, 703217Y, 70F3217, 70F3217Y 3. PD70F3217H, 70F3217HY, 70F3218H, 70F3218HY Remark fXX: Main clock frequency 448 User's Manual U16889EJ1V0UD CHAPTER 14 A/D CONVERTER (11) Internal equivalent circuit The following shows the equivalent circuit of the analog input block. Figure 14-9. Internal Equivalent Circuit of ANIn Pin RIN ANIn COUT CIN * PD70F3217H, 70F3217HY, 70F3218H, 70F3218HY AVREF0 4.5 V 2.7 V RIN 3 k 60 k COUT 8 pF 8 pF CIN 15 pF 15 pF * PD703216, 703216Y, 703217, 703217Y, 70F3217, 70F3217Y AVREF0 4.5 V 2.7 V RIN 6.7 k 20 k COUT 8 pF 8 pF CIN 3.4 pF 5 pF Remarks 1. The above values are reference values. 2. n = 0 to 15 User's Manual U16889EJ1V0UD 449 CHAPTER 14 A/D CONVERTER 14.6 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1 LSB (Least Significant Bit). The percentage of 1 LSB with respect to the full scale is expressed by %FSR (Full Scale Range). %FSR indicates the ratio of analog input voltage that can be converted as a percentage, and is always represented by the following formula regardless of the resolution. 1 %FSR = (Max. value of analog input voltage that can be converted - Min. value of analog input voltage that can be converted)/100 = (AVREF0 - 0)/100 = AVREF0/100 1 LSB is as follows when the resolution is 10 bits. 1 LSB = 1/210 = 1/1024 = 0.098%FSR Accuracy has no relation to resolution, but is determined by overall error. (2) Overall error This shows the maximum error value between the actual measured value and the theoretical value. Zero-scale error, full-scale error, linearity error and errors that are combinations of these express the overall error. Note that the quantization error is not included in the overall error in the characteristics table. Figure 14-10. Overall Error 1......1 Ideal line Digital output Overall error 0......0 0 Analog input AVREF0 450 User's Manual U16889EJ1V0UD CHAPTER 14 A/D CONVERTER (3) Quantization error When analog values are converted to digital values, a 1/2 LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of 1/2 LSB is converted to the same digital code, so a quantization error cannot be avoided. Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. Figure 14-11. Quantization Error 1......1 Digital output 1/2 LSB Quantization error 1/2 LSB 0......0 0 Analog input AVREF0 (4) Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2 LSB) when the digital output changes from 0......000 to 0......001. Figure 14-12. Zero-Scale Error 111 Digital output (Lower 3 bits) Ideal line 100 Zero-scale error 011 010 001 000 -1 0 1 2 3 AVREF0 Analog input (LSB) User's Manual U16889EJ1V0UD 451 CHAPTER 14 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (full scale - 3/2 LSB) when the digital output changes from 1......110 to 1......111. Figure 14-13. Full-Scale Error Full-scale error Digital output (Lower 3 bits) 111 100 011 010 000 0 AVREF0-3 AVREF0-2 AVREF0-1 AVREF0 Analog input (LSB) (6) Differential linearity error While the ideal width of code output is 1 LSB, this indicates the difference between the actual measurement value and the ideal value. Figure 14-14. Differential Linearity Error 1......1 Ideal 1 LSB width Digital output Differential linearity error 0......0 0 Analog input AVREF0 452 User's Manual U16889EJ1V0UD CHAPTER 14 A/D CONVERTER (7) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. Figure 14-15. Integral Linearity Error 1......1 Ideal line Digital output 0......0 0 Integral linearity error AVREF0 Analog input (8) Conversion time This expresses the time from when the analog input voltage was applied to the time when the digital output was obtained. The sampling time is included in the conversion time in the characteristics table. (9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. Figure 14-16. Sampling Time Sampling time Conversion time User's Manual U16889EJ1V0UD 453 CHAPTER 15 D/A CONVERTER 15.1 Functions In the V850ES/KJ1, two channels of D/A converter (DAC0, DAC1) are provided. The D/A converter has the following functions. 8-bit resolution x 2 channels R-2R ladder string method Conversion time: 20 s (MAX.) (AVREF1 = 2.7 to 5.5 V) Analog output voltage: AVREF1 x m/256 (m = 0 to 255; value set to DACSn register) Operation modes: Normal mode, real-time output mode Remark n = 0, 1 454 User's Manual U16889EJ1V0UD CHAPTER 15 D/A CONVERTER 15.2 Configuration The D/A converter configuration is shown below. Figure 15-1. Block Diagram of D/A Converter DACS0 register write DAM.DAMD0 bit DACS0 INTTMH0 signal DACE0 AVREF1 AVSS Selector ANO0 ANO1 Selector DACE1 DACS1 register write DAM.DAMD1 bit INTTMH1 signal DACS1 Caution DAC0 and DAC1 share the AVREF1 and AVSS pins. The AVSS pin is also shared by the A/D converter. The D/A converter consists of the following hardware. Table 15-1. Configuration of D/A Converter Item Control register Configuration D/A converter mode register (DAM) D/A conversion value setting registers 0 and 1 (DACS0, DACS1) User's Manual U16889EJ1V0UD 455 CHAPTER 15 D/A CONVERTER 15.3 Registers The registers that control the D/A converter are as follows. * D/A converter mode register (DAM) * D/A conversion value setting registers 0 and 1 (DACS0, DACS1) (1) D/A converter mode register (DAM) This register controls the operation of the D/A converter. The DAM register can be read or written in 8-bit or 1-bit units. After reset, DAM is cleared to 00H. After reset: 00H R/W Address: FFFFF284H <> <> DAMD0 DACE0 DAM 0 0 0 0 DAMD1 DACE1 DAMDn 0 1 Selection of D/A converter operation mode (n = 0, 1) Normal mode Real-time output modeNote DACEn 0 1 D/A converter operation enable/disable control (n = 0, 1) Disable operation Enable operation Note The output trigger in the real-time output mode (DAMDn bit = 1) is as follows. * When n = 0: INTTMH0 signal (Refer to CHAPTER 10 8-BIT TIMER H) * When n = 1: INTTMH1 signal (Refer to CHAPTER 10 8-BIT TIMER H) (2) D/A conversion value setting registers 0 and 1 (DACS0, DACS1) These registers set the analog voltage value output to the ANO0 and ANO1 pins. These registers can be read or written in 8-bit units. After reset, DACS0 and DACS1 are cleared to 00H. After reset: 00H R/W Address: DACS0 FFFFF280H, DACS1 FFFFF282H DACSn (n = 0, 1) DAn7 DAn6 DAn5 DAn4 DAn3 DAn2 DAn1 DAn0 Caution In the real-time output mode (DAM.DAMDn bit = 1), set the DACS0 and DACS1 registers before the INTTMH0 and INTTMH1 signals are generated. D/A conversion starts when the INTTMH0 and INTTMH1 signals are generated. 456 User's Manual U16889EJ1V0UD CHAPTER 15 D/A CONVERTER 15.4 Operation 15.4.1 Operation in normal mode D/A conversion is performed using a write operation to the DACSn register as the trigger. The setting method is described below. <1> Clear the DAM.DAMDn bit to 0 (normal mode). <2> Set the analog voltage value to be output to the ANOn pin to the DACSn register. Steps <1> and <2> above constitute the initial settings. <3> Set the DAM.DACEn bit to 1 (D/A conversion enable). D/A converted analog voltage value is output from the ANOn pin when this setting is performed. <4> To change the analog voltage value, write to the DACSn register. The analog voltage value immediately before set is held until the next write operation is performed. Remarks 1. For the alternate-function pin settings, refer to Table 4-19 Settings When Port Pins Are Used for Alternate Functions. 2. n = 0, 1 15.4.2 Operation in real-time output mode D/A conversion is performed using the interrupt request signals (INTTMH0, INTTMH1) of 8-bit timers H0 and H1 as the trigger. The setting method is described below. <1> Set the DAM.DAMDn bit to 1 (real-time output mode). <2> Set the analog voltage value to be output to the ANOn pin to the DACSn register. <3> Set the DAM.DACEn bit to 1 (D/A conversion enable). Steps <1> to <3> above constitute the initial settings. <4> Operate 8-bit timers H0 and H1. <5> D/A converted analog voltage value is output from the ANOn pin when the INTTMH0 and INTTMH1 signals are generated. Set the next output analog voltage value to the DACSn register, before the next INTTMH0 and INTTMH1 signals are generated. <6> After that, the value set in the DACSn register is output from the ANOn pin every time the INTTMH0 are INTTMH1 signals are generated. Remarks 1. The output values of the ANO0 and ANO1 pins up to <5> above are undefined. 2. For the output values of the ANO0 and ANO1 pins in the IDLE, HALT, and STOP modes, refer to CHAPTER 22 STANDBY FUNCTION. 3. n = 0, 1 User's Manual U16889EJ1V0UD 457 CHAPTER 15 D/A CONVERTER 15.4.3 Cautions Observe the following cautions when using the D/A converter. * When using the D/A converter, set the port pins to the input mode (PM10, PM11 bits = 11) * When using the D/A converter, reading of the port is prohibited. * When using the D/A converter, use both P10 and P11 as D/A outputs. Using one of the port 1 for D/A output and the other as a port is prohibited. * In the real-time output mode, do not change the set value of the DACSn register while the trigger signal is output. * Make sure that AVREF1 VDD and AVREF1 = 2.7 to 5.5 V. The operation is not guaranteed if ranges other than the above are used. * Because the output impedance of the D/A converter is high, a current cannot be supplied from the ANOn pin. When connecting a resistor of 2 M or lower, take appropriate measures such as inserting a JFET input type operational amplifier between the resistor and the ANOn pin. Remark n = 0, 1 Figure 15-2. Example of External Pin Connection - Output ANOn + JFET input type operational amplifier 10 F EVDD AVREF0 AVSS 0.1 F AVREF1 0.1 F 10 F Caution The figure shown here is only reference. Use it after fully evaluating. 458 User's Manual U16889EJ1V0UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) In the V850ES/KJ1, three channels of asynchronous serial interface (UART) are provided. 16.1 Selecting UART2 or I2C1 Mode UART2 and I2C1 of the V850ES/KJ1 share pins, and therefore these interfaces cannot be used at the same time. Select UART2 or I2C1 in advance by using the PMC8 and PFC8 registers (refer to 4.3.8 Port 8). Caution UART2 or I2C1 transmission/reception operations are not guaranteed if the mode is changed during transmission or reception. Be sure to disable the operation of the unit that is not used. Figure 16-1. Selecting Mode of UART2 or I2C1 After reset: 00H 7 PMC8 0 R/W 6 0 Address: FFFFF450H 5 0 4 0 3 0 2 0 1 PMC81 0 PMC80 After reset: 00H 7 PFC8 0 R/W 6 0 Address: FFFFF470H 5 0 4 0 3 0 2 0 1 PFC81 0 PFC80 PFC8n 0 0 1 1 PMC8n 0 1 0 1 Operation mode Port I/O mode UART2 mode Port I/O mode I C1 mode 2 Remark n = 0, 1 User's Manual U16889EJ1V0UD 459 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.2 Features * Maximum transfer speed: 312.5 kbps * Full-duplex communications On-chip RXBn register On-chip TXBn register * Two-pin configurationNote TXDn: Transmit data output pin RXDn: Receive data input pin * Reception error detection functions * Parity error * Framing error * Overrun error * Interrupt sources: 3 types * Reception error interrupt request signal (INTSREn): * Reception completion interrupt request signal (INTSRn): Interrupt is generated according to the logical OR of the three types of reception errors Interrupt is generated when receive data is transferred from the receive shift register to the RXBn register after serial transfer is completed during a reception enabled state * Transmission completion interrupt request signal (INTSTn): Interrupt is generated when the serial transmission of transmit data (8 or 7 bits) from the transmit shift register is completed * Character length: 7 or 8 bits * Parity functions: Odd, even, 0, or none * Transmission stop bits: 1 or 2 bits * On-chip dedicated baud rate generator Note The ASCK0 pin (external clock input) is available only for UART0. 460 User's Manual U16889EJ1V0UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.3 Configuration Table 16-1. Configuration of UARTn Item Registers Receive buffer register n (RXBn) Transmit buffer register n (TXBn) Receive shift register Transmit shift register Asynchronous serial interface mode register n (ASIMM) Asynchronous serial interface status register n (ASISn) Asynchronous serial interface transmit status register n (ASIFn) Other Reception control parity check Addition of transmission control parity Configuration Remark n = 0 to 2 Figure 16-2 shows the configuration of UARTn. (1) Asynchronous serial interface mode register n (ASIMn) The ASIMn register is an 8-bit register for specifying the operation of UARTn. (2) Asynchronous serial interface status register n (ASISn) The ASISn register consists of a set of flags that indicate the error contents when a reception error occurs. The various reception error flags are set (1) when a reception error occurs and are cleared (0) when the ASISn register is read. (3) Asynchronous serial interface transmit status register n (ASIFn) The ASIFn register is an 8-bit register that indicates the status when a transmit operation is performed. This register consists of a transmit buffer data flag, which indicates the hold status of the TXBn register data, and the transmit shift register data flag, which indicates whether transmission is in progress. (4) Reception control parity check The receive operation is controlled according to the contents set in the ASIMn register. A check for parity errors is also performed during a receive operation, and if an error is detected, a value corresponding to the error contents is set in the ASISn register. (5) Receive shift register This is a shift register that converts the serial data that was input to the RXDn pin to parallel data. One byte of data is received, and if a stop bit is detected, the receive data is transferred to the RXBn register. This register cannot be directly manipulated. (6) Receive buffer register n (RXBn) The RXBn register is an 8-bit buffer register for holding receive data. When 7 characters are received, 0 is stored in the MSB. During a reception enabled state, receive data is transferred from the receive shift register to the RXBn register, synchronized with the end of the shift-in processing of one frame. Also, the reception completion interrupt request signal (INTSRn) is generated by the transfer of data to the RXBn register. User's Manual U16889EJ1V0UD 461 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) (7) Transmit shift register This is a shift register that converts the parallel data that was transferred from the TXBn register to serial data. When one byte of data is transferred from the TXBn register, the shift register data is output from the TXDn pin. The transmission completion interrupt request signal (INTSTn) is generated synchronized with the completion of transmission of one frame. This register cannot be directly manipulated. (8) Transmit buffer register n (TXBn) The TXBn register is an 8-bit buffer for transmit data. A transmit operation is started by writing transmit data to the TXBn register. (9) Addition of transmission control parity A transmit operation is controlled by adding a start bit, parity bit, or stop bit to the data that is written to the TXBn register, according to the contents that were set in the ASIMn register. Figure 16-2. Block Diagram of UARTn Internal bus Asynchronous serial interface mode register n (ASIMn) Receive buffer register n (RXBn) Transmit buffer register n (TXBn) RXDn TXDn Receive shift register Transmit shift register Reception control parity check Parity Framing Overrun Addition of transmission control parity INTSTn INTSRn INTSREn Baud rate generator n Remark For the configuration of the baud rate generator, refer to Figure 16-13. 462 User's Manual U16889EJ1V0UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.4 Registers (1) Asynchronous serial interface mode register n (ASIMn) The ASIMn register is an 8-bit register that controls the UARTn transfer operation. This register can be read or written in 8-bit or 1-bit units. After reset, ASIMn is set to 01H. Cautions 1. When using UARTn, be sure to set the external pins related to UARTn functions to the control made before setting the CKSRn and BRGCn registers, and then set the UARTEn bit to 1. Then set the other bits. 2. Set the UARTEn and RXEn bits to 1 while a high level is input to the RXDn pin. If these bits are set to 1 while a low level is input to the RXDn pin, reception will be started. (1/2) After reset: 01H <7> ASIMn (n = 0 to 2) UARTEn R/W <6> TXEn Address: ASIM0 FFFFFA00H, ASIM1 FFFFFA10H, ASIM2 FFFFFA20H <5> RXEn 4 PSn1 3 PSn0 2 CLn 1 SLn 0 ISRMn UARTEn 0 1 Stop clock supply to UARTn. Supply clock to UARTn. Control of operating clock * If the UARTEn bit is cleared to 0, UARTn is asynchronously reset Note . * If the UARTEn bit = 0, UARTn is reset. To operate UARTn, first set the UARTEn bit to 1. * If the UARTEn bit is cleared from 1 to 0, all the registers of UARTn are initialized. To set the UARTEn bit to 1 again, be sure to re-set the registers of UARTn. The output of the TXDn pin goes high when transmission is disabled, regardless of the setting of the UARTEn bit. TXEn 0 1 Disable transmission Enable transmission Transmission enable/disable * Set the TXEn bit to 1 after setting the UARTEn bit to 1 at startup. Clear the UARTEn bit to 0 after clearing the TXEn bit to 0 to stop. * To initialize the transmission unit, clear (0) the TXEn bit, and after letting 2 Clock cycles (base clock) elapse, set (1) the TXEn bit again. If the TXEn bit is not set again, initialization may not be successful. (For details about the base clock, refer to 16.7.1 (1) Base clock.) Note The ASISn, ASIFn, and RXBn registers are reset. User's Manual U16889EJ1V0UD 463 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) (2/2) RXEn 0 1 Disable reception Enable reception Note Reception enable/disable * Set the RXEn bit to 1 after setting the UARTEn bit to 1 at startup. Clear the UARTEn bit to 0 after clearing the RXEn bit to 0 to stop. * To initialize the reception unit status, clear (0) the RXEn bit, and after letting 2 Clock cycles (base clock) elapse, set (1) the RXEn bit again. If the RXEn bit is not set again, initialization may not be successful. (For details about the base clock, refer to 16.7.1 (1) Base clock.) PSn1 0 0 1 1 PSn0 0 1 0 1 Transmit operation Don't output parity bit Output 0 parity Output odd parity Output even parity Receive operation Receive with no parity Receive as 0 parity Judge as odd parity Judge as even parity * To overwrite the PSn1 and PSn0 bits, first clear (0) the TXEn and RXEn bits. * If "0 parity" is selected for reception, no parity judgment is performed. Therefore, no error interrupt is generated because the ASISn.PEn bit is not set. CLn 0 1 7 bits 8 bits Specification of character length of 1 frame of transmit/receive data * To overwrite the CLn bit, first clear (0) the TXEn and RXEn bits. SLn 0 1 1 bit 2 bits Specification of stop bit length of transmit data * To overwrite the SLn bit, first clear (0) the TXEn bit. * Since reception is always done with a stop bit length of 1, the SLn bit setting does not affect receive operations. ISRMn 0 Enable/disable of generation of reception completion interrupt request signals when an error occurs Generate a reception error interrupt request signal (INTSREn) as an interrupt when an error occurs. In this case, no reception completion interrupt request signal (INTSRn) is generated. 1 Generate a reception completion interrupt request signal (INTSRn) as an interrupt when an error occurs. In this case, no reception error interrupt request signal (INTSREn) is generated. * To overwrite the ISRMn bit, first clear (0) the RXEn bit. Note When reception is disabled, the receive shift register does not detect a start bit. register are retained. No shift-in processing or transfer processing to the RXBn register is performed, and the contents of the RXBn When reception is enabled, the receive shift operation starts, synchronized with the detection of the start bit, and when the reception of one frame is completed, the contents of the receive shift register are transferred to the RXBn register. A reception completion interrupt request signal (INTSRn) is also generated in synchronization with the transfer to the RXBn register. 464 User's Manual U16889EJ1V0UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) (2) Asynchronous serial interface status register n (ASISn) The ASISn register, which consists of 3 error flag bits (PEn, FEn and OVEn), indicates the error status when UARTn reception is complete. The ASISn register is cleared to 00H by a read operation. When a reception error occurs, the RXBn register should be read and the error flag should be cleared after the ASISn register is read. This register is read-only in 8-bit units. After reset, ASISn is set to 00H. Cautions 1. When the ASIMn.UARTEn bit or ASIMn.RXEn bit is cleared to 0, or when the ASISn register is read, the PEn, FEn, and OVEn bits are cleared (0). 2. Operation using a bit manipulation instruction is prohibited. 3. When the main clock is stopped and the CPU is operating on the subclock, do not access the ASISn register using an access method that causes a wait. For details, refer to 3.4.8 (2). After reset: 00H 7 ASISn (n = 0 to 2) 0 R 6 0 Address: ASIS0 FFFFFA03H, ASIS1 FFFFFA13H, ASIS2 FFFFFA23H 5 0 4 0 3 0 2 PEn 1 FEn 0 OVEn PEn 0 1 Status flag indicating a parity error When the UARTEn or RXEn bit is cleared to 0, or after the ASISn register has been read When reception was completed, the receive data parity did not match the parity bit * The operation of the PEn bit differs according to the settings of the ASIMn.PSn1 and ASIMn.PSn0 bits. FEn 0 1 Status flag indicating framing error When the UARTEn or RXEn bit is cleared to 0, or after the ASISn register has been read When reception was completed, no stop bit was detected * For receive data stop bits, only the first bit is checked regardless of the stop bit length. OVEn 0 1 Status flag indicating an overrun error When the UARTEn or RXEn bit is cleared to 0, or after the ASISn register has been read. UARTn completed the next receive operation before reading receive data of the RXBn register. * When an overrun error occurs, the next receive data value is not written to the RXBn register and the data is discarded. User's Manual U16889EJ1V0UD 465 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) (3) Asynchronous serial interface transmit status register n (ASIFn) The ASIFn register, which consists of 2 status flag bits, indicates the status during transmission. By writing the next data to the TXBn register after data is transferred from the TXBn register to the transmit shift register, transmit operations can be performed continuously without suspension even during an interrupt interval. When transmission is performed continuously, data should be written after referencing the TXBFn bit to prevent writing to the TXBn register by mistake. This register is read-only in 8-bit or 1-bit units. After reset, ASIFn is cleared to 00H. After reset: 00H 7 ASIFn (n = 0 to 2) 0 R 6 0 Address: ASIF0 FFFFFA05H, ASIF1 FFFFFA15H, ASIF2 FFFFFA25H 5 0 4 0 3 0 2 0 <1> TXBFn <0> TXSFn TXBFn 0 Transmission buffer data flag Data to be transferred next to TXBn register does not exist (When the ASIMn.UARTEn or ASIMn.TXEn bit is cleared to 0, or when data has been transferred to the transmission shift register) 1 Data to be transferred next exists in TXBn register (Data exists in TXBn register when the TXBn register has been written to) * When transmission is performed continuously, data should be written to the TXBn register after confirming that this flag is 0. If writing to TXBn register is performed when this flag is 1, transmit data cannot be guaranteed. TXSFn 0 Transmit shift register data flag (indicates the transmission status of UARTn) Initial status or a waiting transmission (When the UARTEn or TXEn bit is cleared to 0, or when following transmission completion, the next data transfer from the TXBn register is not performed) 1 Transmission in progress (When data has been transferred from the TXBn register) * When the transmission unit is initialized, initialization should be executed after confirming that this flag is 0 following the occurrence of a transmission completion interrupt request signal (INTSTn). performed when this flag is 1, transmit data cannot be guaranteed. If initialization is 466 User's Manual U16889EJ1V0UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) (4) Receive buffer register n (RXBn) The RXBn register is an 8-bit buffer register for storing parallel data that had been converted by the receive shift register. When reception is enabled (ASIMn.RXEn bit = 1), receive data is transferred from the receive shift register to the RXBn register, synchronized with the completion of the shift-in processing of one frame. Also, a reception completion interrupt request signal (INTSRn) is generated by the transfer to the RXBn register. information about the timing for generating this interrupt request, refer to 16.6.4 Receive operation. If reception is disabled (ASIMn.RXEn bit = 0), the contents of the RXBn register are retained, and no processing is performed for transferring data to the RXBn register even when the shift-in processing of one frame is completed. Also, the INTSRn signal is not generated. When 7 bits is specified for the data length, bits 6 to 0 of the RXBn register are transferred for the receive data and the MSB (bit 7) is always 0. However, if an overrun error (ASISn.OVEn bit = 1) occurs, the receive data at that time is not transferred to the RXBn register. The RXBn register becomes FFH when a reset is input or ASIMn.UARTEn bit = 0. This register is read-only in 8-bit units. For After reset: FFH 7 RXBn (n = 0 to 2) RXBn7 R 6 RXBn6 Address: RXB0 FFFFFA02H, RXB1 FFFFFA12H, RXB2 FFFFFA22H 5 RXBn5 4 RXBn4 3 RXBn3 2 RXBn2 1 RXBn1 0 RXBn0 User's Manual U16889EJ1V0UD 467 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) (5) Transmit buffer register n (TXBn) The TXBn register is an 8-bit buffer register for setting transmit data. When transmission is enabled (ASIMn.TXEn bit = 1), the transmit operation is started by writing data to TXBn register. When transmission is disabled (TXEn bit = 0), even if data is written to TXBn register, the value is ignored. The TXBn register data is transferred to the transmit shift register, and a transmission completion interrupt request signal (INTSTn) is generated, synchronized with the completion of the transmission of one frame from the transmit shift register. For information about the timing for generating this interrupt request, refer to 16.6.2 Transmit operation. When ASIFn.TXBFn bit = 1, writing must not be performed to TXBn register. This register can be read or written in 8-bit units. After reset, TXBn is set to FFH. After reset: FFH 7 TXBn (n = 0 to 2) TXBn7 R/W 6 TXBn6 Address: TXB0 FFFFFA04H, TXB1 FFFFFA14H, TXB2 FFFFFA24H 5 TXBn5 4 TXBn4 3 TXBn3 2 TXBn2 1 TXBn1 0 TXBn0 468 User's Manual U16889EJ1V0UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.5 Interrupt Requests The following three types of interrupt request signals are generated from UARTn. * Reception error interrupt request signal (INTSREn) * Reception completion interrupt request signal (INTSRn) * Transmission completion interrupt request signal (INTSTn) The default priorities among these three types of interrupt request signals are, from high to low, reception error interrupt, reception completion interrupt, and transmission completion interrupt. Table 16-2. Generated Interrupt Request Signals and Default Priorities Interrupt Request Signal Reception error interrupt request signal (INTSREn) Reception completion interrupt request signal (INTSRn) Transmission completion interrupt request signal (INTSTn) Priority 1 2 3 (1) Reception error interrupt request signal (INTSREn) When reception is enabled, the INTSREn signal is generated according to the logical OR of the three types of reception errors explained for the ASISn register. Whether the INTSREn signal or the INTSRn signal is generated when an error occurs can be specified according to the ASIMn.ISRMn bit. When reception is disabled, the INTSREn signal is not generated. (2) Reception completion interrupt request signal (INTSRn) When reception is enabled, the INTSRn signal is generated when data is shifted in to the receive shift register and transferred to the RXBn register. The INTSRn signal can be generated in place of the INTSREn signal according to the ASIMn.ISRMn bit even when a reception error has occurred. When reception is disabled, the INTSRn signal is not generated. (3) Transmission completion interrupt request signal (INTSTn) The INTSTn signal is generated when one frame of transmit data containing 7-bit or 8-bit characters is shifted out from the transmit shift register. User's Manual U16889EJ1V0UD 469 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.6 Operation 16.6.1 Data format Full-duplex serial data transmission and reception can be performed. The transmit/receive data format consists of one data frame containing a start bit, character bits, a parity bit, and stop bits as shown in Figure 16-3. The character bit length within one data frame, the type of parity, and the stop bit length are specified according to the ASIMn register. Also, data is transferred LSB first. Figure 16-3. Format of UARTn Transmit/Receive Data 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bits Character bits * Start bit *** 1 bit * Character bits *** 7 bits or 8 bits * Parity bit *** Even parity, odd parity, 0 parity, or no parity * Stop bits *** 1 bit or 2 bits 470 User's Manual U16889EJ1V0UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.6.2 Transmit operation When the ASIMn.UARTEn bit is set to 1, a high level is output from the TXDn pin. Then, when the ASIMn.TXEn bit is set to 1, transmission is enabled, and the transmit operation is started by writing transmit data to the TXBn register. (1) Transmission enabled state This state is set by the TXEn bit. * TXEn bit = 1: Transmission enabled state * TXEn bit = 0: Transmission disabled state Since UARTn does not have a CTS (transmission enabled signal) input pin, a port should be used to confirm whether the destination is in a reception enabled state. (2) Starting a transmit operation In the transmission enabled state, a transmit operation is started by writing transmit data to the TXBn register. When a transmit operation is started, the data in the TXBn register is transferred to the transmit shift register. Then, the transmit shift register outputs data to the TXDn pin (the transmit data is transferred sequentially starting with the start bit). The start bit, parity bit, and stop bits are added automatically. (3) Transmission interrupt When the transmit shift register becomes empty, a transmission completion interrupt request signal (INTSTn) is generated. The timing for generating the INTSTn signal differs according to the specification of the stop bit length. The INTSTn signal is generated at the same time that the last stop bit is output. If the data to be transmitted next has not been written to the TXBn register, the transmit operation is suspended. Caution Normally, when the transmit shift register becomes empty, the INTSTn signal is generated. However, the INTSTn signal is not generated if the transmit shift register becomes empty due to reset. User's Manual U16889EJ1V0UD 471 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) Figure 16-4. UARTn Transmission Completion Interrupt Timing (a) Stop bit length: 1 TXDn (output) Start D0 D1 D2 D6 D7 Parity Stop INTSTn (output) (b) Stop bit length: 2 TXDn (output) Start D0 D1 D2 D6 D7 Parity Stop INTSTn (output) 472 User's Manual U16889EJ1V0UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.6.3 Continuous transmission operation UARTn can write the next transmit data to the TXBn register at the timing that the transmit shift register starts the shift operation. This enables an efficient transmission rate to be realized by continuously transmitting data even during the transmission completion interrupt service after the transmission of one data frame. In addition, reading the ASIFn.TXSFn bit after the occurrence of a transmission completion interrupt request signal (INTSTn) enables the TXBn register to be efficiently written twice (2 bytes) without waiting for the transmission of 1 data frame. When continuous transmission is performed, data should be written after referencing the ASIFn register to confirm the transmission status and whether or not data can be written to the TXBn register. Caution The values of the ASIF.TXBFn and ASIF.TXSFn bits change 10 11 01 in continuous transmission. Therefore, do not confirm the status based on the combination of the TXBFn and TXSFn bits. Read only the TXBFn bit during continuous transmission. TXBFn 0 1 Whether or Not Writing to TXBn Register Is Enabled Writing is enabled Writing is not enabled Caution When transmission is performed continuously, write the first transmit data (first byte) to the TXBn register and confirm that the TXBFn bit is 0, and then write the next transmit data (second byte) to TXBn register. If writing to the TXBn register is performed when the TXBFn bit is 1, transmit data cannot be guaranteed. The communication status can be confirmed by referring to the TXSFn bit. TXSFn 0 1 Transmission is completed. Under transmission. Transmission Status Cautions 1. When initializing the transmission unit when continuous transmission is completed, confirm that the TXSFn bit is 0 after the occurrence of the transmission completion interrupt, and then execute initialization. If initialization is performed when the TXSFn bit is 1, transmit data cannot be guaranteed. 2. While transmission is being performed continuously, an overrun error may occur if the next transmission is completed before the INTSTn interrupt servicing following the transmission of 1 data frame is executed. An overrun error can be detected by embedding a program that can count the number of transmit data and referencing TXSFn bit. User's Manual U16889EJ1V0UD 473 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) Figure 16-5. Continuous Transmission Processing Flow Set registers Write transmit data to TXBn register No When reading ASIFn register, TXBFn = 0? Yes Write second byte transmit data to TXBn register Interrupt occurrence Required number of transfers performed? No Yes No When reading ASIFn register, TXSFn = 1? Yes When reading ASIFn register, TXSFn = 0? Yes No Write transmit data to TXBn register Wait for interrupt End of transmission processing 474 User's Manual U16889EJ1V0UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) (1) Starting procedure The procedure to start continuous transmission is shown below. Figure 16-6. Continuous Transmission Starting Procedure TXDn (output) <1> INTSTn (output) Start bit <2> Data (1) Stop bit <3> Start bit <4> Data (2) Stop bit <5> TXBn register FFH Data (1) Data (2) Data (3) TXSn register ASIFn register (TXBFn, TXSFn bits) FFH 10 11Note Data (1) Data (2) Data (3) 00 01 11 01 11 01 11 Note Refer to 16.8 Cautions (2). Transmission Starting Procedure Internal Operation ASIFn Register TXBFn TXSFn 0 0 1 Note * Set transmission mode * Write data (1) <1> Start transmission unit 0 1 <2> Generate start bit 1 0 1 1 1 1 Start data (1) transmission * Read ASIFn register (confirm that TXBFn bit = 0) * Write data (2) < 0 0 1 0 0 1 1 1 1 0 0 1 1 1 1 Note Refer to 16.8 Cautions (2). User's Manual U16889EJ1V0UD 475 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) (2) Ending procedure The procedure for ending continuous transmission is shown below. Figure 16-7. Continuous Transmission End Procedure TXDn (output) <6> INTSTn (output) <7> Start bit <8> Data (m - 1) Stop bit <9> Start bit <10> Data (m) <11> Stop bit TXBn register Data (m - 1) Data (m - 1) Data (m) TXSn register ASIFn register (TXBFn, TXSFn bits) Data (m) FFH 11 01 11 01 00 UARTEn bit or TXEn bit Transmission End Procedure Internal Operation ASIFn Register TXBFn TXSFn 1 <6> Transmission of data (m - 2) is in progress <7> INTSTn interrupt occurs * Read ASIFn register (confirm that TXBFn bit = 0) * Write data (m) <8> Generate start bit Start data (m - 1) transmission < 1 0 0 1 1 1 1 0 0 1 1 0 0 0 0 476 User's Manual U16889EJ1V0UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.6.4 Receive operation The awaiting reception state is set by setting the ASIMn.UARTEn bit to 1 and then setting the ASIMn.RXEn bit to 1. To start the receive operation, start sampling at the falling edge when the falling of the RXDn pin is detected. If the RXDn pin is low level at a start bit sampling point, the start bit is recognized. When the receive operation begins, serial data is stored sequentially in the receive shift register according to the baud rate that was set. A reception completion interrupt request signal (INTSRn) is generated each time the reception of one frame of data is completed. Normally, the receive data is transferred from the RXBn register to memory by this interrupt servicing. (1) Reception enabled state The receive operation is set to the reception enabled state by setting the RXEn bit to 1. * RXEn bit = 1: Reception enabled state * RXEn bit = 0: Reception disabled state In receive disabled state, the reception hardware stands by in the initial state. At this time, the contents of the RXBn register are retained, and no reception completion interrupt or reception error interrupt is generated. (2) Starting a receive operation A receive operation is started by the detection of a start bit. The RXDn pin is sampled using the serial clock from baud rate generator n (BRGn). (3) Reception completion interrupt When the RXEn bit = 1 and the reception of one frame of data is completed (the stop bit is detected), the INTSRn signal is generated and the receive data within the receive shift register is transferred to the RXBn register at the same time. Also, if an overrun error (ASISn.OVEn bit = 1) occurs, the receive data at that time is not transferred to the RXBn register, and either the INTSRn signal or a reception error interrupt request signal (INTSREn) is generated according to the ASIMn.ISRMn bit setting. Even if a parity error (ASISn.PEn bit = 1) or framing error (ASISn.FEn bit = 1) occurs during a reception operation, the receive operation continues until stop bit is received, and after reception is completed, either the INTSRn signal or the INTSREn signal is generated according to the ISRMn bit setting (the receive data within the receive shift register is transferred to the RXBn register). If the RXEn bit is cleared (0) during a receive operation, the receive operation is immediately stopped. The contents of the RXBn register and the ASISn register at this time do not change, and the INTSRn signal or the INTSREn signal is not generated. The INTSRn signal or the INTSREn signal is not generated when the RXEn bit = 0 (reception is disabled). User's Manual U16889EJ1V0UD 477 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) Figure 16-8. UARTn Reception Completion Interrupt Timing RXDn (input) Start D0 D1 D2 D6 D7 Parity Stop INTSRn (output) RXBn register Cautions 1. Be sure to read the RXBn register even when a reception error occurs. If the RXBn register is not read, an overrun error will occur at the next data reception and the reception error status will continue infinitely. 2. Reception is always performed assuming a stop bit length of 1. A second stop bit is ignored. 16.6.5 Reception error The three types of errors that can occur during a receive operation are a parity error, framing error, and overrun error. As a result of data reception, the various flags of the ASISn register are set (1), and a reception error interrupt request signal (INTSREn) or a reception completion interrupt request signal (INTSRn) is generated at the same time. The ASIMn.ISRMn bit specifies whether the INTSREn signal or the INTSRn signal is generated. The type of error that occurred during reception can be detected by reading the contents of the ASISn register during the INTSREn or INTSRn interrupt servicing. The contents of the ASISn register are cleared (0) by reading the ASISn register. Table 16-3. Reception Error Causes Error Flag PEn Reception Error Parity error Cause The parity specification during transmission did not match the parity of the reception data No stop bit was detected The reception of the next data was completed before data was read from the RXBn register FEn OVEn Framing error Overrun error 478 User's Manual U16889EJ1V0UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) (1) Separation of reception error interrupt request signal A reception error interrupt request signal can be separated from the INTSRn signal and generated as the INTSREn signal by clearing the ISRMn bit to 0. Figure 16-9. When Reception Error Interrupt Request Signal Is Separated from INTSRn Signal (ISRMn Bit = 0) (a) No error occurs during reception (b) An error occurs during reception INTSRn signal (Reception completion interrupt) INTSREn signal (Reception error interrupt) INTSRn signal (Reception completion interrupt) INTSREn signal (Reception error interrupt) INTSRn does not occur Figure 16-10. When Reception Error Interrupt Request Signal Is Included in INTSRn Signal (ISRMn Bit = 1) (a) No error occurs during reception (b) An error occurs during reception INTSRn signal (Reception completion interrupt) INTSREn signal (Reception error interrupt) INTSRn signal (Reception completion interrupt) INTSREn signal (Reception error interrupt) INTSREn does not occur User's Manual U16889EJ1V0UD 479 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.6.6 Parity types and corresponding operation A parity bit is used to detect a bit error in communication data. Normally, the same type of parity bit is used on the transmission and reception sides. (1) Even parity (i) During transmission The parity bit is controlled so that the number of bits with the value "1" within the transmit data including the parity bit is even. The parity bit value is as follows. * If the number of bits with the value "1" within the transmit data is odd: 1 * If the number of bits with the value "1" within the transmit data is even: 0 (ii) During reception The number of bits with the value "1" within the receive data including the parity bit is counted, and a parity error is generated if this number is odd. (2) Odd parity (i) During transmission In contrast to even parity, the parity bit is controlled so that the number of bits with the value "1" within the transmit data including the parity bit is odd. The parity bit value is as follows. * If the number of bits with the value "1" within the transmit data is odd: 0 * If the number of bits with the value "1" within the transmit data is even: 1 (ii) During reception The number of bits with the value "1" within the receive data including the parity bit is counted, and a parity error is generated if this number is even. (3) 0 parity During transmission the parity bit is set to "0" regardless of the transmit data. During reception, no parity bit check is performed. Therefore, no parity error is generated regardless of whether the parity bit is "0" or "1". (4) No parity No parity bit is added to the transmit data. During reception, the receive operation is performed as if there were no parity bit. Since there is no parity bit, no parity error is generated. 480 User's Manual U16889EJ1V0UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.6.7 Receive data noise filter The RXDn signal is sampled at the rising edge of the prescaler output base clock (fUCLK). If the same sampling value is obtained twice, the match detector output changes, and this output is sampled as input data. Therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (refer to Figure 16-12). Refer to 16.7.1 (1) Base clock regarding the base clock. Also, since the circuit is configured as shown in Figure 16-11, internal processing during a receive operation is delayed by up to 2 clocks according to the external signal status. Figure 16-11. Noise Filter Circuit Base clock fUCLK RXDn In Q Internal signal A In LD_EN Q Internal signal B Match detector Figure 16-12. Timing of RXDn Signal Judged as Noise Base clock RXDn (input) Internal signal A Match Mismatch (judged as noise) Match Mismatch (judged as noise) Internal signal B User's Manual U16889EJ1V0UD 481 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.7 Dedicated Baud Rate Generator n (BRGn) A dedicated baud rate generator, which consists of a source clock selector and an 8-bit programmable counter, generates serial clocks during transmission/reception by UARTn. The dedicated baud rate generator output can be selected as the serial clock for each channel. Separate 8-bit counters exist for transmission and for reception. 16.7.1 Baud rate generator n (BRGn) configuration Figure 16-13. Configuration of Baud Rate Generator n (BRGn) UARTEn fXXNote 1 fXX/2Note 2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 fXX/1,024 ASCK0Note 3 Match detector 1/2 Baud rate Selector fUCLK 8-bit counter UARTEn and TXEn bits (or RXEn bit) CKSRn: TPSn3 to TPSn0 BRGCn: MDLn7 to MDLn0 Notes 1. Set fXX so as to satisfy the following conditions. * VDD = 4.0 to 5.5 V: fXX 12 MHz * VDD = 2.7 to 4.0 V: fXX 6 MHz 2. 3. Remark Set fXX so as to satisfy the following conditions. VDD = 2.7 to 4.0 V: fXX 12 MHz ASCK0 pin input can be used only by UART0. fXX: Main clock frequency (1) Base clock When the ASIMn.UARTEn bit = 1, the clock selected according to the CKSRn.TPSn3 to CKSRn.TPSn0 bits is supplied to the transmission/reception unit. This clock is called the base clock (fUCLK). When the UARTEn bit = 0, fUCLK is fixed to low level. 482 User's Manual U16889EJ1V0UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.7.2 Serial clock generation A serial clock can be generated according to the settings of the CKSRn and BRGCn registers. The base clock to the 8-bit counter is selected by the CKSRn.TPSn3 to CKSRn.TPSn0 bits. The 8-bit counter divisor value can be set by the BRGCn.MDLn7 to BRGCn.MDLn0 bits. (1) Clock select register n (CKSRn) The CKSRn register is an 8-bit register for selecting the basic block using the TPSn3 to TPSn0 bits. The clock selected by the TPSn3 to TPSn0 bits becomes the base clock (fUCLK) of the transmission/reception module. This register can be read or written in 8-bit units. After reset, CKSRn is cleared to 00H. Caution Clear the ASIMn.UARTEn bit to 0 before rewriting the TPSn3 to TPSn0 bits. After reset: 00H 7 CKSRn (n = 0 to 2) 0 R/W 6 0 Address: CKSR0 FFFFFA06H, CKSR1 FFFFFA16H, CKSR2 FFFFFA26H 5 0 4 0 3 TPSn3 2 TPSn2 1 TPSn1 0 TPSn0 TPSn3 0 0 0 0 0 0 0 0 1 1 1 1 TPSn2 0 0 0 0 1 1 1 1 0 0 0 0 TPSn1 0 0 1 1 0 0 1 1 0 0 1 1 TPSn0 0 1 0 1 0 1 0 1 0 1 0 1 fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 fXX/1,024 External clock Note 2 Base clock (fUCLK) Note 1 (ASCK0 pin) Other than above Setting prohibited Notes 1. Set fUCLK so as to satisfy the following conditions. * REGC = VDD = 4.0 to 5.5 V: fUCLK 12 MHz * REGC = Capacity, VDD = 4.0 to 5.5 V: fUCLK 6 MHz * REGC = VDD = 2.7 to 4.0 V: fUCLK 6 MHz 2. ASCK0 pin input clock can be used only by UART0. Setting of UART1 and UART2 is prohibited. Remark fXX: Main clock frequency User's Manual U16889EJ1V0UD 483 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) (2) Baud rate generator control register n (BRGCn) The BRGCn register is an 8-bit register that controls the baud rate (serial transfer speed) of UARTn. This register can be read or written in 8-bit units. After reset, BRGCn is set to FFH. Caution If the MDLn7 to MDLn0 bits are to be overwritten, the ASIMn.TXEn and ASIMn.RXEn bits should be cleared to 0 first. After reset: FFH 7 BRGCn (n = 0 to 2) MDLn7 R/W 6 MDLn6 Address: BRGC0 FFFFFA07H, BRGC1 FFFFFA17H, BRGC2 FFFFFA27H 5 MDLn5 4 MDLn4 3 MDLn3 2 MDLn2 1 MDLn1 0 MDLn0 MDLn7 MDLn6 MDLn5 MDLn4 MDLn3 MDLn2 MDLn1 MDLn0 Set value (k) 0 0 0 0 ... 0 0 0 0 ... 0 0 0 0 ... 0 0 0 0 ... 0 1 1 1 ... x 0 0 0 ... x 0 0 1 ... x 0 1 0 ... - 8 9 10 ... Serial clock Setting prohibited fUCLK/8 fUCLK/9 fUCLK/10 ... fUCLK/250 fUCLK/251 fUCLK/252 fUCLK/253 fUCLK/254 fUCLK/255 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 250 251 252 253 254 255 Remarks 1. fUCLK: Frequency [Hz] of base clock selected by CKSR0.TPSn3 to CKSR0.TPSn0 bits 2. k: Value set by MDLn7 to MDLn0 bits (k = 8, 9, 10, ..., 255) 3. The baud rate is the output clock for the 8-bit counter divided by 2. 4. x: don't care 484 User's Manual U16889EJ1V0UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) (3) Baud rate The baud rate is the value obtained by the following formula. Baud rate [bps] = fUCLK 2xk fUCLK = Frequency [Hz] of base clock selected by CKSRn.TPSn3 to CKSRn.TPSn0 bits. k = Value set by BRGCn.MDLn7 to BRGCn.MDLn0 bits (k = 8, 9, 10, ..., 255) (4) Baud rate error The baud rate error is obtained by the following formula. Error (%) = Actual baud rate (baud rate with error) Target baud rate (normal baud rate) -1 x 100 [%] Cautions 1. Make sure that the baud rate error during transmission does not exceed the allowable error of the reception destination. 2. Make sure that the baud rate error during reception is within the allowable baud rate range during reception, which is described in 16.7.4 during reception. Allowable baud rate range Example: Base clock frequency = 10 MHz = 10,000,000 Hz Setting of BRGCn.MDLn7 to BRGCn.MDLn0 bits = 00100001B (k = 33) Target baud rate = 153,600 bps Baud rate = 10,000,000/(2 x 33) = 151,515 [bps] Error = (151,515/153,600 - 1) x 100 = -1.357 [%] User's Manual U16889EJ1V0UD 485 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.7.3 Baud rate setting example Table 16-4. Baud Rate Generator Setting Data fXX = 20 MHz fUCLK fXX/512 fXX/256 fXX/128 fXX/64 fXX/32 fXX/16 fXX/64 fXX/8 fXX/32 fXX/32 fXX/2 fXX/4 fXX/16 fXX/2 fXX/16 fXX/2 fXX/2 fXX/2 fXX/4 k 41H (65) 41H (65) 41H (65) 41H (65) 41H (65) 41H (65) 0FH (15) 41H (65) 0DH (13) 0AH (10) 95H (149) 41H (65) 0DH (13) 59H (89) 0AH (10) 41H (65) 2BH (43) 21H (33) 08H (8) ERR 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -0.13 0.16 0.16 0.32 0.00 0.16 0.94 -1.36 0 fUCLK fXX/1024 fXX/1024 fXX/512 fXX/256 fXX/128 fXX/64 fXX/64 fXX/32 fXX/2 fXX/32 fXX/2 fXX/16 fXX/2 fXX/2 fXX/16 fXX/8 fXX/2 fXX/4 fXX/2 fXX = 16 MHz k 1AH (26) 0DH (13) 0DH (13) 0DH (13) 0DH (13) 0DH (13) 0CH (12) 0DH (13) A7H (167) 08H (8) 77H (119) 0DH (13) 53H (83) 47H (71) 08H (8) 0DH (13) 23H (35) 0DH (13) 0DH (13) ERR 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -0.20 0.00 0.04 0.16 0.40 0.60 0.00 0.16 -0.79 0.16 -1.54 fUCLK fXX/256 fXX/128 fXX/64 fXX/32 fXX/16 fXX/8 fXX/32 fXX/4 fXX/16 fXX/16 fXX fXX/2 fXX/8 fXX fXX/8 fXX fXX fXX fXX/2 fXX = 10 MHz k 41H (65) 41H (65) 41H (65) 41H (65) 41H (65) 41H (65) 0FH (15) 41H (65) 0DH (13) 0AH (10) 95H (149) 41H (65) 0DH (13) 59H (89) 0AH (10) 41H (65) 2BH (43) 21H (33) 08H (8) ERR 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0 -0.13 0.16 0.16 0.32 0.00 0.16 0.94 -1.36 0.00 Baud Rate (bps) 300 600 1200 2400 4800 9600 10400 19200 24000 31250 33600 38400 48000 56000 62500 76800 115200 153600 312500 Caution The allowable frequency of the base clock (fUCLK) is as follows. * REGC = VDD = 4.0 to 5.5 V: fUCLK 12 MHz * REGC = Capacity, VDD = 4.0 to 5.5 V: fUCLK 6 MHz * REGC = VDD = 2.7 to 4.0 V: fUCLK 6 MHz Remark fXX: fUCLK: k: ERR: Main clock frequency Base clock frequency Set values of BRGCn.MDLn7 to BRGCn.MDLn0 bits Baud rate error [%] n = 0 to 2 486 User's Manual U16889EJ1V0UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.7.4 Allowable baud rate range during reception The degree to which a discrepancy from the transmission destination's baud rate is allowed during reception is shown below. Caution The equations described below should be used to set the baud rate error during reception so that it always is within the allowable error range. Figure 16-14. Allowable Baud Rate Range During Reception Latch timing UARTn transfer rate Start bit Bit 0 FL Bit 1 Bit 7 Parity bit Stop bit 1 data frame (11 x FL) Minimum allowable transfer rate Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmin Maximum allowable transfer rate Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmax As shown in Figure 16-14, after the start bit is detected, the receive data latch timing is determined according to the counter that was set by the BRGCn register. If all data up to the final data (stop bit) is in time for this latch timing, the data can be received normally. If this is applied to 11-bit reception, the following is theoretically true. FL = (Brate) -1 Brate: UARTn baud rate k: FL: BRGCn register set value 1-bit data length When the latch timing margin is 2 base clocks, the minimum allowable transfer rate (FLmin) is as follows. FL min = 11x FL - k-2 2k x FL = 21k + 2 2k FL User's Manual U16889EJ1V0UD 487 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) Therefore, the transfer destination's maximum receivable baud rate (BRmax) is as follows. BRmax = (FLmin/11)-1 = 22k 21k + 2 Brate Similarly, the maximum allowable transfer rate (FLmax) can be obtained as follows. 10 k+2 21k - 2 x FL max = 11x FL - x FL = FL 11 2xk 2xk 21k - 2 FL max = FL x 11 20k Therefore, the transfer destination's minimum receivable baud rate (BRmin) is as follows. BRmin = (FLmax/11)-1 = 20k 21k - 2 Brate The allowable baud rate error of UARTn and the transfer destination can be obtained as follows from the expressions described above for computing the minimum and maximum baud rate values. Table 16-5. Maximum and Minimum Allowable Baud Rate Error Division Ratio (k) Maximum Allowable Baud Rate Error 8 20 50 100 255 +3.53% +4.26% +4.56% +4.66% +4.72% Minimum Allowable Baud Rate Error -3.61% -4.31% -4.58% -4.67% -4.73% Remarks 1. The reception precision depends on the number of bits in one frame, the base clock frequency, and the division ratio (k). The higher the base clock frequency and the larger the division ratio (k), the higher the precision. 2. k: BRGCn register set value 488 User's Manual U16889EJ1V0UD CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART) 16.7.5 Transfer rate during continuous transmission During continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks of the base clock longer than normal. However, on the reception side, the transfer result is not affected since the timing is initialized by the detection of the start bit. Figure 16-15. Transfer Rate During Continuous Transmission 1 data frame Start bit of second byte Bit 7 Parity bit Stop bit Start bit Bit 0 Bit 1 Start bit FL Bit 0 FL FL FL FL FL FLstp FL Representing the 1-bit data length by FL, the stop bit length by FLstp, and the base clock frequency by fUCLK yields the following equation. FLstp = FL + 2/fUCLK Therefore, the transfer rate during continuous transmission is as follows (when the stop bit length = 1). Transfer rate = 11 x FL + (2/fUCLK) 16.8 Cautions Cautions to be observed when using UARTn are shown below. (1) When the supply of clocks to UARTn is stopped (for example, in IDLE or STOP mode), operation stops with each register retaining the value it had immediately before the supply of clocks was stopped. The TXDn pin output also holds and outputs the value it had immediately before the supply of clocks was stopped. However, operation is not guaranteed after the supply of clocks is restarted. Therefore, after the supply of clocks is restarted, the circuits should be initialized by clearing the ASIMn.UARTEn, ASIMn.RXEn, and ASIMn.TXEn bits to 000. (2) UARTn has a 2-stage buffer configuration consisting of the TXBn register and the transmission shift register, and has status flags (ASIFn.TXBFn and ASIFn.TXSFn bits) that indicate the status of each buffer. If the TXBFn and TXSFn bits are read in continuous transmission, the value changes 10 11 01. For the timing to write the next data to the TXBn register, read only the TXBFn bit during continuous transmission. User's Manual U16889EJ1V0UD 489 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) In the V850ES/KJ1, three channels of clocked serial interface 0 (CSI0) are provided. 17.1 Features * * * * * * Maximum transfer speed: 5 Mbps Master mode/slave mode selectable Transmission data length: 8 bits or 16 bits can be set MSB/LSB-first selectable for transfer data Eight clock signals can be selected (7 master clocks and 1 slave clock) 3-wire type SO0n: SI0n: Serial transmit data output Serial receive data input SCK0n: Serial clock I/O * Interrupt sources: 1 type * Transmission/reception completion interrupt request signal (INTCSI0n) * Transmission/reception mode or reception-only mode selectable * Two transmission buffer registers (SOTBFn/SOTBFLn, SOTBn/SOTBLn) and two reception buffer registers (SIRBn/SIRBLn, SIRBEn/SIRBELn) are provided on chip * Single transfer mode/continuous transfer mode selectable Remark n = 0 to 2 490 User's Manual U16889EJ1V0UD CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) 17.2 Configuration CSI0n is controlled via the CSIM0n register. (1) Clocked serial interface mode register 0n (CSIM0n) The CSIM0n register is an 8-bit register that specifies the operation of CSI0n. (2) Clocked serial interface clock selection register n (CSICn) The CSICn register is an 8-bit register that controls the CSI0n serial transfer operation. (3) Serial I/O shift register 0n (SIO0n) The SIO0n register is a 16-bit shift register that converts parallel data into serial data. The SIO0n register is used for both transmission and reception. Data is shifted in (reception) and shifted out (transmission) from the MSB or LSB side. The actual transmission/reception operations are started up by accessing the buffer register. (4) Serial I/O shift register 0nL (SIO0nL) The SIO0nL register is an 8-bit shift register that converts parallel data into serial data. The SIO0nL register is used for both transmission and reception. Data is shifted in (reception) and shifted out (transmission) from the MSB or LSB side. The actual transmission/reception operations are started up by access of the buffer register . (5) Clocked serial interface receive buffer register n (SIRBn) The SIRBn register is a 16-bit buffer register that stores receive data. (6) Clocked serial interface receive buffer register nL (SIRBnL) The SIRBnL register is an 8-bit buffer register that stores receive data. (7) Clocked serial interface read-only receive buffer register n (SIRBEn) The SIRBEn register is a 16-bit buffer register that stores receive data. The SIRBEn register is the same as the SIRBn register. It is used to read the contents of the SIRBn register. (8) Clocked serial interface read-only receive buffer register nL (SIRBEnL) The SIRBEnL register is an 8-bit buffer register that stores receive data. The SIRBEnL register is the same as the SIRBnL register. It is used to read the contents of the SIRBnL register. (9) Clocked serial interface transmit buffer register n (SOTBn) The SOTBn register is a 16-bit buffer register that stores transmit data. (10) Clocked serial interface transmit buffer register nL (SOTBLnL) The SOTBnL register is an 8-bit buffer register that stores transmit data. (11) Clocked serial interface initial transmit buffer register n (SOTBFn) The SOTBFn register is a 16-bit buffer register that stores the initial transmit data in the continuous transfer mode. User's Manual U16889EJ1V0UD 491 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) (12) Clocked serial interface initial transmit buffer register nL (SOTBFnL) The SOTBFnL register is an 8-bit buffer register that stores initial transmit data in the continuous transfer mode. (13) Selector The selector selects the serial clock to be used. (14) Serial clock controller Controls the serial clock supply to the shift register. Also controls the clock output to the SCK0n pin when the internal clock is used. (15) Serial clock counter Counts the serial clock output or input during transmission/reception, and checks whether 8-bit or 16-bit data transmission/reception has been performed. (16) Interrupt controller Controls the interrupt request timing. Remark n = 0 to 2 492 User's Manual U16889EJ1V0UD CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) Figure 17-1. Block Diagram of Clocked Serial Interface fXX/26 fXX/25 fXX/24 fXX/23 fXX/22 fXX/2 TO50, TO51 SCK0n Selector Serial clock controller Clock start/stop control & clock phase control SCK0n Interrupt controller INTCSI0n Transmission control Transmission data control Initial transmit buffer register (SOTBFn/SOTBFnL) Control signal SO selection SO0n Transmit buffer register (SOTBn/SOTBnL) SI0n Shift register (SIOn/SIO0nL) SO latch Receive buffer register (SIRBn/SIRBnL) Remarks 1. n = 0 to 2 2. fXX: Main clock User's Manual U16889EJ1V0UD 493 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) 17.3 Registers (1) Clocked serial interface mode register 0n (CSIM0n) The CSIM0n register controls the CSI0n operation. This register can be read or written in 8-bit or 1-bit units (however, CSOTn bit is read-only). After reset, CSIM0n is cleared to 00H. Caution Overwriting the CSIM0n.TRMDn, CSIM0n.CCLn, CSIM0n.DIRn, CSIM0n.CSITn, and CSIM0n.AUTOn bits can be done only when the CSOTn bit = 0. If these bits are overwritten at any other time, the operation cannot be guaranteed. 494 User's Manual U16889EJ1V0UD CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) After reset: 00H <7> CSIM0n (n = 0 to 2) CSI0En R/W <6> TRMDn Address: CSIM00 FFFFFD00H, CSIM01 FFFFFD10H, CSIM02 FFFFFD20H 5 CCLn <4> DIRn 3 CSITn 2 AUTOn 1 0 <0> CSOTn CSI0En 0 1 Disable CSI0n operation. Enable CSI0n operation. Note CSI0n operation enable/disable The internal CSI0n circuit can be reset asynchronously by clearing the CSI0En bit to 0. For the SCK0n and SO0n pin output status when the CSI0En bit = 0, refer to 17.5 Output Pins. TRMDn 0 1 Receive-only mode Transmission/reception mode Specification of transmission/reception mode When the TRMDn bit = 0, reception is performed and the SO0n pin outputs a low level. Data reception is started by reading the SIRBn register. When the TRMDn bit = 1, transmission/reception is started by writing data to the SOTBn register. CCLn 0 1 8 bits 16 bits Specification of data length DIRn 0 1 Specification of transfer direction mode (MSB/LSB) First bit of transfer data is MSB First bit of transfer data is LSB CSITn 0 1 No delay Control of delay of interrupt request signal Delay mode (interrupt request signal is delayed 1/2 cycle compared to the serial clock) The delay mode (CSITn bit = 1) is valid only in the master mode (CSICn.CKS0n2 to CSICn.CSK0n0 bits are not 111B). In the slave mode (CKS0n2 to CKS0n0 bits are 111B), do not set the delay mode. AUTOn 0 1 Specification of single transfer mode or continuous transfer mode Single transfer mode Continuous mode CSOTn 0 1 Communication stopped Communication in progress Communication status flag The CSOTn bit is cleared (0) by writing 0 to the CSI0En bit. Note The CSOTn bit and the SIRBn, SIRBnL, SIRBE, SIRBEnL, SIOn, and SIOnL registers are reset. User's Manual U16889EJ1V0UD 495 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) (2) Clocked serial interface clock selection register n (CSICn) The CSICn register is an 8-bit register that controls the CSI0n transfer operation. This register can be read or written in 8-bit or 1-bit units. After reset, CSICn is cleared to 00H. Caution The CSICn register can be overwritten only when the CSIM0n.CSI0En bit = 0. After reset: 00H 7 CSICn (n = 0 to 2) CKPn 0 DAPn 0 R/W 6 0 Address: CSIC0 FFFFFD01H, CSIC1 FFFFFD11H, CSIC2 FFFFFD21H 5 0 4 CKPn 3 DAPn 2 CKS0n2 1 CKS0n1 0 CKS0n0 0 Specification of timing of transmitting/receiving data to/from SCK0n (Type 1) SCK0n (I/O) SO0n (output) SI0n (input) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 0 1 (Type 2) SCK0n (I/O) SO0n (output) SI0n (input) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 1 0 (Type 3) SCK0n (I/O) SO0n (output) SI0n (input) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 1 1 (Type 4) SCK0n (I/O) SO0n (output) SI0n (input) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 CKS0n2 CKS0n1 CKS0n0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 2 Serial clock Note 1 Mode Master mode Master mode Master mode Master mode Master mode Master mode Note 2 3 4 5 6 Clock generated by TO50, TO51 External clock (SCK0n pin) Master mode Slave mode Notes 1. Set the serial clock so as to satisfy the following conditions. * REGC = VDD = 4.0 to 5.5 V: Serial clock 5 MHz * REGC = Capacity, VDD = 4.0 to 5.5 V: Serial clock 2.5 MHz * REGC = VDD = 2.7 to 4.0 V: Serial clock 2.5 MHz 2. CSI00: TO50 CSI01, CSI02: TO51 Remark fXX: Main clock frequency 496 User's Manual U16889EJ1V0UD CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) (3) Clocked serial interface receive buffer registers n, nL (SIRBn, SIRBnL) The SIRBn register is a 16-bit buffer register that stores receive data. When the receive-only mode is set (CSIM0n.TRMDn bit = 0), the reception operation is started by reading data from the SIRBn register. This register is read-only in 16-bit units. When the lower 8 bits are used as the SIRBnL register, this register is read-only in 8-bit units. In addition to reset input, this register can also be initialized by clearing (0) the CSIM0n.CSI0En bit. Cautions 1. Read the SIRBn register only when a 16-bit data length has been set (CSIM0n.CCLn bit = 1). Read the SIRBnL register only when an 8-bit data length has been set (CCLn bit = 0). 2. When the single transfer mode has been set (CSIM0n.AUTOn bit = 0), perform a read operation only in the idle state (CSIM0n.CSOTn bit = 0). If the SIRBn or SIRBnL register is read during data transfer, the data cannot be guaranteed. (a) SIRBn register After reset: 0000H 15 SIRBn (n = 0 to 2) 14 13 R 12 Address: SIRB0 FFFFFD02H, SIRB1 FFFFFD12H, SIRB2 FFFFFD22H 11 10 9 8 7 6 5 4 3 2 1 0 SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn SIRBn 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (b) SIRBnL register After reset: 00H 7 SIRBnL (n = 0 to 2) SIRBn7 R 6 SIRBn6 Address: SIRB0L FFFFFD02H, SIRB1L FFFFFD12H, SIRB2L FFFFFD22H 5 SIRBn5 4 SIRBn4 3 SIRBn3 2 SIRBn2 1 SIRBn1 0 SIRBn0 User's Manual U16889EJ1V0UD 497 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) (4) Clocked serial interface read-only receive buffer registers n, nL (SIRBEn, SIRBEnL) The SIRBEn register is a 16-bit buffer register that stores receive data. The SIRBEn register is the same as the SIRBn register. Even if the SIRBEn register is read, the next operation will not start. The SIRBEn register is used to read the contents of the SIRBn register when the serial reception is not continued. This register is read-only in 16-bit units. However, when the lower 8 bits are used as the SIRBEnL register, the register is read-only in 8-bit units. In addition to reset input, this register can also be initialized by clearing (0) the CSIM0n.CSI0En bit. Cautions 1. The receive operation is not started even if data is read from the SIRBEn and SIRBEnL registers. 2. The SIRBEn register can be read only if a 16-bit data length has been set (CSIM0n.CCLn bit = 1). The SIRBEnL register can be read only if an 8-bit data length has been set (CCLn bit = 0). (a) SIRBEn register After reset: 0000H 15 SIRBEn (n = 0 to 2) 14 R 13 Address: SIRBE0 FFFFFD06H, SIRBE1 FFFFFD16H, SIRBE2 FFFFFD26H 12 11 10 9 8 7 6 5 4 3 2 1 0 SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn SIRBEn 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (B) SIRBEnL register After reset: 00H 7 SIRBEnL (n = 0 to 2) R 6 Address: SIRBE0L FFFFFD06H, SIRBE1L FFFFFD16H, SIRBE2L FFFFFD26H 5 4 3 2 1 0 SIRBEn7 SIRBEn6 SIRBEn5 SIRBEn4 SIRBEn3 SIRBEn2 SIRBEn1 SIRBEn0 498 User's Manual U16889EJ1V0UD CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) (5) Clocked serial interface transmit buffer registers n, nL (SOTBn, SOTBnL) The SOTBn register is a 16-bit buffer register that stores transmit data. When the transmission/reception mode is set (CSIM0n.TRMDn bit = 1), the transmission operation is started by writing data to the SOTBn register. This register can be read or written in 16-bit units. However, when the lower 8 bits are used as the SOTBnL register, the register is read-only in 8-bit units. After reset, this register is initialized. Cautions 1. Access the SOTBn register only when a 16-bit data length has been set (CSIM0n.CCLn bit = 1). Access the SOTBnL register only when an 8-bit data length has been set (CCLn bit = 0). 2. When the single transfer mode is set (CSIM0n.AUTOn bit = 0), perform access only in the idle state (CSIM0n.CSOTn bit = 0). If the SOTBn and SOTBnL registers are accessed during data transfer, the data cannot be guaranteed. (a) SOTBn register After reset: 0000H 15 SOTBn (n = 0 to 2) 14 R/W 13 12 Address: SOTB0 FFFFFD04H, SOTB1 FFFFFD14H, SOTB2 FFFFFD24H 11 10 9 8 7 6 5 4 3 2 1 0 SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn SOTBn 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (b) SOTBnL register After reset: 00H 7 SOTBnL (n = 0 to 2) R/W 6 Address: SOTB0L FFFFFD04H, SOTB1L FFFFFD14H, SOTB2L FFFFFD24H 5 4 3 2 1 0 SOTBn7 SOTBn6 SOTBn5 SOTBn4 SOTBn3 SOTBn2 SOTBn1 SOTBn0 User's Manual U16889EJ1V0UD 499 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) (6) Clocked serial interface initial transmit buffer registers n, nL (SOTBFn, SOTBFnL) The SOTBFn register is a 16-bit buffer register that stores initial transmission data in the continuous transfer mode. The transmission operation is not started even if data is written to the SOTBFn register. This register can be read or written in 16-bit units. However, when the lower 8 bits are used as the SOTBFnL register, the register can be read or written in 8-bit units. After reset, this register is initialized. Caution Access the SOTBFn register and SOTBFnL register only when a 16-bit data length has been set (CSIM0n.CCLn bit = 1), and only when an 8-bit data length has been set (CCLn bit = 0), respectively, and only in the idle state (CSIM0n.CSOTn bit = 0). If the SOTBFn and SOTBFnL registers are accessed during data transfer, the data cannot be guaranteed. (a) SOTBFn register After reset: 0000H 15 SOTBFn (n = 0 to 2) 14 R/W 13 12 Address: SOTBF0 FFFFFD08H, SOTBF1 FFFFFD18H, SOTBF2 FFFFFD28H 11 10 9 8 7 6 5 4 3 2 1 0 SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn SOTBFn 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (b) SOTBFnL register After reset: 00H 7 SOTBFnL (n = 0 to 2) R/W 6 Address: SOTBF0L FFFFFD08H, SOTBF1L FFFFFD18H, SOTBF2L FFFFFD28H 5 4 3 2 1 0 SOTBFn7 SOTBFn6 SOTBFn5 SOTBFn4 SOTBFn3 SOTBFn2 SOTBFn1 SOTBFn0 500 User's Manual U16889EJ1V0UD CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) (7) Serial I/O shift registers n, nL (SIO0n, SIO0nL) The SIO0n register is a 16-bit shift register that converts parallel data into serial data. The transfer operation is not started even if the SIO0n register is read. This register is read-only in 16-bit units. However, when the lower 8 bits are used as the SIO0nL register, the register is read-only in 8-bit units. In addition to reset input, this register can also be initialized by clearing (0) the CSIM0n.CSI0En bit. Caution Read the SIO0n register and SIO0nL register only when a 16-bit data length has been set (CSIM0n.CCLn bit = 1), and only when an 8-bit data length has been set (CCLn bit = 0), respectively, and only in the idle state (CSIM0n.CSOTn bit = 0). If the SIO0n and SIO0nL registers are read during data transfer, the data cannot be guaranteed. (a) SIO0n register After reset: 0000H 15 SIO0n (n = 0 to 2) 14 13 R 12 Address: SIO00 FFFFFD0AH, SIO01 FFFFFD1AH, SIO02 FFFFFD2AH 11 10 9 8 7 6 5 4 3 2 1 0 SIOn15 SIOn14 SIOn13 SIOn12 SIOn11 SIOn10 SIOn9 SIOn8 SIOn7 SIOn6 SIOn5 SIOn4 SIOn3 SIOn2 SIOn1 SIOn0 (b) SIO0nL register After reset: 00H 7 SIO0nL (n = 0 to 2) SIOn7 R 6 SIOn6 Address: SIO00L FFFFFD0AH, SIO01L FFFFFD1AH, SIO02L FFFFFD2AH 5 SIOn5 4 SIOn4 3 SIOn3 2 SIOn2 1 SIOn1 0 SIOn0 User's Manual U16889EJ1V0UD 501 502 Register Name SIRBn (SIRBnL) R/W Transmission/Reception Mode Read Function Storing received dataNote 2 Use method When transmission and reception are complete, read the received data from this register. SIRBEn (SIRBEnL) Read Function Use method Not used. - User's Manual U16889EJ1V0UD SIO0n (SIO0nL) Read Function Use method Not used. - SOTBn (SOTBnL) Write Function Use method SOTBFn (SOTBFnL) Write Function Use method Not used Table 17-1. Use of Each Buffer Register Single Transfer Receive-Only Mode * Reading starts reception * Storing received data * First, read dummy data and start transfer. * To perform reception of the next data after reception is complete, read the received data from this register. Continuous TransferNote 1 Transmission/Reception Mode Storing up to the (N - 1)th received data (other than the last)Note 2 When reception is complete, read the received data from this register. Repeat this operation until the (N - 1)th data has been received. Receive-Only Mode * Reading starts reception * Storing up to the (N - 2)th data (other than the last two) When reception is complete, read the received data from this register. Repeat this operation until the (N - 2)th data has been received. (Supplement) Do not read the (N - 1)th data from this register. If read, a reception operation starts and continuous transfer cannot be completed. Storing the (N - 1)th received dataNote 2 Read the (N - 1)th received data from this register when the (N - 1)th or Nth (last) data has been received. Storing the Nth (last) received dataNote 2 When the Nth (last) data has been received, read the Nth (last) data. - CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) Storing the data received lastNote 2 If reception of the next data will not be performed after reception is complete, read the received data from this register. - Not used Not used - Storing the Nth (last) received dataNote 2 When the Nth (last) transmission/reception is complete, read the Nth (last) data. * Starting transmission/reception when written * Storing the data to be transmitted * First, write a dummy data (FFH) to start transmission/reception. * When transmission/reception is complete, write the data to be transmitted next. - - * Starting transmission/reception when written * Storing the data to be transmitted second and subsequently When transmission/reception is complete, write the data to be transmitted next to this register to start the next transmission/reception. Not used Not used - Not used Storing the data to be transmitted firstNote 2 Before starting transmission/reception (writing to SOTBn), write the data to be transmitted first. Not used - Notes 1. It is assumed that the number of data to be transmitted is N. 2. Neither reading nor writing will start communication. Remark In the 16-bit mode, the registers not enclosed in parentheses are used; in the 8-bit mode, the registers in parentheses are used. CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) 17.4 Operation 17.4.1 Transmission/reception completion interrupt request signal (INTCSI0n) The INTCSI0n signal is set (1) upon completion of data transmission/reception. Writing to the CSIM0n register clears (0) the INTCSI0n signal. Caution The delay mode (CSIM0n.CSITn bit = 1) is valid only in the master mode (CSICn.CKS0n2 to CSICn.CKS0n0 bits are not 111B). The delay mode cannot be set when the slave mode is set (CKS0n2 to CKS0n0 bits = 111B). User's Manual U16889EJ1V0UD 503 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) Figure 17-2. Timing Chart of INTCSI0n Signal Output in Delay Mode (a) Transmit/receive type 1 Input clock SCK0n (I/O) SI0n (input) DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO0n (output) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Reg_R/W INTCSI0n signal CSOTn bit Delay (b) Transmit/receive type 4 Input clock SCK0n (I/O) SI0n (input) DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO0n (output) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Reg_R/W INTCSI0n signal CSOTn bit Delay Remarks 1. Reg_R/W: Internal signal. This signal indicates that the SIRBn/SIRBnL register read or the SOTBn/SOTBnL register write was performed. 2. n = 0 to 2 504 User's Manual U16889EJ1V0UD CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) 17.4.2 Single transfer mode (1) Usage In the receive-only mode (CSIM0n.TRMDn bit = 0), communication is started by reading the SIRBn/SIRBnL register. In the transmission/reception mode (TRMDn bit = 1), communication is started by writing to the SOTBn/SOTBnL register. In the slave mode, the operation must be enabled beforehand (CSIM0n.CSI0En bit = 1). When communication is started, the value of the CSIM0n.CSOTn bit becomes 1 (transmission execution status). Upon communication completion, the transmission/reception completion interrupt request signal (INTCSI0n) is generated, and the CSOTn bit is cleared (0). The next data communication request is then waited for. Caution Remark When the CSOTn bit = 1, do not manipulate the CSI0n register. n = 0 to 2 User's Manual U16889EJ1V0UD 505 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) Figure 17-3. Timing Chart in Single Transfer Mode (1/2) (a) In transmission/reception mode, data length: 8 bits, transfer direction: MSB first, no interrupt delay, single transfer mode, when AAH is received and 55H is transmitted, transmit/receive type 1 SCK0n (I/O) SO0n (output) 0 1 0 1 0 1 0 1 (55H) SI0n (input) 1 0 1 0 1 0 1 0 (AAH) Reg_R/W SOTBnL register SIO0nL register SIRBnL register Write 55H to SOTBnL register 55H (transmit data) ABH 56H ADH 5AH B5H 6AH D5H AAH AAH CSOTn bit INTCSI0n signal Remarks 1. Reg_R/W: Internal signal. This signal indicates that the SIRBn/SIRBnL register read or the SOTBn/SOTBnL register write was performed. 2. For the transmit/receive types, refer to 17.3 (2) register n (CSICn). 3. n = 0 to 2 Clocked serial interface clock selection 506 User's Manual U16889EJ1V0UD CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) Figure 17-3. Timing Chart in Single Transfer Mode (2/2) (b) In transmission/reception mode, data length: 8 bits, transfer direction: MSB first, no interrupt delay, single transfer mode, when AAH is received and 55H is transmitted, transmit/receive type 2 SCK0n (I/O) SO0n (output) 0 1 0 1 0 1 0 1 (55H) SI0n (input) 1 0 1 0 1 0 1 0 (AAH) Reg_R/W SOTBnL register SIO0nL register SIRBnL register CSOTn bit INTCSI0n signal Write 55H to SOTBnL register 55H (transmit data) ABH 56H ADH 5AH B5H 6AH D5H AAH AAH Remarks 1. Reg_R/W: Internal signal. This signal indicates that the SIRBn/SIRBnL register read or the SOTBn/SOTBnL register write was performed. 2. For the transmit/receive types, refer to 17.3 (2) register n (CSICn). 3. n = 0 to 2 Clocked serial interface clock selection User's Manual U16889EJ1V0UD 507 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) 17.4.3 Continuous transfer mode (1) Usage (receive-only: 8-bit data length) <1> Set the continuous transfer mode (CSIM0n.AUTOn bit = 1) and the receive-only mode (CSIM0n.TRMDn bit = 0). <2> Read the SIRBnL register (start transfer with dummy read). <3> When the transmission/reception completion interrupt request signal (INTCSI0n) has been generated, read the SIRBnL registerNote (reserve next transfer). <4> Repeat step <3> (N - 2) times. (N: Number of transfer data) Ignore the interrupt triggered by reception of the (N - 1)th data (at this time, the SIRBEnL register can be read). <5> Following generation of the last INTCSI0n signal, read the SIRBEnL register and the SIO0nL registerNote. Note When transferring N number of data, receive data is loaded by reading the SIRBnL register from the first data to the (N - 2)th data. The (N - 1)th data is loaded by reading the SIRBEnL register, and the Nth (last) data is loaded by reading the SIO0nL register (refer to Table 17-1 Use of Each Buffer Register). 508 User's Manual U16889EJ1V0UD CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) Figure 17-4. Continuous Transfer (Receive-Only) Timing Chart * Transmit/receive type 1, 8-bit data length SCK0n (I/O) SI0n (input) SIO0nL register SIRBnL register din-1 din-2 din-3 din-4 din-5 din-5 din-1 SIRBn (dummy) SIRBn (1) din-2 din-3 SIRBn (d2) din-4 SIRBn (d3) SIRBEn (d4) SIO0n (d5) Reg-RD CSOTn bit INTCSI0n signal SO0n (output) L rq_clr trans_rq <1> <2> <3> <4> Period during which next transfer can be reserved <3> <3> <5> Remarks 1. Reg_RD: Internal signal. This signal indicates that the SIRBnL register has been read. rq_clr: trans_rq: 2. n = 0 to 2 Internal signal. Transfer request clear signal. Internal signal. Transfer request signal. In the case of the continuous transfer mode, two transfer requests are set at the start of the first transfer. Following the INTCSI0n signal, transfer is continued if the SIRBnL register can be read within the next transfer reservation period. If the SIRBnL register cannot be read, transfer ends and the SIRBnL register does not receive the new value of the SIO0nL register. The last data can be obtained by reading the SIO0nL register following completion of the transfer. User's Manual U16889EJ1V0UD 509 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) (2) Usage (transmission/reception: 8-bit data length) <1> Set the continuous transfer mode (CSIM0n.AUTOn bit = 1) and the transmission/reception mode (CSIM0n.TRMDn bit = 1). <2> Write the first data to the SOTBFnL register. <3> Write the 2nd data to the SOTBnL register (start transfer). <4> When the transmission/reception completion interrupt request signal (INTCSI0n) has been generated, write the next data to the SOTBnL register (reserve next transfer). Read the SIRBnL register to load the receive data. <5> Repeat step <4> as long as data to be sent remains. <6> When the INTCSI0n signal is generated, read the SIRBnL register to load the (N - 1)th receive data (N: Number of transfer data). <7> Following the last INTCSI0n signal, read the SIO0nL register to load the Nth (last) receive data. 510 User's Manual U16889EJ1V0UD CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) Figure 17-5. Continuous Transfer (Transmission/Reception) Timing Chart * Transmit/receive type 1, 8-bit data length SCK0n (I/O) SO0n (output) SI0n (input) SOTBFnL register SOTBnL register SIO0nL register SIRBnL register dout-1 dout-2 dout-3 dout-4 dout-5 din-5 din-1 SOTBn (d3) SIRBn (d1) din-2 din-3 SOTBn (d4) SIRBn (d2) din-4 SOTBn (d5) SIRBn (d3) SIRBn (d4) SIOn (d5) dout-1 din-1 dout-2 din-2 dout-3 din-3 dout-4 din-4 dout-5 din-5 SOTBFn (d1) Reg_WR SOTBn (d2) Reg_RD CSOTn bit INTCSI0n signal rq_clr trans_rq <1> <2> <3> <4> <5> <4> <6> Period during which next transfer can be reserved <5> <4> <5> <7> <8> Remarks 1. Reg_WR: Internal signal. This signal indicates that the SOTBnL register has been written. Reg_RD: Internal signal. This signal indicates that the SIRBnL register has been read. rq_clr: trans_rq: 2. n = 0 to 2 Internal signal. Transfer request clear signal. Internal signal. Transfer request signal. In the case of the continuous transfer mode, two transfer requests are set at the start of the first transfer. Following the INTCSI0n signal, transfer is continued if the SOTBnL register can be written within the next transfer reservation period. If the SOTBnL register cannot be written, transfer ends and the SIRBnL register does not receive the new value of the SIO0nL register. The last receive data can be obtained by reading the SIO0nL register following completion of the transfer. User's Manual U16889EJ1V0UD 511 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) (3) Next transfer reservation period In the continuous transfer mode, the next transfer must be prepared with the period shown in Figure 17-6. Figure 17-6. Timing Chart of Next Transfer Reservation Period (1/2) (a) When data length: 8 bits, transmit/receive type 1 SCK0n (I/O) INTCSI0n signal Reservation period: 7 SCK0n cycles (b) When data length: 16 bits, transmit/receive type 1 SCK0n (I/O) INTCSI0n signal Reservation period: 15 SCK0n cycles Remark n = 0 to 2 512 User's Manual U16889EJ1V0UD CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) Figure 17-6. Timing Chart of Next Transfer Reservation Period (2/2) (c) When data length: 8 bits, transmit/receive type 2 SCK0n (I/O) INTCSI0n signal Reservation period: 6.5 SCK0n cycles (d) When data length: 16 bits, transmit/receive type 2 SCK0n (I/O) INTCSI0n signal Reservation period: 14.5 SCK0n cycles Remark n = 0 to 2 User's Manual U16889EJ1V0UD 513 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) (4) Cautions To continue continuous transfers, it is necessary to either read the SIRBn register or write to the SOTBn register during the transfer reservation period. If access is performed to the SIRBn register or the SOTBn register when the transfer reservation period is over, the following occurs. (i) In case of conflict between transfer request clear and register access Since transfer request clear has higher priority, the next transfer request is ignored. Therefore, transfer is interrupted, and normal data transfer cannot be performed. Figure 17-7. Transfer Request Clear and Register Access Conflict Transfer reservation period SCK0n (I/O) INTCSI0n signal rq_clr Reg_R/W Remarks 1. rq_clr: Internal signal. Transfer request clear signal. SOTBn/SOTBnL register write was performed. Reg_R/W: Internal signal. This signal indicates that the SIRBn/SIRBnL register read or the 2. n = 0 to 2 514 User's Manual U16889EJ1V0UD CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) (ii) In case of conflict between transmission/reception completion interrupt request signal (INTCSI0n) generation and register access Since continuous transfer has stopped once, executed as a new continuous transfer. In the slave mode, a bit phase error transfer error results (refer to Figure 17-8). In the transmission/reception mode, the value of the SOTBFn register is retransmitted, and illegal data is sent. Figure 17-8. Interrupt Request and Register Access Conflict Transfer reservation period SCK0n (I/O) INTCSI0n signal 0 1 2 3 4 rq_clr Reg_R/W Remarks 1. rq_clr: Internal signal. Transfer request clear signal. Reg_R/W: Internal signal. This signal indicates that the SIRBn/SIRBnL register read or the SOTBn/SOTBnL register write was performed. 2. n = 0 to 2 User's Manual U16889EJ1V0UD 515 CHAPTER 17 CLOCKED SERIAL INTERFACE 0 (CSI0) 17.5 Output Pins The following describes the output pins. For the setting of each pin, refer to Table 4-19 Settings When Port Pins Are Used for Alternate Functions. (1) SCK0n pin When the CSI0n operation is disabled (CSIM0n.CSI0En bit = 0), the SCK0n pin output status is as follows. Table 17-2. SCK0n Pin Output Status CKPn 0 1 CKS0n2 Don't care 1 Other than above CKS0n1 Don't care 1 CKS0n0 Don't care 1 SCK0n Pin Output Fixed to high level High impedance Fixed to low level Remark (2) SO0n pin n = 0 to 2 When the CSI0n operation is disabled (CSI0En bit = 0), the SO0n pin output status is as follows. Table 17-3. SO0n Pin Output Status TRMDn 0 1 DAPn Don't care 0 1 AUTOn Don't care Don't care 0 CCLn Don't care Don't care 0 DIRn Don't care Don't care 0 1 1 0 1 1 0 0 1 1 0 1 SO0n Pin Output Fixed to low level SO latch value (low level) SOTBn7 bit value SOTBn0 bit value SOTBn15 bit value SOTBn0 bit value SOTBFn7 bit value SOTBFn0 bit value SOTBFn15 bit value SOTBFn0 bit value Remark n = 0 to 2 516 User's Manual U16889EJ1V0UD CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION In the V850ES/KJ1, two channels of clocked serial interface A (CSIA) with automatic transmit/receive function are provided. 18.1 Functions CSIAn has the following two modes. * 3-wire serial I/O mode * 3-wire serial I/O mode with automatic transmit/receive function (1) 3-wire serial I/O mode This mode is used to transfer 8-bit data using three lines: a serial clock pin (SCKAn) and two serial data pins (SIAn and SOAn). In addition, whether 8-bit data is transferred MSB or LSB first can be specified, so this interface can be connected to any device. (2) 3-wire serial I/O mode with automatic transmit/receive function This mode is used to transfer 8-bit data using three lines: a serial clock pin (SCKAn) and two serial data pins (SIAn and SOAn). In addition, whether 8-bit data is transferred MSB or LSB first can be specified, so this interface can be connected to any device. Data can be transferred to/from a display driver etc. without using software since a 32-byte buffer RAM is incorporated for automatic transfer. * Maximum transfer speed: 2 MHz (in master mode) * Master mode/slave mode selectable * Transfer data length: 8 bits * MSB/LSB-first selectable for transfer data * Automatic transmit/receive function: Number of transfer bytes can be specified between 1 and 32 Transfer interval can be specified (0 to 63 clocks) Single transfer/repeat transfer selectable * On-chip dedicated baud rate generator (6/8/16/32 divisions) * 3-wire SOAn: SIAn: Serial data output Serial data input SCKAn: Serial clock I/O * Transmission/reception completion interrupt request signal: INTCSIAn * Internal 32-byte buffer RAM (used in 3-wire serial I/O mode with automatic transmit/receive function) Remark n = 0, 1 User's Manual U16889EJ1V0UD 517 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION 18.2 Configuration CSIAn consists of the following hardware. Table 18-1. Configuration of CSIAn Item Register Configuration Serial I/O shift register An (SIOAn) Automatic data transfer address count register n (ADTCn) CSIAn buffer RAM (CSIAnBm, CSIAnBmL, CSIAnBmH) (m = 0 to F) Control registers Serial operation mode specification register n (CSIMAn) Serial status register n (CSISn) Serial trigger register n (CSITn) Divisor selection register n (BRGCAn) Automatic data transfer address point specification register n (ADTPn) Automatic data transfer interval specification register n (ADTIn) Remark For the alternate-function pin settings, refer to Table 4-19 Settings When Port Pins Are Used for Alternate Functions. 518 User's Manual U16889EJ1V0UD Figure 18-1. Block Diagram of CSIAn CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION Buffer RAM Automatic data transfer address point specification register n (ADTPn) Automatic data transfer address count register n (ADTCn) Internal bus DIRAn ATMn SIAn User's Manual U16889EJ1V0UD Serial I/O shift register An (SIOAn) Divisor selection register n (BRGCAn) Serial trigger register n (CSITn) ATSTPn ATSTAn Serial status register n (CSISn) CKSAn1 CKSAn0 TSFn RXEAn SOAn TXEAn 2 2 Serial clock counter Serial transfer controller SCKAn Interrupt generator INTCSIAn Selector fXX/6 to fXX/256 Selector fXX Automatic data transfer interval specification register n (ADTIn) 6-bit counter MASTERn 519 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (1) Serial I/O shift register An (SIOAn) This is an 8-bit register used to store transmit/receive data in 1-byte transfer mode (CSIMAn.ATEn bit = 0). Writing transmit data to the SIOAn register starts the transfer. In addition, after a transfer completion interrupt request signal (INTCSIAn) is generated (CSISn.TSFn bit = 0), data can be received by reading data from the SIOAn register. This register can be read or written in 8-bit units. However, writing to the SIOAn register is prohibited when the CSISn.TSFn bit = 1. After reset, this register is cleared to 00H. Cautions 1. A transfer operation is started by writing to SIOAn register. Consequently, when transmission is disabled (CSIMAn.TXEAn bit = 0), write dummy data to the SIOAn register to start the transfer operation, and then perform a receive operation. 2. Do not write data to the SIOAn register while the automatic transmit/receive function is operating. After reset: 00H 7 SIOAn (n = 0, 1) SIOAn7 R/W 6 SIOAn6 Address: SIOA0 FFFFFD46H, SIOA1 FFFFFD56H 5 SIOAn5 4 SIOAn4 3 SIOAn3 2 SIOAn2 1 SIOAn1 0 SIOAn0 (2) Automatic data transfer address count register n (ADTCn) This is a register used to indicate buffer RAM addresses during automatic transfer. When automatic transfer is stopped, the data position when transfer stopped can be ascertained by reading ADTCn register value. This register is read-only in 8-bit units. However, reading from the ADTCn register is prohibited when the CSISn.TSFn bit = 1. After reset, this register is cleared to 00H. After reset: 00H 7 ADTCn (n = 0, 1) R 6 Address: ADTC0 FFFFFD47H, ADTC1 FFFFD57H 5 4 3 2 1 0 ADTCn7 ADTCn6 ADTCn5 ADTCn4 ADTCn3 ADTCn2 ADTCn1 ADTCn0 18.3 Registers Serial interface CSIAn is controlled by the following six registers. * Serial operation mode specification register n (CSIMAn) * Serial status register n (CSISn) * Serial trigger register n (CSITn) * Divisor selection register n (BRGCAn) * Automatic data transfer address point specification register n (ADTPn) * Automatic data transfer interval specification register n (ADTIn) 520 User's Manual U16889EJ1V0UD CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (1) Serial operation mode specification register n (CSIMAn) This is an 8-bit register used to control the serial transfer operation. This register can be read or written in 8-bit or 1-bit units. After reset, this register is cleared to 00H. After reset: 00H <7> CSIMAn (n = 0, 1) CSIAEn 0 1 CSIAEn R/W 6 ATEn Address: CSIMA0 FFFFFD40H, CSIMA1 FFFFD50H 5 ATMn 4 MASTERn <3> TXEAn <2> RXEAn <1> DIRAn 0 0 CSIAn operation enable/disable control Disable CSIAn operation (SOAn: Low level, SCKAn: High level) Enable CSIAn operation * When the CSIAEn bit is cleared to 0, the CSIAn unit is resetNote asynchronously. * When the CSIAEn bit = 0, the CSIAn unit is reset, so to operate CSIAn, first set the CSIAEn bit to 1. * If the CSIAEn bit is cleared from 1 to 0, all the registers in the CSIAn unit are initialized. Before the CSIAEn bit is set to 1 again, first re-set the registers of the CSIAn unit. * If the CSIAEn bit is cleared from 1 to 0, the buffer RAM value is not held. Also, when the CSIAEn bit = 0, the buffer RAM cannot be accessed. ATEn 0 1 ATMn 0 1 Automatic transfer operation enable/disable control 1-byte transfer mode Automatic transfer mode Specification of automatic transfer mode Single transfer mode (stops at address specified with ADTPn register) Repeat transfer mode (Following transfer completion, the ADTCn register is cleared to 00H and transmission starts again.) Specification of CSIAn master/slave mode Slave mode (synchronized with SCKAn input clock) Master mode (synchronized with internal clock) Transmission enable/disable control Disable transmission (SOAn: Low level) Enable transmission Reception enable/disable control Disable reception Enable reception Specification of transfer data direction MSB first LSB first MASTERn 0 1 TXEAn 0 1 RXEAn 0 1 DIRAn 0 1 Note The ADTCn, CSITn, and SIOAn registers and the CSIS.TSFn bit are reset. User's Manual U16889EJ1V0UD 521 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (2) Serial status register n (CSISn) This is an 8-bit register used to select the serial clock and to indicate the transfer status of CSIAn. This register can be read or written in 8-bit or 1-bit units. After reset, this register is cleared to 00H. However, rewriting the CSISn register is prohibited when the TSFn bit is 1. After reset: 00H 7 CSISn (n = 0, 1) R/W 6 Address: CSIS0 FFFFFD41H, CSIS1 FFFFD51H 5 0 4 0 3 0 2 0 1 0 0 TSFn CKSAn1 CKSAn0 CKSAn1 CKSAn0 Serial clock (fSCKA) selectionNote 20 MHz 16 MHz 10 MHz 100 ns 200 ns 400 ns 800 ns 0 0 1 1 0 1 0 1 fXX fXX/2 fXX/4 fXX/8 Setting prohibited Setting prohibited 100 ns 200 ns 400 ns 125 ns 250 ns 500 ns Rewriting CSISn is prohibited when the CSIMAn.CSIAEn bit is 1. TSFn 0 Transfer status CSIAEn bit = 0 At reset input At completion of specified transfer When transfer has been suspended by setting the CSITn.ATSTPn bit to 1 From transfer start to completion of specified transfer 1 Note Set fSCKA so as to satisfy the following conditions. * REGC = VDD = 4.0 to 5.5 V: fSCKA 12 MHz * REGC = Capacity, VDD = 4.0 to 5.5 V: fSCKA 6 MHz * REGC = VDD = 2.7 to 4.0 V: fSCKA 6 MHz Cautions 1. The TSFn bit is read-only. 2. When the TSFn bit = 1, rewriting the CSIMAn, CSISn, BRGCAn, ADTPn, ADTIn, and SIOAn registers is prohibited. However, the transfer buffer RAM can be rewritten. 3. Be sure to clear bits 1 to 5 to 0. 522 User's Manual U16889EJ1V0UD CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (3) Serial trigger register n (CSITn) The CSITn register between the buffer RAM and shift register is an 8-bit register used to control execution/stop of automatic data transfer. This register can be read or written in 8-bit or 1-bit units. However, manipulate only when the CSIMAn.ATEn bit is 1 (manipulation prohibited when ATEn bit = 0). After reset, this register is cleared to 00H. After reset: 00H 7 CSITn (n = 0, 1) ATSTPn 0 1 0 R/W 6 0 Address: CSIT0 FFFFFD42H, CSIT1 FFFFD52H 5 0 4 0 3 0 2 0 <1> ATSTPn <0> ATSTAn Automatic data transfer suspension - Stop automatic data transfer Even when the ATSTPn bit is set to 1, transfer does not stop until 1 byte has been transferred. 1 is held until immediately before the transmission/reception completion interrupt request signal (INTCSIAn) is generated, and ATSTPn is automatically cleared to 0 after that. After automatic transfer has been suspended, the data address at the point of suspension is stored in the ADTCn register. A function to resume automatic data transfer is not provided, so if transfer has been interrupted by setting the ATSTPn bit to 1, set each register again, and set the ATSTAn bit to 1 to start automatic data transfer. ATSTAn 0 1 Automatic data transfer start - Start automatic data transfer Even when the ATSTAn bit is set to 1, automatic data transfer does not start until 1 byte has been transferred. 1 is held until immediately before the INTCSIAn signal is generated, and ATSTAn is automatically cleared to 0 after that. User's Manual U16889EJ1V0UD 523 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (4) Divisor selection register n (BRGCAn) This is an 8-bit register used to control the serial transfer speed (divisor of CSIA clock). This register can be read or written in 8-bit units. However, when the CSISn.TSFn bit is 1, rewriting the BRGCAn register is prohibited. After reset, this register is set to 03H. After reset: 03H 7 BRGCAn (n = 0, 1) 0 R/W 6 0 Address: BRGCA0 FFFFFD43H, BRGCA1 FFFFD53H 5 0 4 0 3 0 2 0 1 0 BRGCn1 BRGCn0 BRGCn1 BRGCn0 0 0 1 1 0 1 0 1 Selection of CSIAn serial clock (fSCKA division ratio) 6 (fSCKA/6) 8 (fSCKA/8) 16 (fSCKA/16) 32 (fSCKA/32) (5) Automatic data transfer address point specification register n (ADTPn) This is an 8-bit register used to specify the buffer RAM address that ends transfer during automatic data transfer (CSIMAn.ATEn bit = 1). This register can be read or written in 8-bit units. However, when the CSISn.TSFn bit is 1, rewriting the ADTPn register is prohibited. After reset, this register is cleared to 00H. In the V850ES/KJ1, 00H to 1FH can be specified because 32 bytes of buffer RAM are incorporated. Example When the ADTP0 register is set to 07H 8 bytes of FFFFFE00H to FFFFFE07H are transferred. In repeat transfer mode (CSIMAn.ATMn bit = 1), transfer is performed repeatedly up to the address value specified by ADTPn. Example When the ADTP0 register is set to 07H (repeat transfer mode) Transfer is repeated as FFFFFE00H to FFFFFE07H, ... . After reset: 00H 7 ADTPn (n = 0, 1) 0 R/W 6 0 Address: ADTP0 FFFFFD44H, ADTP1 FFFFD54H 5 0 4 ADTPn4 3 2 1 ADTPn1 0 ADTPn0 ADTPn3 ADTPn2 Caution Be sure to clear bits 5 to 7 to 0. 524 User's Manual U16889EJ1V0UD CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION The relationship between buffer RAM address values and the ADTPn register setting values is shown below. Table 18-2. Relationship Between Buffer RAM Address Values and ADTP0 Register Setting Values Buffer RAM Address Value FFFFFE00H FFFFFE01H FFFFFE02H FFFFFE03H FFFFFE04H FFFFFE05H FFFFFE06H FFFFFE07H FFFFFE08H FFFFFE09H FFFFFE0AH FFFFFE0BH FFFFFE0CH FFFFFE0DH FFFFFE0EH FFFFFE0FH ADTP0 Register Setting Value 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH Buffer RAM Address Value FFFFFE10H FFFFFE11H FFFFFE12H FFFFFE13H FFFFFE14H FFFFFE15H FFFFFE16H FFFFFE17H FFFFFE18H FFFFFE19H FFFFFE1AH FFFFFE1BH FFFFFE1CH FFFFFE1DH FFFFFE1EH FFFFFE1FH ADTP0 Register Setting Value 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Table 18-3. Relationship Between Buffer RAM Address Values and ADTP1 Register Setting Values Buffer RAM Address Value FFFFFE20H FFFFFE21H FFFFFE22H FFFFFE23H FFFFFE24H FFFFFE25H FFFFFE26H FFFFFE27H FFFFFE28H FFFFFE29H FFFFFE2AH FFFFFE2BH FFFFFE2CH FFFFFE2DH FFFFFE2EH FFFFFE2FH ADTP1 Register Setting Value 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH Buffer RAM Address Value FFFFFE30H FFFFFE31H FFFFFE32H FFFFFE33H FFFFFE34H FFFFFE35H FFFFFE36H FFFFFE37H FFFFFE38H FFFFFE39H FFFFFE3AH FFFFFE3BH FFFFFE3CH FFFFFE3DH FFFFFE3EH FFFFFE3FH ADTP1 Register Setting Value 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH User's Manual U16889EJ1V0UD 525 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (6) Automatic data transfer interval specification register n (ADTIn) This is an 8-bit register used to specify the interval period between 1-byte transfers during automatic data transfer (CSIMAn.ATEn bit = 1). Set this register when in master mode (CSIMAn.MASTERn bit = 1) (setting is unnecessary in slave mode). Setting in 1-byte transfer mode (ATEn bit = 0) is also valid. When the interval time specified by the ADTIn register after the end of 1-byte transfer has elapsed, a transmission/reception completion interrupt request signal (INTCSIAn) is output. The number of clocks for the interval can be set to between 0 and 63 clocks. This register can be read or written in 8-bit units. However, when the CSISn.TSFn bit is 1, rewriting the ADTIn register is prohibited. After reset, this register is cleared to 00H. After reset: 00H 7 ADTIn (n = 0, 1) 0 R/W 6 0 Address: ADTI0 FFFFFD45H, ADTI1 FFFFD55H 5 ADTIn5 4 ADTIn4 3 ADTIn3 2 ADTIn2 1 ADTIn1 0 ADTIn0 The specified interval time is the transfer clock (specified by the BRGCAn register) multiplied by an integer value. Example When ADTIn register = 03H SCKAn Interval time of 3 clocks (7) CSIAn buffer RAM (CSIAnBm) This area holds transmit/receive data (up to 32 bytes) in automatic transfer mode in 1-byte units. This register can be read or written in 16-bit units. However, when the higher 8 bits and the lower 8 bits of the CSIAnBm register are used as the CSIAnBmH register and CSIAnBmL register, respectively, these registers can be read or written in 8-bit units. After automatic transfer is started, only data equal to one byte more than the number of bytes stored in the ADTPn register is transmitted/received in sequence from the CSIAmB0L register. Cautions 1. To read the value of the CSIAnBm register after data is written to the register, wait for the duration of more than six clocks of fSCKA (serial clock set by the CSISn.CKSAn1 and CSISn.CKSAn0 bits) or until data is written to the buffer RAM at another address. 2. When the main clock stops and the CPU operates on the subclock, do not access the CSIAnBm register. For details, refer to 3.4.8 (2). Remark n = 0, 1 m = 0 to F 526 User's Manual U16889EJ1V0UD CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION Table 18-4. CSIA0 Buffer RAM Address FFFFFE00H FFFFFE00H FFFFFE01H FFFFFE02H FFFFFE02H FFFFFE03H FFFFFE04H FFFFFE04H FFFFFE05H FFFFFE06H FFFFFE06H FFFFFE07H FFFFFE08H FFFFFE08H FFFFFE09H FFFFFE0AH FFFFFE0AH FFFFFE0BH FFFFFE0CH FFFFFE0CH FFFFFE0DH FFFFFE0EH FFFFFE0EH FFFFFE0FH FFFFFE10H FFFFFE10H FFFFFE11H FFFFFE12H FFFFFE12H FFFFFE13H FFFFFE14H FFFFFE14H FFFFFE15H FFFFFE16H FFFFFE16H FFFFFE17H FFFFFE18H FFFFFE18H FFFFFE19H FFFFFE1AH FFFFFE1AH FFFFFE1BH FFFFFE1CH FFFFFE1CH FFFFFE1DH FFFFFE1EH FFFFFE1EH FFFFFE1FH Symbol CSIA0B0 CSIA0B0L CSIA0B0H CSIA0B1 CSIA0B1L CSIA0B1H CSIA0B2 CSIA0B2L CSIA0B2H CSIA0B3 CSIA0B3L CSIA0B3H CSIA0B4 CSIA0B4L CSIA0B4H CSIA0B5 CSIA0B5L CSIA0B5H CSIA0B6 CSIA0B6L CSIA0B6H CSIA0B7 CSIA0B7L CSIA0B7H CSIA0B8 CSIA0B8L CSIA0B8H CSIA0B9 CSIA0B9L CSIA0B9H CSIA0BA CSIA0BAL CSIA0BAH CSIA0BB CSIA0BBL CSIA0BBH CSIA0BC CSIA0BCL CSIA0BCH CSIA0BD CSIA0BDL CSIA0BDH CSIA0BE CSIA0BEL CSIA0BEH CSIA0BF CSIA0BFL CSIA0BFH R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W User's Manual U16889EJ1V0UD R/W Manipulatable Bits 8 16 After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 527 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION Table 18-5. CSIA1 Buffer RAM Address FFFFFE20H FFFFFE20H FFFFFE21H FFFFFE22H FFFFFE22H FFFFFE23H FFFFFE24H FFFFFE24H FFFFFE25H FFFFFE26H FFFFFE26H FFFFFE27H FFFFFE28H FFFFFE28H FFFFFE29H FFFFFE2AH FFFFFE2AH FFFFFE2BH FFFFFE2CH FFFFFE2CH FFFFFE2DH FFFFFE2EH FFFFFE2EH FFFFFE2FH FFFFFE30H FFFFFE30H FFFFFE31H FFFFFE32H FFFFFE32H FFFFFE33H FFFFFE34H FFFFFE34H FFFFFE35H FFFFFE36H FFFFFE36H FFFFFE37H FFFFFE38H FFFFFE38H FFFFFE39H FFFFFE3AH FFFFFE3AH FFFFFE3BH FFFFFE3CH FFFFFE3CH FFFFFE3DH FFFFFE3EH FFFFFE3EH FFFFFE3FH Symbol CSIA1B0 CSIA1B0L CSIA1B0H CSIA1B1 CSIA1B1L CSIA1B1H CSIA1B2 CSIA1B2L CSIA1B2H CSIA1B3 CSIA1B3L CSIA1B3H CSIA1B4 CSIA1B4L CSIA1B4H CSIA1B5 CSIA1B5L CSIA1B5H CSIA1B6 CSIA1B6L CSIA1B6H CSIA1B7 CSIA1B7L CSIA1B7H CSIA1B8 CSIA1B8L CSIA1B8H CSIA1B9 CSIA1B9L CSIA1B9H CSIA1BA CSIA1BAL CSIA1BAH CSIA1BB CSIA1BBL CSIA1BBH CSIA1BC CSIA1BCL CSIA1BCH CSIA1BD CSIA1BDL CSIA1BDH CSIA1BE CSIA1BEL CSIA1BEH CSIA1BF CSIA1BFL CSIA1BFH R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Manipulatable Bits 8 16 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined After Reset 528 User's Manual U16889EJ1V0UD CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION 18.4 Operation CSIAn can be used in the following two modes. * 3-wire serial I/O mode * 3-wire serial I/O mode with automatic transmit/receive function 18.4.1 3-wire serial I/O mode The one-byte data transmission/reception is executed in the mode in which the CSIMAn.ATEn bit is cleared to 0. In this mode, communication is executed by using three lines: serial clock (SCKAn), serial data output (SOAn), and serial data input (SIAn) pins. The 3-wire serial I/O mode is controlled by the following three registers. * Serial operation mode specification register n (CSIMAn) * Serial status register n (CSISn) * Divisor selection register n (BRGCAn) Remarks 1. For the alternate-function pin settings, refer to Table 4-19 Settings When Port Pins Are Used for Alternate Functions. 2. n = 0, 1 User's Manual U16889EJ1V0UD 529 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (1) 1-byte transmission/reception communication operation (a) 1-byte transmission/reception When the CSIMAn.CSIAEn bit and the CSIMAn.ATEn bit = 1, 0, respectively, if transfer data is written to the SIOAn register, the data is output via the SOA0 pin in synchronization with the SCKAn pin falling edge, and then input via the SIAn pin in synchronization with the falling edge of the SCKAn pin, and stored in the SIOAn register in synchronization with the rising edge 1 clock later. Data transmission and data reception can be performed simultaneously. If only reception is to be performed, transfer can only be started by writing a dummy value to the SIOAn register. When transfer of 1 byte is complete, a transmission/reception completion interrupt request signal (INTCSIAn) is generated. In 1-byte transmission/reception, the setting of the CSIMAn.ATMn bit is invalid. Be sure to read data after confirming that the CSISn.TSFn bit = 0. Caution Determine the setting procedure of alternate-function pins considering the relationship with the communication partner. Figure 18-2. 3-Wire Serial I/O Mode Timing SCKAn 1 2 3 4 5 6 7 8 SIAn DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SOAn DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 INTCSIAn Transfer starts at falling edge of SCKAn pin TSFn End of transfer SIOAn write Caution Remark The SOAn pin becomes low level by the SIOAn register write. n = 0, 1 530 User's Manual U16889EJ1V0UD CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (b) Data format In the data format, data is changed in synchronization with the SCKAn pin falling edge as shown in Figure 18-3. The data length is fixed to 8 bits and the data transfer direction can be switched by the specification of the CSIMAn.DIRAn bit. Figure 18-3. Format of Transmit/Receive Data (a) MSB-first (DIRAn bit = 0) SCKAn SIAn SOAn DO7 DI7 DO6 DI6 DO5 DI5 DO4 DI4 DO3 DI3 DO2 DI2 DO1 DI1 DO0 DI0 (b) LSB-first (DIRAn bit = 1) SCKAn SIAn SOAn DO0 DI0 DO1 DI1 DO2 DI2 DO3 DI3 DO4 DI4 DO5 DI5 DO6 DI6 DO7 DI7 Remark n = 0, 1 User's Manual U16889EJ1V0UD 531 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (c) Switching MSB/LSB as start bit Figure 18-4 shows the configuration of the SIOAn register and the internal bus. As shown in the figure, MSB/LSB can be read or written in reverse form. Switching MSB/LSB as the start bit can be specified using the CSIMAn.DIRAn bit. Start bit switching is realized by switching the bit order for data written to the SIOAn register. The SIOAn register shift order remains unchanged. Thus, switching between MSB-first and LSB-first must be performed before writing data to the SIOAn register. Figure 18-4. Transfer Bit Order Switching Circuit 7 6 Internal bus 1 0 LSB-first MSB-first Read/write gate Read/write gate SOAn latch SIAn Shift register n (SIOAn) D Q SOAn SCKAn Remark n = 0, 1 (d) Transfer start Serial transfer is started by setting transfer data to the SIOAn register when the following two conditions are satisfied. * CSIAn operation control bit (CSIMAn.CSIAEn) = 1 * Other than during serial communication Caution If the CSIAEn bit is set to 1 after data is written to the SIOAn register, communication does not start. Upon termination of 8-bit communication, serial communication automatically stops and the transmission/reception completion interrupt request signal (INTCSIAn) is generated. Remark n = 0, 1 532 User's Manual U16889EJ1V0UD CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION 18.4.2 3-wire serial I/O mode with automatic transmit/receive function Up to 32 bytes of data can be transmitted/received without using software in the mode in which the CSIMAn.ATEn bit is set to 1. After communication is started, only data of the set number of bytes stored in RAM in advance can be transmitted, and only data of the set number of bytes can be received and stored in RAM. The 3-wire serial I/O mode with automatic transmit/receive function is controlled by the following registers. * Serial operation mode specification register n (CSIMAn) * Serial status register n (CSISn) * Serial trigger register n (CSITn) * Divisor selection register n (BRGCAn) * Automatic data transfer address point specification register n (ADTPn) * Automatic data transfer interval specification register n (ADTIn) Remarks 1. 2. For the alternate-function pin settings, refer to Table 4-19 Settings When Port Pins Are Used for Alternate Functions. n = 0, 1 (1) Automatic transmit/receive data setting (a) Transmit data setting <1> Write transmit data from the least significant address FFFFFE00H/FFFFFE20H of buffer RAM (up to FFFFFE1FH/FFFFFE3FH at maximum). address to higher address. <2> Set the ADTPn register to the value obtained by subtracting 1 from the number of transmit data bytes. (b) Automatic transmission/reception mode setting <1> Set the CSIMAn.CSIAEn bit and the CSIMAn.ATEn bit to 11. <2> Set the CSIMAn.RXEAn bit and the CSIMAn.TXEAn bit to 11. <3> Set a data transfer interval in the ADTIn register. <4> Set the CSITn.ATSTAn bit to 1. The following operations are automatically carried out when (a) and (b) are carried out. * After the buffer RAM data indicated by the ADTCn register is transferred to the SIOAn register, transmission is carried out (start of automatic transmission/reception). * The received data is written to the buffer RAM address indicated by the ADTCn register. * ADTCn register is incremented and the next data transmission/reception is carried out. Data transmission/reception continues until the ADTCn register incremental output matches the set value of the ADTPn register (end of automatic transmission/reception). However, if the CSIMAn.ATMn bit is set to 1 (continuous transfer mode), the ADTCn register is cleared after a match between the ADTPn and ADTCn registers, and then repeated transmission/reception is started. * When automatic transmission/reception is terminated, the CSISn.TSFn bit is cleared to 0. Caution Determine the setting procedure of alternate-function pins considering the relationship with the communication partner. Remark n = 0, 1 User's Manual U16889EJ1V0UD The transmit data should be in the order from lower 533 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (2) Automatic transmission/reception communication operation (a) Automatic transmission/reception mode Automatic transmission/reception can be performed using buffer RAM. The data stored in the buffer RAM is output from the SOAn pin via the SIOAn register in synchronization with the SCKAn pin falling edge by performing (a) and (b) in (1) Automatic transmit/receive data setting. The data is then input from the SIAn pin via the SIOAn register in synchronization with the serial clock falling edge of the SCKAn pin and the receive data is stored in the buffer RAM in synchronization with the rising edge 1 clock later. Data transfer ends if the CSISn.TSFn bit is cleared to 0 when any of the following conditions is met. * Reset by clearing the CSIMAn.CSIAEn bit to 0 * Transfer of 1 byte is complete by setting the CSITn.ATSTPn bit to 1 * Transfer of the range specified by the ADTPn register is complete At this time, a transmission/reception completion interrupt request signal (INTCSIAn) is generated except when the CSIAEn bit = 0. If a transfer is terminated in the middle, transfer starting from the remaining data is not possible. Read the ADTCn register to confirm how much of the data has already been transferred, set the transfer data again, and perform (a) and (b) in (1) Automatic transmit/receive data setting. Figure 18-5 shows the operation timing in automatic transmission/reception mode and Figure 18-6 shows the operation flowchart. Figure 18-7 shows the operation of the buffer RAM when 6 bytes of data are transmitted/received. Remark n = 0, 1 534 User's Manual U16889EJ1V0UD CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION Figure 18-5. Automatic Transmission/Reception Mode Operation Timings Interval Interval SCKAn SOAn D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SIAn D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 INTCSIAn TSFn Cautions 1. Because, in the automatic transmission/reception mode, the automatic transmit/receive function reads/writes data from/to the buffer RAM after 1-byte transmission/reception, an interval is inserted until the next transmission/reception. As the buffer RAM read/write is performed at the same time as CPU processing, the interval is dependent upon the value of the ADTIn register. 2. When the TSFn bit is cleared, the SOAn pin becomes low level. 3. If CPU access to the buffer RAM conflicts with CSIAn read/write during the interval time, the interval time becomes longer. Remark n = 0, 1 User's Manual U16889EJ1V0UD 535 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION Figure 18-6. Automatic Transmission/Reception Mode Flowchart Start Write transmit data in buffer RAM Set ADTPn register to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Software execution Set automatic transmission/ reception mode Set CSITn.ATSTAn bit to 1 Write transmit data from buffer RAM to SIOAn register Transmission/reception operation Increment pointer value Hardware execution Write receive data from SIOAn register to buffer RAM ADTPn register = ADTCn register Yes No TSFn bit = 0 No Software execution Yes End Remark n = 0, 1 536 User's Manual U16889EJ1V0UD CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION In 6-byte transmission/reception (CSIMAn.ATMn bit = 0, CSIMAn.RXEAn bit = 1, CSIMAn.TXEAn bit = 1) in automatic transmission/reception mode, buffer RAM operates as follows. (i) When transmission/reception operation is started (refer to Figure 18-7 (a).) When the CSITn.ATSTAn bit is set to 1, transmit data 1 (T1) is transferred from the buffer RAM to the SIOAn register. When transmission of the first byte is completed, receive data 1 (R1) is transferred from the SIOAn register to the buffer RAM, and the ADTCn register is incremented. Then transmit data 2 (T2) is transferred from the buffer RAM to the SIOAn register. (ii) 4th byte transmission/reception point (refer to Figure 18-7 (b).) Transmission/reception of the third byte is completed, and transmit data 4 (T4) is transferred from the buffer RAM to the SIOAn register. When transmission of the fourth byte is completed, the receive data 4 (R4) is transferred from the SIOAn register to the buffer RAM, and the ADTCn register is incremented. (iii) Completion of transmission/reception (refer to Figure 18-7 (c).) When transmission of the sixth byte is completed, receive data 6 (R6) is transferred from SIOAn register to the buffer RAM, and the transmission/reception completion interrupt request signal (INTCSIAn) is generated. Figure 18-7. Buffer RAM Operation in 6-Byte Transmission/Reception (in Automatic Transmission/Reception Mode) (1/2) (a) When transmission/reception operation is started FFFFFE1FH FFFFFE05H Transmit data 6 (T6) Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) Transmit data 2 (T2) +1 Receive data 1 (R1) SIOAn register 5 ADTPn register 0 ADTCn register FFFFFE00H Transmit data 1 (T1) Not generated INTCSIAn signal Remarks 1. The above addresses are for CSIA0. For CSIA1, the addresses are FFFFFE20H to FFFFFE3FH. 2. n = 0, 1 User's Manual U16889EJ1V0UD 537 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION Figure 18-7. Buffer RAM Operation in 6-Byte Transmission/Reception (in Automatic Transmission/Reception Mode) (2/2) (b) 4th byte transmission/reception FFFFFE1FH FFFFFE05H Transmit data 6 (R6) Transmit data 5 (R5) Transmit data 4 (R4) Receive data 3 (T3) Receive data 2 (T2) +1 Receive data 4 (R4) SIOAn register 5 ADTPn register 3 ADTCn register FFFFFE00H Receive data 1 (T1) Not generated INTCSIAn signal (c) Completion of transmission/reception FFFFFE1FH FFFFFE05H Receive data 6 (R6) Receive data 5 (R5) Receive data 4 (R4) Receive data 3 (R3) Receive data 2 (R2) 5 SIOAn register ADTPn register 5 ADTCn register FFFFFE00H Receive data 1 (R1) Generated INTCSIAn signal Remarks 1. The above addresses are for CSIA0. For CSIA1, the addresses are FFFFFE20H to FFFFFE3FH. 2. n = 0, 1 538 User's Manual U16889EJ1V0UD CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (b) Automatic transmission mode In this mode, the specified number of 8-bit unit data are transmitted. Serial transfer is started when the CSITn.ATSTAn bit is set to 1 while the CSIMAn.CSIAEn, CSIMAn.ATEn, and CSIMAn.TXEAn bits are set to 1. When the final byte has been transmitted, an interrupt request signal (INTCSIAn) is generated. Figure 18-8 shows the automatic transmission mode operation timing, and Figure 18-9 shows the operation flowchart. Figure 18-10 shows the operation of the buffer RAM when 6 bytes of data are transmitted. Figure 18-8. Automatic Transmission Mode Operation Timing Interval Interval SCKAn SOAn D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 INTCSIAn TSFn Cautions 1. Because, in the automatic transmission mode, the automatic transmit/receive function reads data from the buffer RAM after 1-byte transmission, an interval is inserted until the next transmission. As the buffer RAM read is performed at the same time as CPU processing, the interval is dependent upon the value of the ADTIn register. 2. When the TSFn bit is cleared, the SOAn pin becomes low level. 3. If CPU access to the buffer RAM conflicts with CSIAn read/write during the interval time, the interval time becomes longer. Remark n = 0, 1 User's Manual U16889EJ1V0UD 539 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION Figure 18-9. Automatic Transmission Mode Flowchart Start Write transmit data in buffer RAM Set ADTPn register to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Software execution Set automatic transmission mode Set CSITn.ATSTAn bit to 1 Write transmit data from buffer RAM to SIOAn register Increment pointer value Transmission operation Hardware execution ADTPn register = ADTCn register Yes No TSFn bit = 0 No Software execution Yes End Remark n = 0, 1 540 User's Manual U16889EJ1V0UD CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION In 6-byte transmission (CSIMAn.ATMn bit = 0, CSIMAn.RXEAn bit = 0, CSIMAn.TXEAn bit = 1, CSIMAn.ATEn bit = 1) in automatic transmission mode, buffer RAM operates as follows. (i) When transmission is started (refer to Figure 18-10 (a).) When the CSITn.ATSTAn bit is set to 1, transmit data 1 (T1) is transferred from the buffer RAM to the SIOAn register. When transmission of the first byte is completed, the ADTCn register is incremented. Then transmit data 2 (T2) is transferred from the buffer RAM to the SIOAn register. (ii) 4th byte transmission point (refer to Figure 18-10 (b).) Transmission of the third byte is completed, and transmit data 4 (T4) is transferred from the buffer RAM to the SIOAn register. When transmission of the fourth byte is completed, the ADTCn register is incremented. (iii) Completion of transmission (refer to Figure 18-10 (c).) When transmission of the sixth byte is completed, the interrupt request signal (INTCSIAn) is generated, and the TFSn flag is cleared to 0. Figure 18-10. Buffer RAM Operation in 6-Byte Transmission (in Automatic Transmission Mode) (1/2) (a) When transmission is started FFFFFE1FH FFFFFE05H Transmit data 6 (T6) Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) Transmit data 2 (T2) +1 5 SIOAn register ADTPn register 0 ADTCn register FFFFFE00H Transmit data 1 (T1) Not generated INTCSIAn signal Remarks 1. The above addresses are for CSIA0. For CSIA1, the addresses are FFFFFE20H to FFFFFE3FH. 2. n = 0, 1 User's Manual U16889EJ1V0UD 541 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION Figure 18-10. Buffer RAM Operation in 6-Byte Transmission (in Automatic Transmission Mode) (2/2) (b) 4th byte transmission point FFFFFE1FH FFFFFE05H Transmit data 6 (T6) Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) Transmit data 2 (T2) +1 5 SIOAn register ADTPn register 3 ADTCn register FFFFFE00H Transmit data 1 (T1) Not generated INTCSIAn signal (c) Completion of transmission FFFFFE1FH FFFFFE05H Transmit data 6 (T6) Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) Transmit data 2 (T2) 5 SIOAn register ADTPn register 5 ADTCn register FFFFFE00H Transmit data 1 (T1) Generated INTCSIAn signal Remarks 1. The above addresses are for CSIA0. For CSIA1, the addresses are FFFFFE20H to FFFFFE3FH. 2. n = 0, 1 542 User's Manual U16889EJ1V0UD CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (c) Repeat transmission mode In this mode, data stored in the buffer RAM is transmitted repeatedly. Serial transfer is started when the CSITn.ATSTAn bit is set to 1 while the CSIMAn.CSIAEn, CSIMAn.ATEn, CSIMAn.ATMn, and CSIMAn.TXEAn bits are set to 1. Unlike the basic transmission mode, after the specified number of bytes has been transmitted, the transmission/reception completion interrupt request signal (INTCSIAn) is not generated, the ADTCn register is reset to 0, and the buffer RAM contents are transmitted again. The repeat transmission mode operation timing is shown in Figure 18-11, and the operation flowchart in Figure 18-12. Figure 18-13 shows the operation of the buffer RAM when 6 bytes of data are transmitted in the repeat transmission mode. Figure 18-11. Repeat Transmission Mode Operation Timing Interval SCKAn SOAn Interval D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 Cautions 1. Because, in the repeat transmission mode, a read is performed on the buffer RAM after the transmission of one byte, the interval is included in the period up to the next transmission. As the buffer RAM read is performed at the same time as CPU processing, the interval is dependent upon the ADTIn register. 2. If CPU access to the buffer RAM conflicts with CSIA read/write during the interval time, the interval time becomes longer. Remark n = 0, 1 User's Manual U16889EJ1V0UD 543 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION Figure 18-12. Repeat Transmission Mode Flowchart Start Write transmit data in buffer RAM Set ADTPn register to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes Software execution Set repeat transmission mode Set CSITn.ATSTAn bit to 1 Write transmit data from buffer RAM to SIOAn register Increment pointer value Transmission operation Hardware execution ADTPn register = ADTCn register Yes No Reset ADTCn register to 0 Remark n = 0, 1 544 User's Manual U16889EJ1V0UD CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION In 6-byte transmission (CSIMAn.ATMn bit = 1, CSIMAn.RXEAn bit = 0, CSIMAn.TXEAn bit = 1, CSIMAn.ATEn bit = 1) in repeat transmission mode, buffer RAM operates as follows. (i) When transmission is started (refer to Figure 18-13 (a).) When the CSITn.ATSTAn bit is set to 1, transmit data 1 (T1) is transferred from the buffer RAM to the SIOAn register. When transmission of the first byte is completed, the ADTCn register is incremented. Then transmit data 2 (T2) is transferred from the buffer RAM to the SIOAn register. (ii) Upon completion of transmission of 6 bytes (refer to Figure 18-13 (b).) When transmission of the sixth byte is completed, the interrupt request signal (INTCSIAn) is not generated. The ADTCn register is reset to 0. (iii) 7th byte transmission point (refer to Figure 18-13 (c).) Transmit data 1 (T1) is transferred from the buffer RAM to SIOAn register again. When transmission of the first byte is completed, the ADTCn register is incremented. Then transmit data 2 (T2) is transferred from the buffer RAM to the SIOAn register. Figure 18-13. Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmission Mode) (1/2) (a) When transmission is started FFFFFE1FH FFFFFE05H Transmit data 6 (T6) Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) Transmit data 2 (T2) +1 5 SIOAn register ADTPn register 0 ADTCn register FFFFFE00H Transmit data 1 (T1) Not generated INTCSIAn signal Remarks 1. The above addresses are for CSIA0. For CSIA1, the addresses are FFFFFE20H to FFFFFE3FH. 2. n = 0, 1 User's Manual U16889EJ1V0UD 545 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION Figure 18-13. Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmission Mode) (2/2) (b) Upon completion of transmission of 6 bytes FFFFFE1FH FFFFFE05H Transmit data 6 (T6) Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) Transmit data 2 (T2) 5 SIOAn register ADTPn register 5 ADTCn register FFFFFE00H Transmit data 1 (T1) Not generated INTCSIAn signal (c) 7th byte transmission point FFFFFE1FH FFFFFE05H Transmit data 6 (T6) Transmit data 5 (T5) Transmit data 4 (T4) Transmit data 3 (T3) Transmit data 2 (T2) +1 5 SIOAn register ADTPn register 0 ADTCn register FFFFFE00H Transmit data 1 (T1) Not generated INTCSIAn signal Remarks 1. The above addresses are for CSIA0. For CSIA1, the addresses are FFFFFE20H to FFFFFE3FH. 2. n = 0, 1 546 User's Manual U16889EJ1V0UD CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (d) Data format In the data format, data is changed in synchronization with the SCKAn pin falling edge as shown in Figure 18-14. The data length is fixed to 8 bits and the data transfer direction can be switched by the specification of the CSIMAn.DIRAn bit. Figure 18-14. Format of CSIAn Transmit/Receive Data (a) MSB-first (DIRAn bit = 0) SCKAn SIAn SOAn DO7 DI7 DO6 DI6 DO5 DI5 DO4 DI4 DO3 DI3 DO2 DI2 DO1 DI1 DO0 DI0 (b) LSB-first (DIRAn bit = 1) SCKAn SIAn SOAn DO0 DI0 DO1 DI1 DO2 DI2 DO3 DI3 DO4 DI4 DO5 DI5 DO6 DI6 DO7 DI7 Remark n = 0, 1 User's Manual U16889EJ1V0UD 547 CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION (e) Automatic transmission/reception suspension and restart Automatic transmission/reception can be temporarily suspended by setting the CSITn.ATSTPn bit to 1. During 8-bit data transfer, the transmission/reception is not suspended. It is suspended upon completion of 8-bit data transfer. When suspended, the CSISn.TSFn bit is cleared to 0 after transfer of the 8th bit. To restart automatic transmission/reception, set the CSITn.ATSTAn bit to 1. The remaining data can be transmitted in this way. Cautions 1. If the IDLE instruction is executed during automatic transmission/reception, transfer is suspended and the IDLE mode is set if during 8-bit data transfer. When the IDLE mode is cleared, automatic transmission/reception is restarted from the suspended point. 2. When suspending automatic transmission/reception, do not change the operating mode to 3-wire serial I/O mode while the TSFn bit = 1. Figure 18-15. Automatic Transmission/Reception Suspension and Restart ATSTPn bit = 1 (Suspend command) Suspend Restart command ATSTAn bit = 1 SCKAn SOAn SIAn D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Remark n = 0, 1 548 User's Manual U16889EJ1V0UD CHAPTER 19 I2C BUS To use the I2C bus function, set the P38/SDA0, P39/SCL0, P80/SDA1, and P81/SCL1 pins to N-ch open drain output as the alternate function. In the V850ES/KJ1, two channels of I2C bus are provided. The products with an on-chip I2C bus are shown below. PD703216Y, 703217Y, 70F3217Y, 70F3217HY, 70F3218HY 19.1 Selecting UART2 or I2C1 Mode UART2 and I2C1 of the V850ES/KJ1 share pins, and therefore these interfaces cannot be used at the same time. Select UART2 or I2C1 in advance by using the PMC8 and PFC8 registers (refer to 4.3.8 Port 8). Caution UART2 or I2C1 transmission/reception operations are not guaranteed if the mode is changed during transmission or reception. Be sure to disable the operation of the unit that is not used. Figure 19-1. Selecting Mode of UART2 or I2C1 After reset: 00H 7 PMC8 0 R/W 6 0 Address: FFFFF450H 5 0 4 0 3 0 2 0 1 PMC81 0 PMC80 After reset: 00H 7 PFC8 0 R/W 6 0 Address: FFFFF470H 5 0 4 0 3 0 2 0 1 PFC81 0 PFC80 PFC8n 0 0 1 1 PMC8n 0 1 0 1 Operation mode Port I/O mode UART2 mode Port I/O mode I C1 mode 2 Remark n = 0, 1 User's Manual U16889EJ1V0UD 549 CHAPTER 19 I C BUS 2 19.2 Features The I2C0 and I2C1 have the following two modes. * Operation stop mode * I2C (Inter IC) bus mode (multimaster supported) (1) Operation stop mode This mode is used when serial transfers are not performed. consumption. (2) I2C bus mode (multimaster supported) This mode is used for 8-bit data transfers with several devices via two lines: a serial clock (SCLn) line and a serial data bus (SDAn) line. This mode complies with the I2C bus format and the master device can output "start condition", "data", and "stop condition" data to the slave device, via the serial data bus. The slave device automatically detects these received data by hardware. This function can simplify the part of application program that controls the I2C bus. Since the SCLn and SDAn pins are used for N-ch open drain outputs, I2Cn requires pull-up resistors for the serial clock line and the serial data bus line. Remark n = 0, 1 It can therefore be used to reduce power 550 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 Figure 19-2. Block Diagram of I2Cn Internal bus IIC status register n (IICSn) MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn IIC control register n (IICCn) IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn SET SDAn Noise eliminator Slave address register n (SVAn) Match signal CLEAR Start condition generator IIC shift register n (IICn) DQ SO latch CLn1, CLn0 N-ch opendrain output Data hold time correction circuit ACK output circuit Wakeup controller ACK detector Start condition detector Stop condition detector SCLn Noise eliminator Serial clock counter Interrupt request signal generator INTIICn Serial clock controller N-ch opendrain output Serial clock wait controller Bus status detector fXX Prescaler CLDn DADn SMCn DFCn CLn1 CLn0 IIC clock selection register n (IICCLn) CLXn STCFn IICBSYn STCENn IICRSVn IIC flag register n (IICFn) IIC function expansion register n (IICXn) Internal bus Remark n = 0, 1 User's Manual U16889EJ1V0UD 551 CHAPTER 19 I C BUS 2 A serial bus configuration example is shown below. Figure 19-3. Serial Bus Configuration Example Using I2C Bus +VDD +VDD Master CPU1 Slave CPU1 Address 1 SDA SCL Serial data bus Serial clock SDA SCL Master CPU2 Slave CPU2 Address 2 SDA SCL Slave CPU3 Address 3 SDA SCL Slave IC Address 4 SDA SCL Slave IC Address N 552 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 19.3 Configuration I2Cn includes the following hardware. Table 19-1. Configuration of I2Cn Item Registers Configuration IIC shift registers 0 and 1 (IIC0, IIC1) Slave address registers 0 and 1 (SVA0, SVA1) Control registers IIC control registers 0 and 1 (IICC0, IICC1) IIC status registers 0 and 1 (IICS0, IICS1) IIC flag registers 0 and 1 (IICCF0, IICCF1) IIC clock selection registers 0 and 1 (IICCL0, IICCL1) IIC function expansion registers 0 and 1 (IICX0, IICX1) Remark n = 0, 1 (1) IIC shift registers 0 and 1 (IIC0, IIC1) The IICn register is used to convert 8-bit serial data to 8-bit parallel data and to convert 8-bit parallel data to 8bit serial data. The IICn register can be used for both transmission and reception. Write and read operations to the IICn register are used to control the actual transmit and receive operations. The IICn register can be read or written in 8-bit units. After reset, IIC0 and IIC1 are cleared to 00H. (2) Slave address registers 0 and 1 (SVA0, SVA1) The SVAn register sets local addresses when in slave mode. The SVAn register can be read or written in 8-bit units. After reset, SVA0 and SVA1 are cleared to 00H. (3) SO latch The SO latch is used to retain the SDAn pin's output level. (4) Wakeup controller This circuit generates an interrupt request signal (INTIICn) when the address received by this register matches the address value set to the SVAn register or when an extension code is received. (5) Prescaler This selects the sampling clock to be used. (6) Serial clock counter This counter counts the serial clocks that are output and the serial clocks that are input during transmit/receive operations and is used to verify that 8-bit data was sent or received. (7) Interrupt request signal generator This circuit controls the generation of interrupt request signals (INTIICn). An I2C interrupt is generated following either of two triggers. * Falling of the eighth or ninth clock of the serial clock (set by IICCn.WTIMn bit) * Interrupt request generated when a stop condition is detected (set by IICCn.SPIEn bit) User's Manual U16889EJ1V0UD 553 CHAPTER 19 I C BUS 2 (8) Serial clock controller In master mode, this circuit generates the clock output via the SCLn pin from a sampling clock. (9) Serial clock wait controller This circuit controls the wait timing. (10) ACK output circuit, stop condition detector, start condition detector, and ACK detector These circuits are used to output and detect various control signals. (11) Data hold time correction circuit This circuit generates the hold time for data corresponding to the falling edge of the serial clock. (12) Start condition generator This circuit generates a start condition when the IICCn.STTn bit is set. However, in the communication reservation disabled status (IICFn.IICRSVn bit = 1), when the bus is not released (IICFn.IICBSYn bit = 1), start condition requests are ignored and the IICFn.STCFn bit is set to 1. (13) Bus status detector This circuit detects whether or not the bus is released by detecting start conditions and stop conditions. However, as the bus status cannot be detected immediately following operation, the initial status is set by the IICFn.STCENn bit. 554 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 19.4 Registers I2C0 and I2C1 are controlled by the following registers. * IIC control registers 0, 1 (IICC0, IICC1) * IIC status registers 0, 1 (IICS0, IICS1) * IIC flag registers 0, 1 (IICF0, IICF1) * IIC clock selection registers 0, 1 (IICCL0, IICCL1) * IIC function expansion registers 0, 1 (IICX0, IICX1) The following registers are also used. * IIC shift registers 0, 1 (IIC0, IIC1) * Slave address registers 0, 1 (SVA0, SVA1) Remark For the alternate-function pin settings, refer to Table 4-19 Settings When Port Pins Are Used for Alternate Functions. (1) IIC control registers 0, 1 (IICC0, IICC1) The IICCn register is used to enable/stop I2Cn operations, set wait timing, and set other I2C operations. The IICCn register can be read or written in 8-bit or 1-bit units. After reset, IICCn is cleared to 00H. User's Manual U16889EJ1V0UD 555 CHAPTER 19 I C BUS 2 (1/4) After reset: 00H <7> IICCn (n = 0, 1) IICEn 0 1 I Cn operation enable/disable specification Stop operation. Reset the IICSn register Enable operation. Condition for setting (IICEn bit = 1) * Set by instruction Note 1 2 R/W <6> LRELn <5> WRELn Address: IICC0 FFFFFD82H, IICC1 FFFFFD92H <4> SPIEn <3> WTIMn <2> ACKEn <1> STTn <0> SPTn IICEn . Stop internal operation. Condition for clearing (IICEn bit = 0) * Cleared by instruction * Reset LRELn 0 1 Normal operation Exit from communications This exits from the current communications and sets standby mode. This setting is automatically cleared to 0 after being executed. Its uses include cases in which a locally irrelevant extension code has been received. The SCLn and SDAn lines are set to high impedance. The STTn, SPTn, IICSn.MSTSn, IICSn.EXCn, IICSn.COIn, IICSn.TRCn, IICSn.ACKDn, and IICSn.STDn bits are cleared to 0. The standby mode following exit from communications remains in effect until the following communications entry conditions are met. * After a stop condition is detected, restart is in master mode. * An address match or extension code reception occurs after the start condition. Condition for clearing (LRELn bit = 0) * Reset Note 2 Condition for setting (LRELn bit = 1) * Set by instruction * Automatically cleared after execution WRELn 0 1 Do not cancel wait Wait cancellation control Cancel wait. This setting is automatically cleared to 0 after wait is canceled. Note 2 Condition for clearing (WRELn bit = 0) * Reset Condition for setting (WRELn bit = 1) * Set by instruction * Automatically cleared after execution Notes 1. 2. The IICSn register, and the IICFn.STCFn, IICFn.IICBSYn, IICCLn.CLDn, and IICCLn.DADn bits are reset. This flag's signal is invalid when the IICEn bit = 0. 556 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 (2/4) SPIEn 0 1 Disable Enable Enable/disable generation of interrupt request when stop condition is detected Condition for clearing (SPIEn bit = 0) * Cleared by instruction * Reset Note Condition for setting (SPIEn bit = 1) * Set by instruction WTIMn 0 Control of wait and interrupt request generation Interrupt request is generated at the eighth clock's falling edge. Master mode: After output of eight clocks, clock output is set to low level and wait is set. Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master device. 1 Interrupt request is generated at the ninth clock's falling edge. Master mode: After output of nine clocks, clock output is set to low level and wait is set. Slave mode: After input of nine clocks, the clock is set to low level and wait is set for master device. An interrupt is generated at the falling of the 9th clock during address transfer independently of the setting of this bit. The setting of this bit is valid when the address transfer is completed. When in master mode, a wait is inserted at the falling edge of the ninth clock during address transfers. For a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after an acknowledge signal (ACK) is issued. However, when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. Condition for clearing (WTIMn bit = 0) * Cleared by instruction * Reset Note Condition for setting (WTIMn bit = 1) * Set by instruction ACKEn 0 1 Disable acknowledgment. Acknowledgment control Enable acknowledgment. During the ninth clock period, the SDAn line is set to low level. However, ACK is invalid during address transfers and other than in expansion mode. Condition for clearing (ACKEn bit = 0) * Cleared by instruction * Reset Note Condition for setting (ACKEn bit = 1) * Set by instruction Note This flag's signal is invalid when the IICEn bit = 0. User's Manual U16889EJ1V0UD 557 CHAPTER 19 I C BUS 2 (3/4) STTn 0 1 Do not generate a start condition. When bus is released (in STOP mode): Generate a start condition (for starting as master). The SDAn line is changed from high level to low level and then the start condition is generated. Next, after the rated amount of time has elapsed, the SCLn line is changed to low level. When a third party is communicating * When communication reservation function is enabled (IICFn.IICRSVn bit = 0) Functions as the start condition reservation flag. When set to 1, automatically generates a start condition after the bus is released. * When communication reservation function is disabled (IICRSVn bit = 1) The IICFn.STCFn bit is set to 1. No start condition is generated. In the wait state (when master device): Generates a restart condition after releasing the wait. Cautions concerning set timing For master reception: Cannot be set to 1 during transfer. Can be set to 1 only when the ACKEn bit has been cleared to 0 and slave has been notified of final reception. For master transmission: A start condition cannot be generated normally during the ACKn period. Set to 1 during the wait period. * Cannot be set to 1 at the same time as the SPTn bit. Condition for clearing (STTn bit = 0) * Cleared by loss in arbitration * Cleared after start condition is generated by master device * When the LRELn bit = 1 (exit from communications) * When the IICEn bit = 0 (operation stop) * Reset Note Start condition trigger Condition for setting (STTn bit = 1) * Set by instruction Note This flag's signal is invalid when the IICEn bit = 0. Remark The STTn bit is 0 if it is read after data setting. 558 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 (4/4) SPTn 0 1 Stop condition is not generated. Stop condition is generated (termination of master device's transfer). After the SDAn line goes to low level, either set the SCLn line to high level or wait until the SCLn pin goes to high level. Next, after the rated amount of time has elapsed, the SDAn line is changed from low level to high level and a stop condition is generated. Cautions concerning setting timing For master reception: Cannot be set to 1 during transfer. Can be set to 1 only when the ACKEn bit has been cleared to 0 and during the wait period after slave has been notified of final reception. For master transmission: A stop condition cannot be generated normally during the ACK signal period. Set to 1 during the wait period. * Cannot be set to 1 at the same time as the STTn bit. The SPTn bit can be set to 1 only when in master mode Note 1 Stop condition trigger . When the WTIMn bit has been cleared to 0, if the SPTn bit is set to 1 during the wait period that follows output of eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock. When a ninth clock must be output, the WTIMn bit should be set from 0 to 1 during the wait period following output of eight clocks, and the SPTn bit should be set to 1 during the wait period that follows output of the ninth clock. Condition for clearing (SPTn bit = 0) * Cleared by loss in arbitration * Automatically cleared after stop condition is detected * When the LRELn bit = 1 (exit from communications) * When the IICEn bit = 0 (operation stop) * Reset Note 2 Condition for setting (SPTn bit = 1) * Set by instruction Notes 1. Set the SPTn bit to 1 only in master mode. However, the SPTn bit must be set to 1 and a stop condition generated before the first stop condition is detected following the switch to operation enable status. For details, refer to 19.15 Cautions. 2. This flag's signal is invalid when the IICEn bit = 0. Caution When the IICSn.TRCn bit is set to 1, the WRELn bit is set to 1 during the ninth clock and wait is canceled, after which the TRCn bit is cleared to 0 and the SDAn line is set to high impedance. Remark The SPTn bit is 0 if it is read after data setting. User's Manual U16889EJ1V0UD 559 CHAPTER 19 I C BUS 2 (2) IIC status registers 0, 1 (IICS0, IICS1) The IICSn register indicates the status of the I2Cn bus. The IICSn register is read-only, in 8-bit or 1-bit units. After reset, IICSn is cleared to 00H. Caution When the main clock is stopped and the CPU is operating on the subclock, do not access the IICSn register using an access method that causes a wait. For details, refer to 3.4.8 (2). (1/3) After reset: 00H <7> IICSn (n = 0, 1) MSTSn R <6> ALDn <5> EXCn Address: IICS0 FFFFFD86H, IICS1 FFFFFD96H <4> COIn <3> TRCn <2> ACKDn <1> STDn <0> SPDn MSTSn 0 1 Master device status Slave device status or communication standby status Master device communication status Condition for setting (MSTSn bit = 1) * When a start condition is generated Condition for clearing (MSTSn bit = 0) * When a stop condition is detected * When the ALDn bit = 1 (arbitration loss) * Cleared by the IICCn.LRELn bit = 1 (exit from communications) * When the IICCn.IICEn bit changes from 1 to 0 (operation stop) * Reset ALDn 0 1 Detection of arbitration loss This status means either that there was no arbitration or that the arbitration result was a "win". This status indicates the arbitration result was a "loss". The MSTSn bit is cleared to 0. Condition for setting (ALDn bit = 1) Note Condition for clearing (ALDn bit = 0) * Automatically cleared after the IICSn register is read * Reset * When the IICEn bit changes from 1 to 0 (operation stop) * When the arbitration result is a "loss". Note This register is also cleared when a bit manipulation instruction is executed for bits other than the IICSn register. 560 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 (2/3) EXCn 0 1 Extension code was not received. Extension code was received. Condition for setting (EXCn bit = 1) * When the higher four bits of the received address data is either "0000" or "1111" (set at the rising edge of the eighth clock). Detection of extension code reception Condition for clearing (EXCn bit = 0) * When a start condition is detected * When a stop condition is detected * Cleared by the LRELn bit = 1 (exit from communications) * When the IICEn bit changes from 1 to 0 (operation stop) * Reset COIn 0 1 Addresses do not match. Addresses match. Detection of matching addresses Condition for clearing (COIn bit = 0) * When a start condition is detected * When a stop condition is detected * Cleared by the LRELn bit = 1 (exit from communications) * When the IICEn bit changes from 1 to 0 * Reset Condition for setting (COIn bit = 1) * When the received address matches the local address (SVAn register) (set at the rising edge of the eighth clock). TRCn 0 1 Detection of transmit/receive status Receive status (other than transmit status). The SDAn line is set for high impedance. Transmit status. The value in the SO latch is enabled for output to the SDAn line (valid starting at the rising edge of the first byte's ninth clock). Condition for setting (TRCn bit = 1) Master * When a start condition is generated Slave * When "1" is input in the first byte's LSB (transfer direction specification bit) Condition for clearing (TRCn bit = 0) * When a stop condition is detected * Cleared by the LRELn bit = 1 (exit from communications) * When the IICEn bit changes from 1 to 0 (operation stop) Note * Cleared by the IICCn.WRELn bit = 1 (wait release) * When the ALDn bit changes from 0 to 1 (arbitration loss) * Reset Master * When "1" is output to the first byte's LSB (transfer direction specification bit) Slave * When a start condition is detected When not used for communication Note The IICSn.TRCn bit is cleared to 0 and the SDAn line become high impedance when the IICCn.WRELn bit is set to 1 and wait state is released at the ninth clock with the TRCn bit = 1. User's Manual U16889EJ1V0UD 561 CHAPTER 19 I C BUS 2 (3/3) ACKDn 0 1 ACK signal was not detected. ACK signal was detected. Condition for setting (ACKDn bit = 1) * After the SDAn pin is set to low level at the rising edge of the SCLn pin's ninth clock Detection of acknowledge signal (ACK) Condition for clearing (ACKDn bit = 0) * When a stop condition is detected * At the rising edge of the next byte's first clock * Cleared by the LRELn bit = 1 (exit from communications) * When the IICEn bit changes from 1 to 0 (operation stop) * Reset STDn 0 1 Start condition was not detected. Detection of start condition Start condition was detected. This indicates that the address transfer period is in effect Condition for setting (STDn bit = 1) When a start condition is detected Condition for clearing (STDn bit = 0) * When a stop condition is detected * At the rising edge of the next byte's first clock following address transfer * Cleared by the LRELn bit = 1 (exit from communications) * When the IICEn bit changes from 1 to 0 (operation stop) * Reset SPDn 0 1 Stop condition was not detected. Detection of stop condition Stop condition was detected. The master device's communication is terminated and the bus is released. Condition for setting (SPDn bit = 1) When a stop condition is detected Condition for clearing (SPDn bit = 0) * At the rising edge of the address transfer byte's first clock following setting of this bit and detection of a start condition * When the IICEn bit changes from 1 to 0 (operation stop) * Reset 562 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 (3) IIC flag registers 0, 1 (IICF0, IICF1) IICF0 and IICF1 are registers that set the operation mode of I2Cn and indicate the status of the I2C bus. These registers can be read or written in 8-bit or 1-bit units. However, the STCFn and IICBSYn bits are readonly. The IICRSVn bit can be used to enable/disable the communication reservation function (refer to 19.14 Communication Reservation). The STCENn bit can be used to set the initial value of the IICBSYn bit (refer to 19.15 Cautions). The IICRSVn and STCENn bits can be written only when the operation of I2Cn is disabled (IICCn.IICEn bit = 0). When operation is enabled, the IICFn register can be read. After reset, IICFn is cleared to 00H. User's Manual U16889EJ1V0UD 563 CHAPTER 19 I C BUS 2 After reset: 00H <7> IICFn (n = 0, 1) STCFn 0 1 STCFn R/WNote <6> IICBSYn Address: IICF0 FFFFFD8AH, IICF1 FFFFFD9AH 5 0 4 0 3 0 2 0 <1> <0> STCENn IICRSVn IICCn.STTn clear flag Generate start condition Start condition generation unsuccessful: clear STTn flag Condition for setting (STCFn bit = 1) * Generating start condition unsuccessful and the STTn bit cleared to 0 when communication reservation is disabled (IICRSVn bit = 1). Condition for clearing (STCFn bit = 0) * Clearing by setting the STTn bit = 1 * Reset IICBSYn 0 1 Bus release status Bus communication status I2Cn bus status flag Condition for clearing (IICBSYn bit = 0) * Detection of stop condition * Reset Condition for setting (IICBSYn bit = 1) * Detection of start condition * Setting of the IICEn bit when the STCENn bit = 0 STCENn 0 1 Initial start enable trigger After operation is enabled (IICEn bit = 1), enable generation of a start condition upon detection of a stop condition. After operation is enabled (IICEn bit = 1), enable generation of a start condition without detecting a stop condition. Condition for setting (STCEn bit = 1) * Setting by instruction Condition for clearing (STCEn bit = 0) * Detection of start condition * Reset IICRSVn 0 1 Communication reservation function disable bit Enable communication reservation Disable communication reservation Condition for setting (IICRSVn bit = 1) * Setting by instruction Condition for clearing (IICRSVn bit = 0) * Clearing by instruction * Reset Note Bits 6 and 7 are read-only bits. Cautions 1. Write to the STCENn bit only when the operation is stopped (IICEn bit = 0). 2. As the bus release status (IICBSYn bit = 0) is recognized regardless of the actual bus status when the STCENn bit = 1, when generating the first start condition (STTn bit = 1), it is necessary to verify that no third party communications are in progress in order to prevent such communications from being destroyed. 3. Write to the IICRSVn bit only when the operation is stopped (IICEn bit = 0). 564 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 (4) IIC clock selection registers 0, 1 (IICCL0, IICCL1) The IICCLn register is used to set the transfer clock for the I2C bus. The IICCLn register can be read or written in 8-bit or 1-bit units. However, the CLDn and DADn bits are readonly. The SMCn, CLn1 and CLn0 bits are set in combination with the IICXn.CLXn bit (refer to 19.4 (6) I2Cn transfer clock setting method). After reset, IICCLn is cleared to 00H. After reset: 00H 7 IICCLn (n = 0, 1) 0 R/W Note Address: IICCL0 FFFFFD84H, IICCL1 FFFFFD94H <5> CLDn <4> DADn 3 SMCn 2 DFCn 1 CLn1 0 CLn0 6 0 CLDn 0 1 Detection of SCLn pin level (valid only when IICCn.IICEn bit = 1) The SCLn pin was detected at low level. The SCLn pin was detected at high level. Condition for setting (CLDn bit = 1) * When the SCLn pin is at high level Condition for clearing (CLDn bit = 0) * When the SCLn pin is at low level * When the IICEn bit = 0 (operation stop) * Reset DADn 0 1 Detection of SDAn pin level (valid only when IICEn bit = 1) The SDAn pin was detected at low level. The SDAn pin was detected at high level. Condition for setting (DADn bit = 1) * When the SDAn pin is at high level Condition for clearing (DADn bit = 0) * When the SDAn pin is at low level * When IICEn bit = 0 (operation stop) * Reset SMCn 0 1 Operates in standard mode. Operates in high-speed mode. Operation mode switching DFCn 0 1 Digital filter off. Digital filter on. Digital filter operation control Digital filter can be used only in high-speed mode. In high-speed mode, the transfer clock does not vary regardless of DFCn bit set/clear. The digital filter is used for noise elimination in high-speed mode. Note Bits 4 and 5 are read-only bits. User's Manual U16889EJ1V0UD 565 CHAPTER 19 I C BUS 2 (5) IIC function expansion registers 0, 1 (IICX0, IICX1) These registers set the function expansion of I2Cn (valid only in high-speed mode). These registers can be read or written in 8-bit or 1-bit units. The CLXn bit is set in combination with the IICCLn.SMCn, IICCLn.CLn1, and IICCLn.CLn0 bits (refer to 19.4 (6) I2Cn transfer clock setting method). After reset, IICXn is cleared to 00H. After reset: 00H 7 IICXn (n = 0, 1) 0 R/W 6 0 Address: IICX0 FFFFFD85H, IICX1 FFFFFD95H 5 0 4 0 3 0 2 0 1 0 <0> CLXn (6) I2Cn transfer clock setting method The I2Cn transfer clock frequency (fSCL) is calculated using the following expression (n = 0, 1). fSCL = 1/(m x T + tR + tF) m = 12, 24, 48, 54, 86, 88, 172, 198 (refer to Table 19-2 Selection Clock Setting.) T: tR: tF: 1/fXX SCLn rise time SCLn fall time For example, the I2Cn transfer clock frequency (fSCL) when fXX = 16 MHz, m = 172, tR = 200 ns, and tF = 50 ns is calculated using following expression. fSCL = 1/(172 x 62.5 ns + 200 ns + 50 ns) 90.9 kHz m x T + tR + tF tR m/2 x T tF m/2 x T SCLn SCLn inversion SCLn inversion SCLn inversion The selection clock is set using a combination of the IICCLn.SMCn, IICCLn.CLn1, and IICCLn.CLn0 bits and the IICXn.CLXn bit. 566 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 Table 19-2. Selection Clock Setting IICXn Bit 0 CLXn 0 0 0 0 0 0 0 1 1 1 1 Bit 3 SMCn 0 0 0 0 1 1 1 0 1 1 1 IICCLn Bit 1 CLn1 0 0 1 1 0 1 1 x 0 1 1 Bit 0 CLn0 0 1 0 1 x 0 1 x x 0 1 fXX/2 fXX/2 fXX fXX/3 fXX/2 fXX fXX/3 Setting prohibited fXX/2 fXX Setting prohibited fXX/24 fXX/12 8.00 MHz to 8.38 MHz 4.00 MHz to 4.19 MHz High-speed mode (SMCn bit = 1) fXX/88 fXX/172 fXX/86 fXX/198 fXX/48 fXX/24 fXX/54 4.0 MHz to 8.38 MHz 8.38 MHz to 16.76 MHz 4.19 MHz to 8.38 MHz 16.0 MHz to 19.8 MHz 8 MHz to 16.76 MHz 4 MHz to 8.38 MHz 16 MHz to 20 MHz High-speed mode (SMCn bit = 1) Normal mode (SMCn bit = 0) Selection Clock Transfer Clock (fXX/m) Settable Internal System Clock Frequency (fXX) Range Operation Mode Remarks 1. n = 0, 1 2. x: don't care (7) IIC shift registers 0, 1 (IIC0, IIC1) The IICn register is used for serial transmission/reception (shift operations) that is synchronized with the serial clock. The IICn register can be read or written in 8-bit units, but data should not be written to IICn during a data transfer. When the IICn register is written during wait, the wait is cancelled and data transfer is started. After reset, IICn is cleared to 00H. After reset: 00H 7 IICn (n = 0, 1) R/W 6 Address: IIC0 FFFFFD80H, IIC1 FFFFFD90H 5 4 3 2 1 0 (8) Slave address registers 0, 1 (SVA0, SVA1) The SVAn register holds the I2C bus's slave addresses. The SVAn register can be read or written in 8-bit units, but bit 0 should be fixed as 0. After reset, SVAn is cleared to 00H. After reset: 00H 7 SVAn (n = 0, 1) R/W 6 Address: SVA0 FFFFFD83H, SVA1 FFFFFD93H 5 4 3 2 1 0 0 User's Manual U16889EJ1V0UD 567 CHAPTER 19 I C BUS 2 19.5 Functions 19.5.1 Pin configuration The serial clock pin (SCLn) and serial data bus pin (SDAn) are configured as follows (n = 0, 1). SCLn ...............This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. SDAn ..............This pin is used for serial data input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. Since outputs from the serial clock line and the serial data bus line are N-ch open-drain outputs, an external pull-up resistor is required. Figure 19-4. Pin Configuration Diagram VDD Slave device Master device SCLn Clock output VDD (Clock input) SDAn Data output SDAn Data output Clock input SCLn (Clock output) Data input Data input 568 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 19.6 I2C Bus Definitions and Control Methods The following section describes the I2C bus's serial data communication format and the signals used by the I2C bus. The transfer timing for the "start condition", "data", and "stop condition" output via the I2C bus's serial data bus is shown below. Figure 19-5. I2C Bus's Serial Data Transfer Timing SCLn 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 SDAn Start Address condition R/W ACK Data ACK Data ACK Stop condition The master device outputs the start condition, slave address, and stop condition. The acknowledge signal (ACK) can be output by either the master or slave device (normally, it is output by the device that receives 8-bit data). The serial clock (SCLn) is continuously output by the master device. However, in the slave device, the SCLn's lowlevel period can be extended and a wait can be inserted (n = 0, 1). 19.6.1 Start condition A start condition is met when the SCLn pin is at high level and the SDAn pin changes from high level to low level. The start conditions for the SCLn pin and SDAn pin are signals that the master device outputs to the slave device when starting a serial transfer. Start conditions can be detected when the device is used as a slave (n = 0, 1). Figure 19-6. Start Conditions H SCLn SDAn A start condition is output when the IICCn.STTn bit is set to 1 after a stop condition has been detected (IICSn.SPDn bit = 1). When a start condition is detected, IICSn.STDn bit is set to 1. User's Manual U16889EJ1V0UD 569 CHAPTER 19 I C BUS 2 19.6.2 Addresses The 7 bits of data that follow the start condition are defined as an address. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via bus lines. Therefore, each slave device connected via the bus lines must have a unique address. The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data matches the data values stored in the SVAn register. If the address data matches the SVAn values, the slave device is selected and communicates with the master device until the master device transmits a start condition or stop condition (n = 0, 1). Figure 19-7. Address SCLn 1 2 3 4 5 6 7 8 9 SDAn AD6 AD5 AD4 AD3 Address AD2 AD1 AD0 R/W Note INTIICn Note The interrupt request signal (INTIICn) is generated if a local address or extension code is received during slave device operation. Remark n = 0, 1 The slave address and the eighth bit, which specifies the transfer direction as described in 19.6.3 written to the IICn register. The slave address is assigned to the higher 7 bits of the IICn register. Transfer direction specification below, are together written to the IICn register and are then output. Received addresses are 570 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 19.6.3 Transfer direction specification In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device. When the transfer direction specification bit has a value of 1, it indicates that the master device is receiving data from a slave device. Figure 19-8. Transfer Direction Specification SCLn 1 2 3 4 5 6 7 8 9 SDAn AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W Transfer direction specification Note INTIICn Note The interrupt request signal (INTIICn) is generated if a local address or extension code is received during slave device operation. Remark n = 0, 1 User's Manual U16889EJ1V0UD 571 CHAPTER 19 I C BUS 2 19.6.4 Acknowledge signal (ACK) The acknowledge signal (ACK) is used by the transmitting and receiving devices to confirm serial data reception. The receiving device returns one ACK signal for each 8 bits of data it receives. The transmitting device normally receives an ACK signal after transmitting 8 bits of data. However, when the master device is the receiving device, it does not output an ACK signal after receiving the final data to be transmitted. The transmitting device detects whether or not an ACK signal is returned after it transmits 8 bits of data. When an ACK signal is returned, the reception is judged as normal and processing continues. If the slave device does not return an ACK signal, the master device outputs either a stop condition or a restart condition and then stops the current transmission. Failure to return an ACK signal may be caused by the following two factors. <1> Reception was not performed normally. <2> The final data was received. When the receiving device sets the SDAn line to low level during the ninth clock, the ACK signal becomes active (normal receive response). When the IICCn.ACKEn bit is set to 1, automatic ACK signal generation is enabled (n = 0, 1). Transmission of the eighth bit following the 7 address data bits causes the IICSn.TRCn bit to be set. When this TRCn bit's value is 0, it indicates receive mode. Therefore, the ACKEn bit should be set to 1. When the slave device is receiving (when TRCn bit = 0), if the slave device does not need to receive any more data after receiving several bytes, clearing the ACKEn bit to 0 will prevent the master device from starting transmission of the subsequent data. Similarly, when the master device is receiving (when TRCn bit = 0) and the subsequent data is not needed and when either a restart condition or a stop condition should therefore be output, clearing the ACKEn bit to 0 will prevent the ACK signal from being returned. This prevents the MSB data from being output via the SDAn line (i.e., stops transmission) during transmission from the slave device. Figure 19-9. Acknowledge Signal (ACK) SCLn 1 2 3 4 5 6 7 8 9 SDAn AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W ACK Remark n = 0, 1 When the local address is received, an ACK signal is automatically output in synchronization with the falling edge of the SCLn pin's eighth clock regardless of the ACKEn bit value. No ACK signal is output if the received address is not a local address (n = 0, 1). The ACK signal output method during data reception is based on the wait timing setting, as described below. * When 8-clock wait is selected: (IICCn.WTIMn bit = 0) * When 9-clock wait is selected: (WTIMn bit = 1) ACK signal is output at the falling edge of the SCLn pin's eighth clock if the ACKEn bit is set to 1 before wait cancellation. ACK signal is automatically output at the falling edge of the SCLn pin's eighth clock if the ACKEn bit has already been set to 1. 572 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 19.6.5 Stop condition When the SCLn pin is at high level, changing the SDAn pin from low level to high level generates a stop condition (n = 0, 1). A stop condition is a signal that the master device outputs to the slave device when serial transfer has been completed. Stop conditions can be detected when the device is used as a slave. Figure 19-10. Stop Condition H SCLn SDAn Remark n = 0, 1 A stop condition is generated when the IICCn.SPTn bit is set to 1. When the stop condition is detected, the IICSn.SPDn bit is set to 1 and the interrupt request signal (INTIICn) is generated when the IICCn.SPIEn bit is set to 1. User's Manual U16889EJ1V0UD 573 CHAPTER 19 I C BUS 2 19.6.6 Wait signal (WAIT) The wait signal (WAIT) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCLn pin to low level notifies the communication partner of the wait status. When wait status has been canceled for both the master and slave devices, the next data transfer can begin (n = 0, 1). Figure 19-11. Wait Signal (1/2) (a) When master device has a nine-clock wait and slave device has an eight-clock wait (master: transmission, slave: reception, and IICCn.ACKEn bit = 1) Master Master returns to high Wait after output impedance but slave is in wait state (low level). of ninth clock. IICn data write (cancel wait) IICn SCLn 6 7 8 9 1 2 3 Slave Wait after output of eighth clock. IICn SCLn FFH is written to IICn register or IICCn.WRELn bit is set to 1. ACKEn H Transfer lines Wait signal from slave 6 7 8 9 Wait signal from master 1 2 3 SCLn SDAn D2 D1 D0 ACK D7 D6 D5 Remark n = 0, 1 574 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 Figure 19-11. Wait Signal (2/2) (b) When master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and ACKEn = 1) Master IICn Master and slave both wait after output of ninth clock. IICn data write (cancel wait) SCLn Slave IICn SCLn 6 7 8 9 1 2 3 FFH is written to IICn register or WRELn bit is set to 1. ACKEn Transfer lines SCLn H Wait signal from master and slave 6 7 8 9 Wait signal from slave 1 2 3 SDAn D2 D1 D0 ACK D7 D6 D5 Output according to previously set ACKEn bit value Remark n = 0, 1 A wait may be automatically generated depending on the setting for the IICCn.WTIMn bit. Normally, when the IICCn.WRELn bit is set to 1 or when FFH is written to the IICn register, the wait status is canceled and the transmitting side writes data to the IICn register to cancel the wait status. The master device can also cancel the wait status via either of the following methods. * By setting the IICCn.STTn bit to 1 * By setting the IICCn.SPTn bit to 1 User's Manual U16889EJ1V0UD 575 CHAPTER 19 I C BUS 2 19.7 I2C Interrupt Request Signals (INTIICn) The following shows the value of the IICSn register at the INTIICn interrupt request signal generation timing and at the INTIICn signal timing (n = 0, 1). 19.7.1 Master device operation (1) Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception) <1> When IICCn.WTIMn bit = 0 SPTn bit = 1 ST AD6 to AD0 RW AK 1 1: IICSn register = 10XXX110B 2: IICSn register = 10XXX000B 3: IICSn register = 10XXX000B (WTIMn bit = 1) 4: IICSn register = 10XXXX00B 5: IICSn register = 00000001B D7 to D0 2 AK D7 to D0 3 AK 4 SP 5 Remark : Always generated : Generated only when IICCn.SPIEn bit = 1 X: don't care n = 0, 1 <2> When WTIMn bit = 1 IICCn.SPTn bit = 1 ST AD6 to AD0 RW AK 1 1: IICSn register = 10XXX110B 2: IICSn register = 10XXX100B 3: IICSn register = 10XXXX00B 4: IICSn register = 00000001B D7 to D0 AK 2 D7 to D0 AK 3 SP 4 Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care n = 0, 1 576 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 (2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) <1> When WTIMn bit = 0 IICCn.STTn bit = 1 ST AD6 to AD0 RW AK 1 D7 to D0 2 AK 3 ST AD6 to AD0 RW AK 4 D7 to D0 5 AK 6 SPTn bit = 1 SP 7 1: IICSn register = 10XXX110B 2: IICSn register = 10XXX000B (WTIMn bit = 1) 3: IICSn register = 10XXXX00B (WTIMn bit = 0) 4: IICSn register = 10XXX110B (WTIMn bit = 0) 5: IICSn register = 10XXX000B (WTIMn bit = 1) 6: IICSn register = 10XXXX00B 7: IICSn register = 00000001B Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care n = 0, 1 <2> When WTIMn bit = 1 STTn bit = 1 ST AD6 to AD0 RW AK 1 D7 to D0 AK 2 ST AD6 to AD0 RW AK 3 D7 to D0 AK 4 SPTn bit = 1 SP 5 1: IICSn register = 10XXX110B 2: IICSn register = 10XXXX00B 3: IICSn register = 10XXX110B 4: IICSn register = 10XXXX00B 5: IICSn register = 00000001B Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care n = 0, 1 User's Manual U16889EJ1V0UD 577 CHAPTER 19 I C BUS 2 (3) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) <1> When WTIMn bit = 0 SPTn bit = 1 ST AD6 to AD0 RW AK 1 1: IICSn register = 1010X110B 2: IICSn register = 1010X000B 3: IICSn register = 1010X000B (WTIMn bit = 1) 4: IICSn register = 1010XX00B 5: IICSn register = 00000001B D7 to D0 2 AK D7 to D0 3 AK 4 SP 5 Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care n = 0, 1 <2> When WTIMn bit = 1 SPTn bit = 1 ST AD6 to AD0 RW AK 1 1: IICSn register = 1010X110B 2: IICSn register = 1010X100B 3: IICSn register = 1010XX00B 4: IICSn register = 00000001B D7 to D0 AK 2 D7 to D0 AK 3 SP 4 Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care n = 0, 1 578 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 19.7.2 Slave device operation (when receiving slave address data (match with address)) (1) Start ~ Address ~ Data ~ Data ~ Stop <1> When IICCn.WTIMn bit = 0 ST AD6 to AD0 RW AK 1 1: IICSn register = 0001X110B 2: IICSn register = 0001X000B 3: IICSn register = 0001X000B 4: IICSn register = 00000001B D7 to D0 2 AK D7 to D0 3 AK SP 4 Remark : Always generated : Generated only when IICCn.SPIEn bit = 1 X: don't care n = 0, 1 <2> When WTIMn bit = 1 ST AD6 to AD0 RW AK 1 1: IICSn register = 0001X110B 2: IICSn register = 0001X100B 3: IICSn register = 0001XX00B 4: IICSn register = 00000001B D7 to D0 AK 2 D7 to D0 AK 3 SP 4 Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care n = 0, 1 User's Manual U16889EJ1V0UD 579 CHAPTER 19 I C BUS 2 (2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, match with address) ST AD6 to AD0 RW AK 1 D7 to D0 2 AK ST AD6 to AD0 RW AK 3 D7 to D0 4 AK SP 5 1: IICSn register = 0001X110B 2: IICSn register = 0001X000B 3: IICSn register = 0001X110B 4: IICSn register = 0001X000B 5: IICSn register = 00000001B Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care n = 0, 1 <2> When WTIMn bit = 1 (after restart, match with address) ST AD6 to AD0 RW AK 1 D7 to D0 AK 2 ST AD6 to AD0 RW AK 3 D7 to D0 AK 4 SP 5 1: IICSn register = 0001X110B 2: IICSn register = 0001XX00B 3: IICSn register = 0001X110B 4: IICSn register = 0001XX00B 5: IICSn register = 00000001B Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care n = 0, 1 580 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 (3) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, extension code reception) ST AD6 to AD0 RW AK 1 D7 to D0 2 AK ST AD6 to AD0 RW 3 AK D7 to D0 4 AK SP 5 1: IICSn register = 0001X110B 2: IICSn register = 0001X000B 3: IICSn register = 0010X010B 4: IICSn register = 0010X000B 5: IICSn register = 00000001B Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care n = 0, 1 <2> When WTIMn bit = 1 (after restart, extension code reception) ST AD6 to AD0 RW AK 1 D7 to D0 AK 2 ST AD6 to AD0 RW 3 AK 4 D7 to D0 AK 5 SP 6 1: IICSn register = 0001X110B 2: IICSn register = 0001XX00B 3: IICSn register = 0010X010B 4: IICSn register = 0010X110B 5: IICSn register = 0010XX00B 6: IICSn register = 00000001B Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care n = 0, 1 User's Manual U16889EJ1V0UD 581 CHAPTER 19 I C BUS 2 (4) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, mismatch with address (= not extension code)) ST AD6 to AD0 RW AK 1 D7 to D0 2 AK ST AD6 to AD0 RW AK 3 D7 to D0 AK SP 4 1: IICSn register = 0001X110B 2: IICSn register = 0001X000B 3: IICSn register = 00000X10B 4: IICSn register = 00000001B Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care n = 0, 1 <2> When WTIMn bit = 1 (after restart, mismatch with address (= not extension code)) ST AD6 to AD0 RW AK 1 D7 to D0 AK 2 ST AD6 to AD0 RW AK 3 D7 to D0 AK SP 4 1: IICSn register = 0001X110B 2: IICSn register = 0001XX00B 3: IICSn register = 00000X10B 4: IICSn register = 00000001B Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care n = 0, 1 582 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 19.7.3 Slave device operation (when receiving extension code) (1) Start ~ Code ~ Data ~ Data ~ Stop <1> When IICCn.WTIMn bit = 0 ST AD6 to AD0 RW 1 1: IICSn register = 0010X010B 2: IICSn register = 0010X000B 3: IICSn register = 0010X000B 4: IICSn register = 00000001B AK D7 to D0 2 AK D7 to D0 3 AK SP 4 Remark : Always generated : Generated only when IICCn.SPIEn bit = 1 X: don't care n = 0, 1 <2> When WTIMn bit = 1 ST AD6 to AD0 RW 1 1: IICSn register = 0010X010B 2: IICSn register = 0010X110B 3: IICSn register = 0010X100B 4: IICSn register = 0010XX00B 5: IICSn register = 00000001B AK 2 D7 to D0 AK 3 D7 to D0 AK 4 SP 5 Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care n = 0, 1 User's Manual U16889EJ1V0UD 583 CHAPTER 19 I C BUS 2 (2) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, match with address) ST AD6 to AD0 RW 1 AK D7 to D0 2 AK ST AD6 to AD0 RW AK 3 D7 to D0 4 AK SP 5 1: IICSn register = 0010X010B 2: IICSn register = 0010X000B 3: IICSn register = 0001X110B 4: IICSn register = 0001X000B 5: IICSn register = 00000001B Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care n = 0, 1 <2> When WTIMn bit = 1 (after restart, match with address) ST AD6 to AD0 RW 1 AK 2 D7 to D0 AK 3 ST AD6 to AD0 RW AK 4 D7 to D0 AK 5 SP 6 1: IICSn register = 0010X010B 2: IICSn register = 0010X110B 3: IICSn register = 0010XX00B 4: IICSn register = 0001X110B 5: IICSn register = 0001XX00B 6: IICSn register = 00000001B Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care n = 0, 1 584 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 (3) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, extension code reception) ST AD6 to AD0 RW 1 AK D7 to D0 2 AK ST AD6 to AD0 RW 3 AK D7 to D0 4 AK SP 5 1: IICSn register = 0010X010B 2: IICSn register = 0010X000B 3: IICSn register = 0010X010B 4: IICSn register = 0010X000B 5: IICSn register = 00000001B Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care n = 0, 1 <2> When WTIMn bit = 1 (after restart, extension code reception) ST AD6 to AD0 RW 1 AK 2 D7 to D0 AK 3 ST AD6 to AD0 RW 4 AK 5 D7 to D0 AK 6 SP 7 1: IICSn register = 0010X010B 2: IICSn register = 0010X110B 3: IICSn register = 0010XX00B 4: IICSn register = 0010X010B 5: IICSn register = 0010X110B 6: IICSn register = 0010XX00B 7: IICSn register = 00000001B Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care n = 0, 1 User's Manual U16889EJ1V0UD 585 CHAPTER 19 I C BUS 2 (4) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, mismatch with address (= not extension code)) ST AD6 to AD0 RW 1 AK D7 to D0 2 AK ST AD6 to AD0 RW AK 3 D7 to D0 AK SP 4 1: IICSn register = 0010X010B 2: IICSn register = 0010X000B 3: IICSn register = 00000X10B 4: IICSn register = 00000001B Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care n = 0, 1 <2> When WTIMn bit = 1 (after restart, mismatch with address (= not extension code)) ST AD6 to AD0 RW 1 AK 2 D7 to D0 AK 3 ST AD6 to AD0 RW AK 4 D7 to D0 AK SP 5 1: IICSn register = 0010X010B 2: IICSn register = 0010X110B 3: IICSn register = 0010XX00B 4: IICSn register = 00000X10B 5: IICSn register = 00000001B Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care n = 0, 1 586 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 19.7.4 Operation without communication (1) Start ~ Code ~ Data ~ Data ~ Stop ST AD6 to AD0 RW AK D7 to D0 AK D7 to D0 AK SP 1 1: IICSn register = 00000001B Remark : Generated only when IICCn.SPIEn bit = 1 n = 0, 1 19.7.5 Arbitration loss operation (operation as slave after arbitration loss) (1) When arbitration loss occurs during transmission of slave address data <1> When IICCn.WTIMn bit = 0 ST AD6 to AD0 RW AK 1 D7 to D0 2 AK D7 to D0 3 AK SP 4 1: IICSn register = 0101X110B (Example: when IICSn.ALDn bit is read during interrupt servicing) 2: IICSn register = 0001X000B 3: IICSn register = 0001X000B 4: IICSn register = 00000001B Remark : Always generated : Generated only when IICCn.SPIEn bit = 1 X: don't care n = 0, 1 <2> When WTIMn bit = 1 ST AD6 to AD0 RW AK 1 D7 to D0 AK 2 D7 to D0 AK 3 SP 4 1: IICSn register = 0101X110B (Example: when ALDn bit is read during interrupt servicing) 2: IICSn register = 0001X100B 3: IICSn register = 0001XX00B 4: IICSn register = 00000001B Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care n = 0, 1 User's Manual U16889EJ1V0UD 587 CHAPTER 19 I C BUS 2 (2) When arbitration loss occurs during transmission of extension code <1> When WTIMn bit = 0 ST AD6 to AD0 RW 1 AK D7 to D0 2 AK D7 to D0 3 AK SP 4 1: IICSn register = 0110X010B (Example: when ALDn bit is read during interrupt servicing) 2: IICSn register = 0010X000B 3: IICSn register = 0010X000B 4: IICSn register = 00000001B Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care n = 0, 1 <2> When WTIMn bit = 1 ST AD6 to AD0 RW 1 AK 2 D7 to D0 AK 3 D7 to D0 AK 4 SP 5 1: IICSn register = 0110X010B (Example: when ALDn bit is read during interrupt servicing) 2: IICSn register = 0010X110B 3: IICSn register = 0010X100B 4: IICSn register = 0010XX00B 5: IICSn register = 00000001B Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care n = 0, 1 588 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 19.7.6 Operation when arbitration loss occurs (no communication after arbitration loss) (1) When arbitration loss occurs during transmission of slave address data ST AD6 to AD0 RW AK 1 D7 to D0 AK D7 to D0 AK SP 2 1: IICSn register = 01000110B (Example: when IICSn.ALDn bit is read during interrupt servicing) 2: IICSn register = 00000001B Remark : Always generated : Generated only when IICCn.SPIEn bit = 1 n = 0, 1 (2) When arbitration loss occurs during transmission of extension code ST AD6 to AD0 RW 1 AK D7 to D0 AK D7 to D0 AK SP 2 1: IICSn register = 0110X010B (Example: when ALDn bit is read during interrupt servicing) IICCn.LRELn bit is set to 1 by software 2: IICSn register = 00000001B Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care n = 0, 1 User's Manual U16889EJ1V0UD 589 CHAPTER 19 I C BUS 2 (3) When arbitration loss occurs during data transfer <1> When IICCn.WTIMn bit = 0 ST AD6 to AD0 RW AK 1 D7 to D0 2 AK D7 to D0 AK SP 3 1: IICSn register = 10001110B 2: IICSn register = 01000000B (Example: when ALDn bit is read during interrupt servicing) 3: IICSn register = 00000001B Remark : Always generated : Generated only when SPIEn bit = 1 n = 0, 1 <2> When WTIMn bit = 1 ST AD6 to AD0 RW AK 1 D7 to D0 AK 2 D7 to D0 AK SP 3 1: IICSn register = 10001110B 2: IICSn register = 01000100B (Example: when ALDn bit is read during interrupt servicing) 3: IICSn register = 00000001B Remark : Always generated : Generated only when SPIEn bit = 1 n = 0, 1 590 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 (4) When loss occurs due to restart condition during data transfer <1> Not extension code (Example: mismatches with address) ST AD6 to AD0 RW AK 1 D7 to Dn ST AD6 to AD0 RW AK 2 D7 to D0 AK SP 3 1: IICSn register = 1000X110B 2: IICSn register = 01000110B (Example: when ALDn bit is read during interrupt servicing) 3: IICSn register = 00000001B Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care Dn = D6 to D0 n = 0, 1 <2> Extension code ST AD6 to AD0 RW AK 1 D7 to Dn ST AD6 to AD0 RW 2 AK D7 to D0 AK SP 3 1: IICSn register = 1000X110B 2: IICSn register = 0110X010B (Example: when ALDn bit is read during interrupt servicing) LRELn bit is set to 1 by software 3: IICSn register = 00000001B Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care Dn = D6 to D0 n = 0, 1 User's Manual U16889EJ1V0UD 591 CHAPTER 19 I C BUS 2 (5) When loss occurs due to stop condition during data transfer ST AD6 to AD0 RW AK 1 D7 to Dn SP 2 1: IICSn register = 1000X110B 2: IICSn register = 01000001B Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care Dn = D6 to D0 n = 0, 1 (6) When arbitration loss occurs due to low-level data when attempting to generate a restart condition When WTIMn bit = 1 IICCn.STTn bit = 1 ST AD6 to AD0 RW AK 1 D7 to D0 AK 2 D7 to D0 AK 3 D7 to D0 AK SP 4 1: IICSn register = 1000X110B 2: IICSn register = 1000XX00B 3: IICSn register = 01000100B (Example: when ALDn bit is read during interrupt servicing) 4: IICSn register = 00000001B Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care n = 0, 1 592 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 (7) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition When WTIMn bit = 1 STTn bit = 1 ST AD6 to AD0 RW AK 1 D7 to D0 AK 2 SP 3 1: IICSn register = 1000X110B 2: IICSn register = 1000XX00B 3: IICSn register = 01000001B Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care n = 0, 1 (8) When arbitration loss occurs due to low-level data when attempting to generate a stop condition When WTIMn bit = 1 IICCn.SPTn bit = 1 ST AD6 to AD0 RW AK 1 D7 to D0 AK 2 D7 to D0 AK 3 D7 to D0 AK SP 4 1: IICSn register = 1000X110B 2: IICSn register = 1000XX00B 3: IICSn register = 01000000B (Example: when ALDn bit is read during interrupt servicing) 4: IICSn register = 00000001B Remark : Always generated : Generated only when SPIEn bit = 1 X: don't care n = 0, 1 User's Manual U16889EJ1V0UD 593 CHAPTER 19 I C BUS 2 19.8 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control The setting of the IICCn.WTIMn bit determines the timing by which the INTIICn signal is generated and the corresponding wait control, as shown below. Table 19-3. INTIICn Signal Generation Timing and Wait Control WTIMn Bit During Slave Device Operation Address 0 1 9 9 Notes 1, 2 During Master Device Operation Address 9 9 Data Reception 8 9 Data Transmission 8 9 Data Reception 8 9 Note 2 Data Transmission 8 9 Note 2 Notes 1, 2 Note 2 Note 2 Notes 1. The slave device's INTIICn signal and wait period occurs at the falling edge of the ninth clock only when there is a match with the address set to the SVAn register. At this point, an ACK signal is output regardless of the value set to the IICCn.ACKEn bit. For a slave device that has received an extension code, the INTIICn signal occurs at the falling edge of the eighth clock. When the address does not match after restart, the INTIICn signal is generated at the falling edge of the ninth clock, but no wait occurs. 2. If the received address does not match the contents of the SVAn register and extension codes have not been received, neither the INTIICn signal nor a wait occurs. Remarks 1. The numbers in the table indicate the number of the serial clock's clock signals. Interrupt requests and wait control are both synchronized with the falling edge of these clock signals. 2. n = 0, 1 (1) During address transmission/reception * Slave device operation: * Master device operation: Interrupt and wait timing are determined depending on the conditions in Notes 1 and 2 above regardless of the WTIMn bit. Interrupt and wait timing occur at the falling edge of the ninth clock regardless of the WTIMn bit. (2) During data reception * Master/slave device operation: Interrupt and wait timing are determined according to the WTIMn bit. (3) During data transmission * Master/slave device operation: Interrupt and wait timing are determined according to the WTIMn bit. 594 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 (4) Wait cancellation method The four wait cancellation methods are as follows. * By setting the IICCn.WRELn bit to 1 * By writing to the IICn register * By start condition setting (IICCn.STTn bit = 1)Note * By stop condition setting (IICCn.SPTn bit = 1)Note Note Master only When an 8-clock wait has been selected (WTIMn bit = 0), the output level of the ACK signal must be determined prior to wait cancellation. Remark n = 0, 1 (5) Stop condition detection The INTIICn signal is generated when a stop condition is detected. Remark n = 0, 1 19.9 Address Match Detection Method When in I2C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match detection is performed automatically by hardware. An INTIICn interrupt request signal occurs when a local address has been set to the SVAn register and when the address set to the SVAn register matches the slave address sent by the master device, or when an extension code has been received (n = 0, 1). 19.10 Error Detection In I2C bus mode, the status of the serial data bus (SDAn) during data transmission is captured by the IICn register of the transmitting device, so the IICn register data prior to transmission can be compared with the transmitted IICn register data to enable detection of transmission errors. A transmission error is judged as having occurred when the compared data values do not match (n = 0, 1). User's Manual U16889EJ1V0UD 595 CHAPTER 19 I C BUS 2 19.11 Extension Code (1) When the higher 4 bits of the receive address are either 0000 or 1111, the extension code flag (EXCn) is set for extension code reception and an interrupt request signal (INTIICn) is issued at the falling edge of the eighth clock. The local address stored in the SVAn register is not affected. (2) If 11110xx0 is set to the SVAn register by a 10-bit address transfer and 11110xx0 is transferred from the master device, the results are as follows. Note that the INTIICn signal occurs at the falling edge of the eighth clock. * Higher 4 bits of data match: IICSn.EXCn bit = 1 * 7 bits of data match: IICSn.COIn bit = 1 (3) Since the processing after the INTIICn signal occurs differs according to the data that follows the extension code, such processing is performed by software. For example, when operation as a slave is not desired after the extension code is received, set the IICCn.LRELn bit to 1 and the CPU will enter the next communication wait state. Remark n = 0, 1 Table 19-4. Extension Code Bit Definitions Slave Address 0000 0000 0000 0000 1111 000 000 001 010 0xx R/W Bit 0 1 X X X General call address Start byte CBUS address Address that is reserved for different bus format 10-bit slave address specification Description 596 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 19.12 Arbitration When several master devices simultaneously output a start condition (when the IICCn.STTn bit is set to 1 before the IICSn.STDn bit is set to 1), communication among the master devices is performed as the number of clocks is adjusted until the data differs. This kind of operation is called arbitration (n = 0, 1). When one of the master devices loses in arbitration, an arbitration loss flag (IICSn.ALDn bit) is set (1) via the timing by which the arbitration loss occurred, and the SCLn and SDAn lines are both set for high impedance, which releases the bus. The arbitration loss is detected based on the timing of the next interrupt request signal (INTIICn) (the eighth or ninth clock, when a stop condition is detected, etc.) and the ALDn bit = 1 setting that has been made by software. For details of interrupt request timing, refer to 19.7 I2C Interrupt Request Signals (INTIICn). Figure 19-12. Arbitration Timing Example Master 1 SCLn Hi-Z SDAn Master 2 SCLn Hi-Z Master 1 loses arbitration SDAn Transfer lines SCLn SDAn Remark n = 0, 1 User's Manual U16889EJ1V0UD 597 CHAPTER 19 I C BUS 2 Table 19-5. Status During Arbitration and Interrupt Request Generation Timing Status During Arbitration During address transmission Read/write data after address transmission During extension code transmission Read/write data after extension code transmission During data transmission During ACK signal transfer period after data reception When restart condition is detected during data transfer When stop condition is detected during data transfer When the SDAn pin is at low level while attempting to output a restart condition When stop condition is detected while attempting to output a restart condition When the SDAn pin is at low level while attempting to output a stop condition When the SCLn pin is at low level while attempting to output a restart condition At falling edge of eighth or ninth clock following byte transfer Note 1 Interrupt Request Generation Timing At falling edge of eighth or ninth clock following byte transfer Note 1 When stop condition is output (when IICCn.SPIEn bit = 1) Note 2 At falling edge of eighth or ninth clock following byte transfer Note 2 Note 1 When stop condition is output (when SPIEn bit = 1) Notes 1. When the IICCn.WTIMn bit = 1, an interrupt request occurs at the falling edge of the ninth clock. When the WTIMn bit = 0 and the extension code's slave address is received, an interrupt request occurs at the falling edge of the eighth clock. 2. Remark When there is a possibility that arbitration will occur, set the SPIEn bit = 1 for master device operation. n = 0, 1 19.13 Wakeup Function The I2C bus slave function is a function that generates an interrupt request signal (INTIICn) when a local address or extension code has been received. This function makes processing more efficient by preventing unnecessary interrupt requests from occurring when addresses do not match. When a start condition is detected, wakeup standby mode is set. This wakeup standby mode is in effect while addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has output a start condition) to a slave device. However, when a stop condition is detected, the IICCn.SPIEn bit is set regardless of the wake up function, and this determines whether interrupt requests are enabled or disabled (n = 0, 1). 598 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 19.14 Communication Reservation 19.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0) To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not used. * When arbitration results in neither master nor slave operation * When an extension code is received and slave operation is disabled (ACK signal is not returned and the bus was released when the IICCn.LRELn bit was set to "1"). If the IICCn.STTn bit is set (1) while the bus is not used, a start condition is automatically generated and wait status is set after the bus is released (after a stop condition is detected). When the bus release is detected (when a stop condition is detected), writing to the IICn register causes the master's address transfer to start. At this point, the IICCn.SPIEn bit should be set (1). When the STTn bit has been set (1), the operation mode (as start condition or as communication reservation) is determined according to the bus status. If the bus has been released.............................................. a start condition is generated If the bus has not been released (standby mode) .............. communication reservation To detect which operation mode has been determined for the STTn bit, set the STTn bit (1), wait for the wait period, then check the IICSn.MSTSn bit. Wait periods, which should be set via software, are listed in Table 19-6. These wait periods can be set via the settings for the IICCLn.SMCn, IICCLn.CLn1, and IICCLn.CLn0 bits. Table 19-6. Wait Periods SMCn 0 0 0 0 1 1 1 1 CLn1 0 0 1 1 0 0 1 1 CLn0 0 1 0 1 0 1 0 1 32 clocks 13 clocks Wait Period 26 clocks 46 clocks 92 clocks 37 clocks 16 clocks Remark n = 0, 1 User's Manual U16889EJ1V0UD 599 CHAPTER 19 I C BUS 2 The communication reservation timing is shown below. Figure 19-13. Communication Reservation Timing Program processing STTn =1 Write to IICn Hardware processing Communication reservation Set SPDn and INTIICn Set STDn SCLn 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 SDAn Output by master with bus access IICn: STTn: STDn: SPDn: Remark IIC shift register n Bit 1 of IIC control register n (IICCn) Bit 1 of IIC status register n (IICSn) Bit 0 of IIC status register n (IICSn) n = 0, 1 Communication reservations are accepted via the following timing. 1). After the IICSn.STDn bit is set to 1, a communication reservation can be made by setting the IICCn.STTn bit to 1 before a stop condition is detected (n = 0, Figure 19-14. Timing for Accepting Communication Reservations SCLn SDAn STDn SPDn Standby mode Remark n = 0, 1 User's Manual U16889EJ1V0UD 600 CHAPTER 19 I C BUS 2 The communication reservation flowchart is illustrated below. Figure 19-15. Communication Reservation Flowchart DI STTn = 1 ; Sets STTn flag (communication reservation). Define communication reservation ; Defines that communication reservation is in effect (defines and sets user flag to any part of RAM). Wait ; Gets wait period set by software (refer to Table 19-6). Note (Communication reservation) Yes MSTSn = 0? ; Confirmation of communication reservation No (Generate start condition) Cancel communication reservation ; Clear user flag. IICn xxH ; IICn write operation EI Note The communication reservation operation executes a write to the IICn register when a stop condition interrupt request occurs. Remark n = 0, 1 User's Manual U16889EJ1V0UD 601 CHAPTER 19 I C BUS 2 19.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1) When the IICCn.STTn bit is set when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. The following two statuses are included in the status where bus is not used. * When arbitration results in neither master nor slave operation * When an extension code is received and slave operation is disabled (ACK signal is not returned and the bus was released when the IICCn.LRELn bit was set to 1) To confirm whether the start condition was generated or request was rejected, check the IICFn.STCFn flag. The time shown in Table 19-7 is required until the STCFn flag is set after setting the STTn bit = 1. Therefore, secure the time by software. Table 19-7. Wait Periods CLn1 0 0 1 1 CLn0 0 1 0 1 Wait Period 6 clocks 6 clocks 3 clocks 9 clocks Remarks 1. x: don't care 2. n = 0, 1 602 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 19.15 Cautions (1) When IICFn.STCENn bit = 0 Immediately after I2Cn operation is enabled, the bus communication status (IICFn.IICBSYn bit = 1) is recognized regardless of the actual bus status. To execute master communication in the status where a stop condition has not been detected, generate a stop condition and then release the bus before starting the master communication. Use the following sequence for generating a stop condition. <1> Set the IICCLn register. <2> Set the IICCn.IICEn bit. <3> Set the IICCn.SPTn bit. (2) When IICFn.STCENn bit = 1 Immediately after I2Cn operation is enabled, the bus released status (IICBSYn bit = 0) is recognized regardless of the actual bus status. To issue the first start condition (IICCn.STTn bit = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. Remark n = 0, 1 19.16 Communication Operations 19.16.1 Master operation 1 The following shows the flowchart for master communication when the communication reservation function is enabled (IICFn.IICRSVn bit = 0) and the master operation is started after a stop condition is detected (IICFn.STCENn bit = 0). User's Manual U16889EJ1V0UD 603 CHAPTER 19 I C BUS 2 Figure 19-16. Master Operation Flowchart (1) START IICCLn xxH Select transfer clock IICCn xxH IICEn = SPIEn = WTIMn = 1 SPTn = 1 INTIICn = 1? No Yes (stop condition detection) STTn = 1 Wait Wait time is secured by software (refer to Table 19-6) MSTSn = 1? No Communication reservation No Yes (start condition generation) INTIICn = 1? Yes Start IICn write transfer Stop condition detection, start condition generation by communication reservation No INTIICn = 1? Yes ACKDn = 1? Yes Address transfer completion TRCn = 1? Yes (transmit) Start IICn write transfer No Generate stop condition (no slave with matching address) No (receive) End WTIMn = 0 ACKEn = 1 INTIICn = 1? Yes Data processing No No WRELn = 1 Start reception ACKDn = 1? No Yes INTIICn = 1? Yes Data processing No (restart) Transfer completed? Transfer completed? Yes Generate stop condition SPTn = 1 Yes ACKEn = 0 No End Remark n = 0, 1 604 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 19.16.2 Master operation 2 The following shows the flowchart for master communication when the communication reservation function is disabled (IICRSVn bit = 1) and the master operation is started without detecting a stop condition (STCENn bit = 1). Figure 19-17. Master Operation Flowchart (2) START IICCLn xxH IICFn xxH IICCn xxH IICEn = SPIEn = WTIMn = 1 Transfer clock selection IICFn register setting IICCn register initial setting IICBSYn = 0? Yes STTn = 1 No Insert wait Wait time is secured by software (refer to Table 19-7) STCFn = 0? Yes Start IICn write transfer No Stop master communication Master communication is stopped because bus is occupied INTIICn = 1? No Yes (address transfer completion) ACKDn = 1? Yes TRCn = 1? Yes (transmit) Start IICn write transfer WRELn = 1 Start reception INTIICn = 1? Yes Data processing No No No (receive) Generate stop condition (no slave with matching address) WTIMn = 0 ACKEn = 1 No End INTIICn = 1? Yes Data processing ACKDn = 1? Yes No No Reception completed? Yes ACKEn = 0 No (restart) Transfer completed? Yes SPTn = 1 Generate stop condition End Remark n = 0, 1 User's Manual U16889EJ1V0UD 605 CHAPTER 19 I C BUS 2 19.16.3 Slave operation The following shows the processing procedure of the slave operation. Basically, the operation of the slave device is event-driven. communication) is necessary. The following description assumes that data communication does not support extension codes. Also, it is assumed that the INTIICn interrupt servicing performs only status change processing and that the actual data communication is performed during the main processing. Figure 19-18. Software Outline During Slave Operation Therefore, processing by an INTIICn interrupt (processing requiring a significant change of the operation status, such as stop condition detection during INTIICn Interrupt servicing Setting, etc. I2C Data Setting, etc. Flag Main processing Therefore, the following three flags are prepared so that the data transfer processing can be performed by transmitting these flags to the main processing instead of the INTIICn signal. (1) Communication mode flag This flag indicates the following communication statuses. Clear mode: Data communication not in progress ACK signal from master not detected, address mismatch) (2) Ready flag This flag indicates that data communication is enabled. This is the same status as an INTIICn interrupt during normal data transfer. This flag is set in the interrupt processing block and cleared in the main processing block. The ready flag for the first data for transmission is not set in the interrupt processing block, so the first data is transmitted without clearance processing (the address match is regarded as a request for the next data). (3) Communication direction flag This flag indicates the direction of communication and is the same as the value of the IICSn.TRCn bit. The following shows the operation of the main processing block during slave operation. Start I2Cn and wait for the communication enabled status. When communication is enabled, perform transfer using the communication mode flag and ready flag (the processing of the stop condition and start condition is performed by interrupts, conditions are confirmed by flags). For transmission, repeat the transmission operation until the master device stops returning ACK signal. When the master device stops returning ACK signal, transfer is complete. Communication mode: Data communication in progress (valid address detection stop condition detection, 606 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 For reception, receive the required number of data and do not return ACK signal for the next data immediately after transfer is complete. After that, the master device generates the stop condition or restart condition. This causes exit from communications. Figure 19-19. Slave Operation Flowchart (1) START IICCLn XXH IICFn = XXH Selection of transfer flag IICFn register setting IICCn XXH IICEn = 1 No Communication mode? Yes Communication direction flag = 1? Yes WRELn = 1 WTIMn = 1 No Communication mode? Data processing Yes No IICn data Ready? Yes No Communication mode? Yes No Ready? Yes Clear ready flag No Transfer completed? Yes ACKEn = 0 WRELn = 1 Data processing Clear ready flag Read data No ACKEn = WTIMn = 1 No ACKDn = 1? Yes WRELn = 1 Clear communication mode flag User's Manual U16889EJ1V0UD 607 CHAPTER 19 I C BUS 2 The following shows an example of the processing of the slave device by an INTIICn interrupt (it is assumed that no extension codes are used here). During an INTIICn interrupt, the status is confirmed and the following steps are executed. <1> When a stop condition is detected, communication is terminated. <2> When a start condition is detected, the address is confirmed. If the address does not match, communication is terminated. If the address matches, the communication mode is set and wait is released, and operation returns from the interrupt (the ready flag is cleared). <3> For data transmission/reception, when the ready flag is set, operation returns from the interrupt while the I2Cn bus remains in the wait status. Remark <1> to <3> in the above correspond to <1> to <3> in Figure 19-20 Slave Operation Flowchart (2). Figure 19-20. Slave Operation Flowchart (2) INTIICn generated Yes SPDn = 1? No <1> Yes STDn = 1? No <3> Set ready flag <2> No COIn = 1? Yes Interrupt servicing completed Communication direction flag TRCn Set communication mode flag Clear ready flag Interrupt servicing completed Termination processing LRELn = 1 Clear communication mode Interrupt servicing completed 608 User's Manual U16889EJ1V0UD CHAPTER 19 I C BUS 2 19.17 Timing of Data Communication When using I2C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the IICSn.TRCn bit that specifies the data transfer direction and then starts serial communication with the slave device. The IICn register's shift operation is synchronized with the falling edge of the serial clock (SCLn pin). The transmit data is transferred to the SO latch and is output (MSB first) via the SDAn pin. Data input via the SDAn pin is captured by the IICn register at the rising edge of the SCLn pin. The data communication timing is shown below. Remark n = 0, 1 User's Manual U16889EJ1V0UD 609 CHAPTER 19 I C BUS 2 Figure 19-21. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ address Processing by master device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn H Transmit L L H H IICn address IICn data Transfer lines SCLn SDAn 1 2 3 4 5 6 7 8 W 9 ACK 1 D7 2 D6 3 D5 4 D4 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Start condition Processing by slave device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn (When EXCn = 1) TRCn L Receive H H L L L Note IICn FFH Note Note To cancel slave wait, write FFH to IICn or set WRELn. Remark n = 0, 1 User's Manual U16889EJ1V0UD 610 CHAPTER 19 I C BUS 2 Figure 19-21. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data Processing by master device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn H Transmit L L H H H L L L IICn data IICn data Transfer lines SCLn SDAn 8 D0 9 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 1 D7 2 D6 3 D5 Processing by slave device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn L Receive L L H H L L L Note Note IICn FFH Note IICn FFH Note Note To cancel slave wait, write FFH to IICn or set WRELn. Remark n = 0, 1 User's Manual U16889EJ1V0UD 611 CHAPTER 19 I C BUS 2 Figure 19-21. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition Processing by master device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn (When SPIEn = 1) TRCn H Transmit L H H IICn data IICn address Transfer lines SCLn SDAn 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 Stop condition IICn FFH Note 9 1 2 AD6 AD5 Start condition Processing by slave device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn H H L L L Note IICn FFH Note Note (When SPIEn = 1) TRCn L Receive Note To cancel slave wait, write FFH to IICn or set WRELn. Remark n = 0, 1 User's Manual U16889EJ1V0UD 612 CHAPTER 19 I C BUS 2 Figure 19-22. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ address Processing by master device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn Transfer lines SCLn SDAn 1 2 3 4 5 6 7 8 R 9 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 L Note H H IICn address IICn FFH Note AD6 AD5 AD4 AD3 AD2 AD1 AD0 Start condition Processing by slave device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn H H L L L L IICn data Note To cancel master wait, write FFH to IICn or set WRELn. Remark n = 0, 1 User's Manual U16889EJ1V0UD 613 CHAPTER 19 I C BUS 2 Figure 19-22. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data Processing by master device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn L Receive L L H H H L L Note Note IICn FFH Note IICn FFH Note Transfer lines SCLn SDAn 8 D0 9 ACK 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 D5 Processing by slave device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn TRCn H Transmit L L H H L L L L IICn data IICn data Note To cancel master wait, write FFH to IICn or set WRELn. Remark n = 0, 1 User's Manual U16889EJ1V0UD 614 CHAPTER 19 I C BUS 2 Figure 19-22. Example of Slave to Master Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition Processing by master device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn (When SPIEn = 1) TRCn Transfer lines SCLn SDAn 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 N- ACK Stop condition Processing by slave device IICn ACKDn STDn SPDn WTIMn ACKEn MSTSn STTn SPTn WRELn INTIICn (When SPIEn = 1) TRCn H H L L L IICn data 1 2 Note H IICn FFH Note IICn address AD6 AD5 Start condition Note To cancel master wait, write FFH to IICn or set WRELn. Remark n = 0, 1 User's Manual U16889EJ1V0UD 615 CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION 20.1 Overview The V850ES/KJ1 is provided with a dedicated interrupt controller (INTC) for interrupt servicing and realize an interrupt function that can service interrupt requests from a total of 46 to 51 sources. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution. The V850ES/KJ1 can process interrupt requests from the on-chip peripheral hardware and external sources. Moreover, exception processing can be started by the TRAP instruction (software exception) or by generation of an exception event (fetching of an illegal op code) (exception trap). 20.1.1 Features Interrupt Source Interrupt function Non-maskable interrupt Maskable interrupt External Internal External Internal WDT1 TMP TM0 TMH TM5 WT BRG UART CSI0 CSIA IIC Note 2 Note 1 V850ES/KJ1 1 channel (NMI pin) 2 channels (WDT1, WDT2) 7 channels (all edge detection interrupts) 1 channel 3 channels 12 channels 2 channels 2 channels 2 channels 1 channel 9 channels 3 channels 2 channels 2 channels 1 channel 1 channel 41 channels 16 channels (TRAP00H to TRAP0FH) 16 channels (TRAP10H to TRAP1FH) KR AD Total Exception function Exception trap Software exception 2 channels (ILGOP/DBG0) Notes 1. Only in the PD70F3218H, 70F3218HY 2. Only in products with an I2C bus (Y products) Table 20-1 lists the interrupt/exception sources. 616 User's Manual U16889EJ1V0UD CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 20-1. Interrupt Source List (1/2) Type Classification Default Priority Name Trigger Interrupt Exception Source Code Handler Address Restored Interrupt PC Control Register Reset Interrupt - RESET RESET pin input Internal reset input from WDT1, WDT2 Nonmaskable Interrupt - - NMI INTWDT1 NMI pin valid edge input WDT1 overflow (when nonmaskable interrupt selected) - INTWDT2 Note 2 Pin WDT1 WDT2 Pin WDT1 0000H 00000000H Undefined - 0010H 0020H 00000010H 00000020H nextPC Note 1 - - WDT2 overflow (when nonmaskable interrupt selected) WDT2 0030H Note 2 00000020H Note 1 - Software exception Exception - - - TRAP0n TRAP1n ILGOP/ DBG0 TRAP instruction TRAP instruction Illegal op code/DBTRAP instruction - - - 004nH 005nH 00000040H 00000050H 00000060H nextPC nextPC nextPC - - - Note 2 Note 2 Exception Exception trap Maskable Interrupt 0060H 0 INTWDTM1 WDT1 overflow (when interval WDT1 timer selected) 0080H 00000080H nextPC WDT1IC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTTM000 INTTM001 INTTM010 INTTM011 INTTM50 INTTM51 INTCSI00 INTCSI01 INTSRE0 INTP0 pin valid edge input INTP1 pin valid edge input INTP2 pin valid edge input INTP3 pin valid edge input INTP4 pin valid edge input INTP5 pin valid edge input INTP6 pin valid edge input TM00 and CR000 match TM00 and CR001 match TM01 and CR010 match TM01 and CR011 match TM50 and CR50 match TM51 and CR51 match CSI00 transfer completion CSI01 transfer completion UART0 reception error occurrence Pin Pin Pin Pin Pin Pin Pin TM00 TM00 TM01 TM01 TM50 TM51 CSI00 CSI01 UART0 0090H 00A0H 00B0H 00C0H 00D0H 00E0H 00F0H 0100H 0110H 0120H 0130H 0140H 0150H 0160H 0170H 0180H 00000090H nextPC PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 TM0IC00 TM0IC01 TM0IC10 TM0IC11 TM5IC0 TM5IC1 CSI0IC0 CSI0IC1 SREIC0 000000A0H nextPC 000000B0H nextPC 000000C0H nextPC 000000D0H nextPC 000000E0H nextPC 000000F0H nextPC 00000100H 00000110H 00000120H 00000130H 00000140H 00000150H 00000160H 00000170H 00000180H nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC 17 18 INTSR0 INTST0 UART0 reception completion UART0 transmission completion UART0 UART0 0190H 01A0H 00000190H 000001AH nextPC nextPC SRIC0 STIC0 19 INTSRE1 UART1 reception error occurrence UART1 01B0H 000001B0H nextPC SREIC1 20 21 INTSR1 INTST1 UART1 reception completion UART1 transmission completion UART1 UART1 01C0H 01D0H 000001C0H nextPC 000001D0H nextPC SRIC1 STIC1 Notes 1. For restoration in the case of INTWDT1 and INTWDT2, refer to 20.10 Cautions. 2. n = 0 to FH User's Manual U16889EJ1V0UD 617 CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 20-1. Interrupt Source List (2/2) Type Classification Default Priority Name Trigger Interrupt Exception Source Code Handler Address Restored Interrupt PC Control Register Maskable Interrupt 22 INTTMH0 TMH0 and CMP00/CMP01 match 23 INTTMH1 TMH1 and CMP10/CMP11 match 24 25 26 27 28 29 30 INTCSIA0 INTIIC0 INTAD INTKR INTWTI INTWT INTBRG Note 1 TMH0 01E0H 000001E0H nextPC TMHIC0 TMH1 01F0H 000001F0H nextPC TMHIC1 CSIA0 transfer completion I C0 transfer completion A/D conversion completion Key return interrupt Watch timer interval Watch timer reference time 8-bit counter of prescaler 3 and PRSCM match 2 CSIA0 I C0 A/D KR WT WT Prescaler 3 2 0200H 0210H 0220H 0230H 0240H 0250H 0260H 00000200H 00000210H 00000220H 00000230H 00000240H 00000250H 00000260H nextPC nextPC nextPC nextPC nextPC nextPC nextPC CSIAIC0 IICIC0 ADIC KRIC WTIIC WTIC BRGIC 31 32 33 34 35 36 37 38 39 40 41 INTTM020 INTTM021 INTTM030 INTTM031 INTCSIA1 INTTM040 INTTM041 INTTM050 INTTM051 INTCSI02 INTSRE2 TM02 and CR020 match TM02 and CR021 match TM03 and CR030 match TM03 and CR031 match CSIA1 transfer completion TM04 and CR040 match TM04 and CR041 match TM05 and CR050 match TM05 and CR051 match CSI02 transfer completion UART2 reception error occurrence TM02 TM02 TM03 TM03 CSIA1 TM04 TM04 TM05 TM05 CSI02 UART2 0270H 0280H 0290H 02A0H 02B0H 02C0H 02D0H 02E0H 02F0H 0300H 0310H 00000270H 00000280H 00000290H nextPC nextPC nextPC TM0IC20 TM0IC21 TM0IC30 TM0IC31 CSIAIC1 TM0IC40 TM0IC41 TM0IC50 TM0IC51 CSI0IC2 SREIC2 000002A0H nextPC 000002B0H nextPC 000002C0H nextPC 000002D0H nextPC 000002E0H nextPC 000002F0H nextPC 00000300H 00000310H nextPC nextPC 42 43 INTSR2 INTST2 UART2 reception completion UART2 transmission completion UART2 UART2 0320H 0330H 00000320H 00000330H nextPC nextPC SRIC2 STIC2 44 45 46 INTIIC1 Note 1 I C1 transfer completion TMP0 overflow TP0CCR0 capture/ TMP0 and TP0CCR0 match 2 I C1 TMP0 TMP0 2 0340H 03A0H 03B0H 00000340H nextPC IICIC1 TP0OVIC TP0CCIC0 INTTP0OV Note 2 000003A0H nextPC 000003B0H nextPC INTTP0CC0 Note 2 47 INTTP0CC1 Note 2 TP0CCR1 capture/ TMP0 and TP0CCR1 match TMP0 03C0H 000003C0H nextPC TP0CCIC1 618 User's Manual U16889EJ1V0UD CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION Notes 1. Only in the PD703216Y, 703217Y, 70F3217Y, 70F3217HY, 70F3218HY 2. Only in the PD70F3218H, 70F3218HY Remarks 1. Default priority: The priority order when two or more maskable interrupt requests with the same priority level are generated at the same time. The highest priority is 0. The priority of non-maskable interrupt request is as follows. INTWDT2 > INTWDT1 > NMI Restored PC: The value of the program counter (PC) saved to EIPC, FEPC, or DBPC when interrupt/exception processing is started. The restored PC when a non-maskable or maskable interrupt is acknowledged while either of the following instructions is being executed does not become nextPC (when an interrupt is acknowledged during the execution of an instruction, the execution of that instruction is stopped and is resumed following completion of interrupt servicing). * Load instructions (SLD.B, SLD.BU, SLD.H, SLD.HU, SLD.W) * Divide instructions (DIV, DIVH, DIVU, DIVHU) * PREPARE, DISPOSE instructions (only when an interrupt occurs before stack pointer update) nextPC: The PC value at which processing is started following interrupt/exception processing. 2. The execution address of the illegal op code when an illegal op code exception occurs is calculated with (Restored PC - 4). User's Manual U16889EJ1V0UD 619 CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION 20.2 Non-Maskable Interrupts Non-maskable interrupt request signals are acknowledged unconditionally, even when interrupts are disabled (DI state). Non-maskable interrupts (NMI) are not subject to priority control and take precedence over all other interrupt request signals. The following three types of non-maskable interrupt request signals are available in the V850ES/KJ1. * NMI pin input (NMI) * Non-maskable interrupt request signal (INTWDT1) due to overflow of watchdog timer 1 * Non-maskable interrupt request signal (INTWDT2) due to overflow of watchdog timer 2 There are four choices for the valid edge of an NMI pin, namely: rising edge, falling edge, both edges, and no edge detection. The non-maskable interrupt request signal (INTWDT1) due to overflow of watchdog timer 1 functions by setting the WDTM1.WDTM14 and WDTM1.WDTM13 bits to 10. The non-maskable interrupt request signal (INTWDT2) due to overflow of watchdog timer 2 functions by setting the WDTM2.WDM21 and WDTM2.WDM20 bits to 01. When two or more non-maskable interrupts occur simultaneously, they are processed in a sequence determined by the following priority order (the interrupt request signals with low priority level are ignored). INTWDT2 > INTWDT1 > NMI If during NMI processing, an NMI, INTWDT1, or INTWDT2 request signal newly occurs, processing is performed as follows. (1) If an NMI request signal newly occurs during NMI processing The new NMI request signal is held pending regardless of the value of the PSW.NP bit. The NMI request signal held pending is acknowledged upon completion of processing of the NMI currently being executed (following RETI instruction execution). (2) If an INTWDT1 request signal newly occurs during NMI processing If the NP bit remains set (to 1) during NMI processing, the new INTWDT1 request signal is held pending. The INTWDT1 request signal held pending is acknowledged upon completion of processing of the NMI currently being executed (following RETI instruction execution). If the NP bit is cleared (to 0) during NMI processing, a newly generated INTWDT1 request signal is executed (NMI processing is interrupted). (3) If an INTWDT2 request signal newly occurs during NMI processing A newly generated INTWDT2 request signal is executed regardless of the value of the NP bit (NMI processing is interrupted). Caution For non-maskable interrupt servicing from non-maskable interrupt request signals (INTWDT1, INTWDT2), refer to 20.10 Cautions. 620 User's Manual U16889EJ1V0UD CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 20-1. Acknowledging Non-Maskable Interrupt Request Signals (1/2) (a) If two or more NMI request signals are simultaneously generated * NMI and INTWDT1 requests simultaneously generated * NMI and INTWDT2 requests simultaneously generated Main routine INTWDT1 processing NMI, INTWDT1 request (simultaneously generated) Main routine INTWDT2 processing NMI, INTWDT2 request (simultaneously generated) System reset System reset * INTWDT1 and INTWDT2 requests simultaneously generated * NMI, INTWDT1, and INTWDT2 requests simultaneously generated Main routine INTWDT2 processing INTWDT1, INTWDT2 request (simultaneously generated) Main routine INTWDT2 processing NMI, INTWDT1, INTWDT2 requests (simultaneously generated) System reset System reset User's Manual U16889EJ1V0UD 621 CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 20-1. Acknowledging Non-Maskable Interrupt Request Signals (2/2) (b) If a new non-maskable interrupt request signal is generated during a non-maskable interrupt servicing Non-maskable interrupt currently being serviced NMI Non-maskable interrupt request newly generated during non-maskable interrupt servicing NMI * Generation of NMI request during NMI processing INTWDT1 INTWDT2 * Generation of INTWDT1 request during NMI processing * Generation of INTWDT2 request during NMI processing (NP = 1 state prior to INTWDT1 request is maintained) Main routine NMI processing NMI request(Hold pending) (Held pending) NMI processing NMI request INTWDT1 request (Hold pending) INTWDT1 processing NMI request INTWDT2 request Main routine NMI processing NMI request Main routine NMI processing INTWDT2 processing System reset System reset * Generation of INTWDT1 request during NMI processing (Set NP = 0 before INTWDT1 request) Main routine NMI processing NP = 0 INTWDT1 processing NMI request INTWDT1 request System reset * Generation of INTWDT1 request during NMI processing (Set NP = 0 after INTWDT1 request) Main routine NMI processing INTWDT1(Hold pending) request NP = 0 INTWDT1 processing NMI request System reset INTWDT1 * Generation of NMI request during INTWDT1 processing * Generation of INTWDT1 request during INTWDT1 processing * Generation of INTWDT2 request during INTWDT1 processing Main routine INTWDT1 processing INTWDT1 request NMI request(Invalid) System reset Main routine INTWDT1 processing INTWDT1 request INTWDT1(Invalid) request System reset INTWDT1 request System reset Main routine INTWDT1 processing INTWDT2 processing INTWDT2 * Generation of NMI request during INTWDT2 processing * Generation of INTWDT1 request during INTWDT2 processing * Generation of INTWDT2 request during INTWDT2 processing Main routine INTWDT2 processing INTWDT2 request NMI request(Invalid) System reset Main routine INTWDT2 processing INTWDT1(Invalid) request System reset Main routine INTWDT2 processing INTWDT2(Invalid) request System reset INTWDT2 request INTWDT2 request 622 User's Manual U16889EJ1V0UD CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION 20.2.1 Operation Upon generation of a non-maskable interrupt request signal, the CPU performs the following processing and transfers control to a handler routine. <1> Saves the restored PC to FEPC. <2> Saves the current PSW to FEPSW. <3> Writes the exception code (0010H, 0020H, 0030H) to the higher halfword (FECC) of ECR. <4> Sets the PSW.NP and PSW.ID bits to 1 and clears the PSW.EP bit to 0. <5> Loads the handler address (00000010H, 00000020H, 00000030H) of the non-maskable interrupt to the PC and transfers control. Figure 20-2 shows the servicing flow for non-maskable interrupts. Figure 20-2. Non-Maskable Interrupt Servicing NMI input INTC acknowledged Non-maskable interrupt request CPU processing PSW. NP 0 1 FEPC FEPSW ECR. FECC PSW. NP PSW. EP PSW. ID PC Restored PC PSW Exception code 1 0 1 Handler address Interrupt request held pending Interrupt servicing User's Manual U16889EJ1V0UD 623 CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION 20.2.2 Restore Execution is restored from non-maskable interrupt servicing by the RETI instruction. (1) In case of NMI Restore from NMI processing is done with the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC. (i) Loads the values of the restored PC and PSW from FEPC and FEPSW, respectively, because the PSW.EP bit and the PSW.NP bit are 0 and 1, respectively. (ii) Transfers control back to the loaded address of the restored PC and PSW. Figure 20-3 shows the processing flow of the RETI instruction. Figure 20-3. RETI Instruction Processing RETI instruction 1 PSW.EP 0 PSW.NP 0 1 PC PSW EIPC EIPSW PC PSW FEPC FEPSW Original processing restored Caution When the EP bit and the NP bit are changed by the LDSR instruction during non-maskable interrupt servicing, in order to restore the PC and PSW correctly during restoring by the RETI instruction, it is necessary to clear the EP bit back to 0 and set the NP bit back to 1 using the LDSR instruction immediately before the RETI instruction. Remark The solid line shows the CPU processing flow. (2) In case of INTWDT1, INTWDT2 signals For non-maskable interrupt servicing by the non-maskable interrupt request signals (INTWDT1, INTWDT2), refer to 20.10 Cautions. 624 User's Manual U16889EJ1V0UD CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION 20.2.3 NP flag The NP flag is a status flag that indicates that non-maskable interrupt servicing is in progress. This flag is set when a non-maskable interrupt request has been acknowledged, and masks all non-maskable requests to prevent multiple interrupts. After reset: 00000020H PSW 0 NP EP ID SAT CY OV S Z NP 0 1 NMI servicing status No non-maskable interrupt servicing Non-maskable interrupt serving in progress User's Manual U16889EJ1V0UD 625 CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION 20.3 Maskable Interrupts Maskable interrupt request signals can be masked by interrupt control registers. The V850ES/KJ1 has 43 to 48 maskable interrupt sources (refer to 20.1.1 Features). If two or more maskable interrupt request signals are generated at the same time, they are acknowledged according to the default priority. In addition to the default priority, eight levels of interrupt priorities can be specified by using the interrupt control registers, allowing programmable priority control. When an interrupt request signal has been acknowledged, the interrupt disabled (DI) status is set and the acknowledgment of other maskable interrupt request signals is disabled. When the EI instruction is executed in an interrupt servicing routine, the interrupt enabled (EI) status is set, which enables acknowledgment of interrupt request signals having a priority higher than that of the interrupt request signal currently in progress. Note that only interrupt request signals with a higher priority have this capability; interrupt request signals with the same priority level cannot be nested. To use multiple interrupts, it is necessary to save EIPC and EIPSW to memory or a register before executing the EI instruction, and restore EIPC and EIPSW to the original values by executing the DI instruction before the RETI instruction. When the WDTM1.WDTM14 bit is cleared to 0, the watchdog timer 1 overflow interrupt functions as a maskable interrupt (INTWDTM1). 20.3.1 Operation If a maskable interrupt request signal is generated, the CPU performs the following processing and transfers control to a handler routine. <1> Saves the restored PC to EIPC. <2> Saves the current PSW to EIPSW. <3> Writes an exception code to the lower halfword of ECR (EICC). <4> Sets the PSW.ID bit to 1 and clears the PSW.EP bit to 0. <5> Loads the corresponding handler address to the PC and transfers control. The maskable interrupt request signal masked by INTC and the maskable interrupt request signal that occurs while another interrupt is being serviced (when PSW.NP bit = 1 or ID bit = 1) are held pending internally. When the interrupts are unmasked, or when the NP bit = 0 and the ID bit = 0 by using the RETI and LDSR instructions, a new maskable interrupt servicing is started in accordance with the priority of the pending maskable interrupt request signal. Figure 20-4 shows the servicing flow for maskable interrupts. 626 User's Manual U16889EJ1V0UD CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 20-4. Maskable Interrupt Servicing INT input Interrupt mask released? Yes INTC acknowledged Priority higher than that of interrupt currently being serviced? Yes Priority higher than that of other interrupt requests? Yes Highest default priority of interrupt requests with the same priority? Yes Maskable interrupt request No No No No Interrupt request pending 1 PSW. NP 0 1 PSW. ID CPU processing EIPC EIPSW ECR. EICC PSW. EP PSW. ID ISPR. correspondingbitNote PC 0 Restored PC PSW Exception code 0 1 1 Handler address Interrupt request pending Interrupt servicing Note For the ISPR register, refer to 20.3.6 In-service priority register (ISPR). User's Manual U16889EJ1V0UD 627 CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION 20.3.2 Restore Execution is restored from maskable interrupt servicing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC. (1) Loads the values of the restored PC and PSW from EIPC and EIPSW because the PSW.EP bit and the PSW.NP bit are both 0. (2) Transfers control to the loaded address of the restored PC and PSW. Figure 20-5 shows the processing flow of the RETI instruction. Figure 20-5. RETI Instruction Processing RETI instruction 1 PSW. EP 0 1 PSW. NP 0 PC PSW ISPR. corresponding -bitNote EIPC EIPSW PC PSW FEPC FEPSW 0 Original processing restored Note For the ISPR register, refer to 20.3.6 In-service priority register (ISPR). Caution When the EP bit and the NP bit are changed by the LDSR instruction during maskable interrupt servicing, in order to restore the PC and PSW correctly during restoring by the RETI instruction, it is necessary to clear the EP bit back to 0 and the NP bit back to 0 using the LDSR instruction immediately before the RETI instruction. Remark The solid line shows the CPU processing flow. 628 User's Manual U16889EJ1V0UD CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION 20.3.3 Priorities of maskable interrupts INTC provides a multiple interrupt servicing in which an interrupt can be acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels specified by the interrupt priority level specification bit (xxICn.xxPRn bit). When two or more interrupts having the same priority level specified by xxPRn are generated at the same time, interrupts are serviced in order depending on the priority level allocated to each interrupt request (default priority level) beforehand. For more information, refer to Table 20-1 Interrupt Source List. Programmable priority control divides interrupt requests into eight levels by setting the priority level specification flag. Note that when an interrupt request signal is acknowledged, the PSW.ID flag is automatically set (1). Therefore, when multiple interrupts are to be used, clear (0) the ID flag beforehand (for example, by placing the EI instruction into the interrupt service program) to enable interrupts. Remark xx: Identifying name of each peripheral unit (refer to Table 20-2 (xxICn)) n: Peripheral unit number (refer to Table 20-2 Interrupt Control Registers (xxICn)) Interrupt Control Registers User's Manual U16889EJ1V0UD 629 CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 20-6. Example of Interrupt Nesting (1/2) Main routine Servicing of a EI Interrupt request a (level 3) EI Interrupt request b (level 2) Interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. Servicing of b Servicing of c Interrupt request c (level 3) Interrupt request d (level 2) Although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. Servicing of d Servicing of e EI Interrupt request e (level 2) Interrupt request f (level 3) Interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. Servicing of f Servicing of g EI Interrupt request g (level 1) Interrupt request h (level 1) Servicing of h Interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. Caution The values of EIPC and EIPSW must be saved before executing multiple interrupts. Remarks 1. a to u in the figure are the names of interrupt request signals shown for the sake of explanation. 2. The default priority in the figure indicates the relative priority between two interrupt request signals. 630 User's Manual U16889EJ1V0UD CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 20-6. Example of Interrupt Nesting (2/2) Main routine Servicing of i EI Interrupt request i (level 2) Interrupt request j (level 3) Interrupt request k (level 1) EI Servicing of k Interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. Servicing of j Servicing of l Interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. Interrupt request l (level 2) Interrupt request m (level 3) Interrupt request n (level 1) Servicing of n Pending interrupt requests are acknowledged after servicing of interrupt request l. At this time, interrupt requests n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. Servicing of m Interrupt request o (level 3) Servicing of o Servicing of p EI Servicing of q EI Servicing of r EI Interrupt request p Interrupt request q EI (level 2) Interrupt request r (level 1) (level 0) If levels 3 to 0 are acknowledged Servicing of s Pending interrupt requests t and u are acknowledged after processing of s. Because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. Servicing of u Interrupt request s (level 1) Interrupt request t (level 2)Note 1 Interrupt request u (level 2)Note 2 Servicing of t Notes 1. Lower default priority 2. Higher default priority User's Manual U16889EJ1V0UD 631 CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 20-7. Example of Servicing Simultaneously Generated Interrupt Request Signals Main routine EI Interrupt request a (level 2) Interrupt request b (level 1)Note 1 Interrupt request c (level 1)Note 2 Servicing of interrupt request b *Interrupt requests b and c are acknowledged first according to their priorities. *Because the priorities of b and c are the same, b is acknowledged first because it has the higher default priority. Servicing of interrupt request c Servicing of interrupt request a Notes 1. Higher default priority 2. Lower default priority 632 User's Manual U16889EJ1V0UD CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION 20.3.4 Interrupt control register (xxlCn) An interrupt control register is assigned to each maskable interrupt and sets the control conditions for each maskable interrupt request. The interrupt control registers can be read or written in 8-bit or 1-bit units. After reset, xxICn is set to 47H. Caution Be sure to read the xxICn.xxIFn bit while interrupts are disabled (DI). If the xxIFn bit is read while interrupts are enabled (EI), an incorrect value may be read if there is a conflict between acknowledgment of the interrupt and reading of the bit. After reset: 47H <> xxICn xxIFn R/W <> xxMKn Address: FFFFF110H to FFFFF168H 0 0 0 xxPRn2 xxPRn1 xxPRn0 xxIFn 0 1 Interrupt request flagNote Interrupt request not generated Interrupt request generated xxMKn 0 1 Enables interrupt servicing Interrupt mask flag Disables interrupt servicing (pending) xxPRn2 0 0 0 0 1 1 1 1 xxPRn1 0 0 1 1 0 0 1 1 xxPRn0 0 1 0 1 0 1 0 1 Interrupt priority specification bit Specifies level 0 (highest) Specifies level 1 Specifies level 2 Specifies level 3 Specifies level 4 Specifies level 5 Specifies level 6 Specifies level 7 (lowest) Note Automatically reset by hardware when interrupt request is acknowledged. Remark xx: Identifying name of each peripheral unit (refer to Table 20-2 (xxICn)) n: Peripheral unit number (refer to Table 20-2 Interrupt Control Registers (xxICn).) Interrupt Control Registers Following tables list the addresses and bits of the interrupt control registers. User's Manual U16889EJ1V0UD 633 CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 20-2. Interrupt Control Registers (xxlCn) (1/2) Address Register <7> FFFFF110H FFFFF112H FFFFF114H FFFFF116H FFFFF118H FFFFF11AH FFFFF11CH FFFFF11EH FFFFF120H FFFFF122H FFFFF124H FFFFF126H FFFFF128H FFFFF12AH FFFFF12CH FFFFF12EH FFFFF130H FFFFF132H FFFFF134H FFFFF136H FFFFF138H FFFFF13AH FFFFF13CH FFFFF13EH FFFFF140H FFFFF142H FFFFF144H FFFFF146H FFFFF148H FFFFF14AH FFFFF14CH FFFFF14EH FFFFF150H FFFFF152H FFFFF154H FFFFF156H FFFFF158H FFFFF15AH FFFFF15CH FFFFF15EH FFFFF160H WDT1IC PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 TM0IC00 TM0IC01 TM0IC10 TM0IC11 TM5IC0 TM5IC1 CSI0IC0 CSI0IC1 SREIC0 SRIC0 STIC0 SREIC1 SRIC1 STIC1 TMHIC0 TMHIC1 CSIAIC0 IICIC0 ADIC KRIC WTIIC WTIC BRGIC TM0IC20 TM0IC21 TM0IC30 TM0IC31 CSIAIC1 TM0IC40 TM0IC41 TM0IC50 TM0IC51 CSI0IC2 Note Bits <6> WDT1MK PMK0 PMK1 PMK2 PMK3 PMK4 PMK5 PMK6 TM0MK00 TM0MK01 TM0MK10 TM0MK11 TM5MK0 TM5MK1 CSI0MK0 CSI0MK1 SREMK0 SRMK0 STMK0 SREMK1 SRMK1 STMK1 TMHMK0 TMHMK1 CSIAMK0 IICMK0 ADMK KRMK WTIMK WTMK BRGMK TM0MK20 TM0MK21 TM0MK30 TM0MK31 CSIAMK1 TM0MK40 TM0MK41 TM0MK50 TM0MK51 CSI0MK2 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 WDT1IF PIF0 PIF1 PIF2 PIF3 PIF4 PIF5 PIF6 TM0IF00 TM0IF01 TM0IF10 TM0IF11 TM5IF0 TM5IF1 CSI0IF0 CSI0IF1 SREIF0 SRIF0 STIF0 SREIF1 SRIF1 STIF1 TMHIF0 TMHIF1 CSIAIF0 IICIF0 ADIF KRIF WTIIF WTIF BRGIF TM0IF20 TM0IF21 TM0IF30 TM0IF31 CSIAIF1 TM0IF40 TM0IF41 TM0IF50 TM0IF51 CSI0IF2 WDT1PR2 WDT1PR1 WDT1PR0 PPR02 PPR12 PPR22 PPR32 PPR42 PPR52 PPR62 PPR01 PPR11 PPR21 PPR31 PPR41 PPR51 PPR61 PPR00 PPR10 PPR20 PPR30 PPR40 PPR50 PPR60 TM0PR002 TM0PR001 TM0PR000 TM0PR012 TM0PR011 TM0PR010 TM0PR102 TM0PR101 TM0PR100 TM0PR112 TM0PR111 TM0PR110 TM5PR02 TM5PR12 TM5PR01 TM5PR11 TM5PR00 TM5PR10 CSI0PR02 CSI0PR01 CSI0PR00 CSI0PR12 CSI0PR11 CSI0PR10 SREPR02 SRPR02 STPR02 SREPR12 SRPR12 STPR12 TMHPR02 TMHPR12 SREPR01 SRPR01 STPR01 SREPR11 SRPR11 STPR11 TMHPR01 TMHPR11 SREPR00 SRPR00 STPR00 SREPR10 SRPR10 STPR10 TMHPR00 TMHPR10 CSIAPR02 CSIAPR01 CSIAPR00 IICPR02 ADPR2 KRPR2 WTIPR2 WTPR2 BRGPR2 IICPR01 ADPR1 KRPR1 WTIPR1 WTPR1 BRGPR1 IICPR00 ADPR0 KRPR0 WTIPR0 WTPR0 BRGPR0 TM0PR202 TM0PR201 TM0PR200 TM0PR212 TM0PR211 TM0PR210 TM0PR302 TM0PR301 TM0PR300 TM0PR312 TM0PR311 TM0PR310 CSIAPR12 CSIAPR11 CSIAPR10 TM0PR402 TM0PR401 TM0PR400 TM0PR412 TM0PR411 TM0PR410 TM0PR502 TM0PR501 TM0PR500 TM0PR512 TM0PR511 TM0PR510 CSI0PR22 CSI0PR21 CSI0PR20 Note Only in the PD703216Y, 703217Y, 70F3217Y, 70F3217HY, 70F3218HY 634 User's Manual U16889EJ1V0UD CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 20-2. Interrupt Control Registers (xxlCn) (2/2) Address Register <7> FFFFF162H FFFFF164H FFFFF166H FFFFF168H FFFFF174H FFFFF176H FFFFF178H SREIC2 SRIC2 STIC2 IICIC1 Note 1 Bits <6> SREMK2 SRMK2 STMK2 IICMK1 TP0OVMK 5 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 2 SREPR22 SRPR22 STPR22 IICPR12 1 SREPR21 SRPR21 STPR21 IICPR11 0 SREPR20 SRPR20 STPR20 IICPR10 SREIF2 SRIF2 STIF2 IICIF1 TP0OVIF TP0OVIC Note 2 TP0OVPR2 TP0OVPR1 TP0OVPR0 TP0CCPR02 TP0CCPR12 TP0CCPR01 TP0CCPR11 TP0CCPR00 TP0CCPR10 TP0CCIC0 TP0CCIC1 Note 2 TP0CCIF0 TP0CCMK0 TO0CCIF1 TP0CCMK1 Note 2 Notes 1. Only in the PD703216Y, 703217Y, 70F3217Y, 70F3217HY, 70F3218HY 2. Only in the PD70F3218H, 70F3218HY User's Manual U16889EJ1V0UD 635 CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION 20.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3) These registers set the interrupt mask status for maskable interrupts. The xxMKn bit of the IMR0 to IMR3 registers and the xxMKn bit of the xxlCn register are respectively linked. The IMRm register can be read or written in 16-bit units (m = 0 to 3). When the higher 8 bits of the IMRk register are treated as the IMRkH register and the lower 8 bits of the IMRk register as the IMRkL register, they can be read or written in 8-bit or 1-bit units (k = 0 to 2). Caution In the device file, the xxMKn bit of the xxICn register is defined as a reserved word. Therefore, if bit manipulation is performed using the name xxMKn, the xxICn register, not the IMRm register, is rewritten (as a result, the IMRm register is also rewritten). 636 User's Manual U16889EJ1V0UD CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION After reset: FFFFH 15 R/W 14 Address: IMR0 FFFFF100H, IMR0L FFFFF100H, IMR0H FFFFF101H 13 12 11 10 9 8 IMR0 (IMR0H Note 1 ) CSI0MK1 CSI0MK0 TM5MK1 TM5MK0 TM0MK11 TM0MK10 TM0MK01 TM0MK00 7 6 5 4 3 2 1 0 (IMR0L) PMK6 PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 WDT1MK After reset: FFFFH 15 R/W 14 Address: IMR1 FFFFF102H, IMR1L FFFFF102H, IMR1H FFFFF103H 13 12 11 10 9 8 IMR1 (IMR1H Note 1 ) TM0MK20 BRGMK 7 6 WTMK 5 WTIMK 4 KRMK 3 ADMK 2 IICMK0 CSIAMK0 1 0 (IMR1L) TMHMK1 TMHMK0 STMK1 SRMK1 SREMK1 STMK0 SRMK0 SREMK0 After reset: FFFFH 15 R/W 14 Address: IMR2 FFFFF104H, IMR2L FFFFF104H, IMR2H FFFFF105H 13 12 11 10 9 8 IMR2 (IMR2H Note 1 ) 1 7 1 6 1 5 IICMK1 4 STMK2 3 SRMK2 2 SREMK2 CSI0MK2 1 0 (IMR2L) TM0MK51 TM0MK50 TM0MK41 TM0MK40 CSIAMK1 TM0MK31 TM0MK30 TM0MK21 After reset: FFFFH 15 R/W 14 Address: IMR3, IMR3L FFFFF106H 13 12 11 10 9 8 IMR3Note 2 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 (IMR3L) 1 1 1 TP0CCMK1 TP0CCMK0 TP0OVMK 1 1 xxMKn 0 1 Interrupt mask flag setting Enables interrupt servicing Disables interrupt servicing Notes 1. When reading from or writing to bits 8 to 15 of the IMR0 to IMR2 registers in 8-bit or 1-bit units, specify these bits as bits 0 to 7 of the IMR0H to IMR2H registers. 2. Only in the PD70F3218H, 70F3218HY Caution Set bits 15 to 13 of the IMR2 register and bits 15 to 5, 1, and 0 of the IMR3 register to 1. The operation is not guaranteed if their value is changed. Remark xx: Identifying name of each peripheral unit (refer to Table 20-2 Interrupt Control Registers (xxICn)) n: Peripheral unit number (refer to Table 20-2 Interrupt Control Registers (xxICn)) User's Manual U16889EJ1V0UD 637 CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION 20.3.6 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently being acknowledged. When the interrupt request signal is acknowledged, the bit of this register corresponding to the priority level of that interrupt request signal is set (1) and remains set while the interrupt is being serviced. When the RETI instruction is executed, the bit among those that are set (1) in the ISPR register that corresponds to the interrupt request signal having the highest priority is automatically cleared (0) by hardware. However, it is not cleared (0) when execution is returned from non-maskable interrupt servicing or exception processing. This register is read-only in 8-bit or 1-bit units. After reset, ISPR is cleared to 00H. Caution If an interrupt is acknowledged while the ISPR register is being read in the interrupt enabled (EI) status, the value of the ISPR register after the bits of the register have been set to 1 by acknowledging the interrupt may be read. To accurately read the value of the ISPR register before an interrupt is acknowledged, read the register while interrupts are disabled (DI status). After reset: 00H <> R Address: FFFFF1FAH <> <> <> <> <> <> <> ISPR ISPR7 ISPR6 ISPR5 ISPR4 ISPR3 ISPR2 ISPR1 ISPR0 ISPRn 0 1 Priority of interrupt currently being acknowledged Interrupt request with priority n is not acknowledged Interrupt request with priority n is being acknowledged Remark n = 0 to 7 (priority level) 638 User's Manual U16889EJ1V0UD CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION 20.3.7 ID flag The interrupt disable flag (ID) is allocated to the PSW and controls the maskable interrupt's operating state, and stores control information regarding enabling/disabling reception of interrupt request signals. After reset, this flag is set to 00000020H. After reset: 00000020H PSW 0 NP EP ID SAT CY OV S Z ID 0 1 Maskable interrupt servicing specificationNote Maskable interrupt request signal acknowledgment enabled Maskable interrupt request signal acknowledgment disabled Note Interrupt disable flag (ID) function ID is set (1) by the DI instruction and cleared (0) by the EI instruction. Its value is also modified by the RETI instruction or LDSR instruction when referencing the PSW. Non-maskable interrupt request signals and exceptions are acknowledged regardless of this flag. When a maskable interrupt request signal is acknowledged, the ID flag is automatically set (1) by hardware. An interrupt request signal generated during the acknowledgment disabled period (ID flag = 1) can be acknowledged when the xxICn.xxIFn bit is set (1), and the ID flag is cleared (0). User's Manual U16889EJ1V0UD 639 CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION 20.3.8 Watchdog timer mode register 1 (WDTM1) This register is a special register that can be written to only in a special sequence. To generate a maskable interrupt (INTWDT1), clear the WDTM14 bit to 0. This register can be read or written in 8-bit or 1-bit units (for details, refer to CHAPTER 12 WATCHDOG TIMER FUNCTIONS). After reset: 00H <> WDTM1 RUN1 R/W Address: FFFFF6C2H 0 0 WDTM14 WDTM13 0 0 0 RUN1 0 1 Watchdog timer operation mode selectionNote 1 Stop count operation Clear counter and start count operation WDTM14 WDTM13 0 0 1 1 0 1 0 1 Watchdog timer operation mode selectionNote 2 Interval timer mode (Generate maskable interrupt INTWDTM1 when overflow occurs) Watchdog timer mode 1Note 3 (Generate non-maskable interrupt INTWDT1 when overflow occurs) Watchdog timer mode 2 (Start WDTRES2 reset operation when overflow occurs) Notes 1. Once the RUN1 bit has been set (1), it cannot be cleared (0) by software. Therefore, once counting starts, it cannot be stopped except reset. 2. Once the WDTM14 and WDTM13 bits have been set (1), they cannot be cleared (0) by software. Reset is the only way to clear these bits. 3. For non-maskable interrupt servicing due to a non-maskable interrupt request signal (INTWDT1), refer to 20.10 Cautions. 640 User's Manual U16889EJ1V0UD CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION 20.4 External Interrupt Request Input Pins (NMI, INTP0 to INTP6) 20.4.1 Noise elimination (1) Noise elimination for NMI pin The NMI pin includes a noise eliminator that operates using analog delay. Therefore, a signal input to the NMI pin is not detected as an edge unless it maintains its input level for a certain period. The edge is detected only after a certain period has elapsed. The NMI pin is used for releasing the STOP mode. In the STOP mode, noise elimination using the system clock is not performed because the internal system clock is stopped. (2) Noise elimination for INTP0 to INTP6 pins The INTP0 to INTP6 pins include a noise eliminator that operates using analog delay. Therefore, a signal input to each pin is not detected as an edge unless it maintains its input level for a certain period. The edge is detected only after a certain period has elapsed. 20.4.2 Edge detection The valid edges of the NMI and INTP0 to INTP6 pins can be selected from the following four types for each pin. * Falling edge * Rising edge * Both edges * No edge detection After reset, the edge detection for the NMI pin is set to "no edge detection". Therefore, interrupt requests cannot be acknowledged (the NMI pin functions as a normal port) unless a valid edge is specified by the INTR0, INTF0, INTR9H, and INTF9H registers. When using the P02/NMI pin as an output port, set the NMI pin valid edge to "no edge detection". User's Manual U16889EJ1V0UD 641 CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1) External interrupt rising and falling edge specification registers 0 (INTR0, INTF0) These are 8-bit registers that specify detection of the rising and falling edges of the NMI and INTP0 to INTP3 pins. These registers can be read or written in 8-bit or 1-bit units. After reset, these registers are cleared to 00H. Caution When switching to the port function from the external interrupt function (alternate function), edge detection may be performed. Therefore, set the port mode after setting the INTF0n and INTR0n bits = 00. After reset: 00H R/W Address: INTR0 FFFFFC20H, INTF0 FFFFFC00H INTR0 0 INTR06 INTP3 INTR05 INTP2 INTR04 INTP1 INTR03 INTP0 INTR02 NMI 0 0 INTF0 0 INTF06 INTP3 INTF05 INTP2 INTF04 INTP1 INTF03 INTP0 INTF02 NMI 0 0 Remark For specification of the valid edge, refer to Table 20-3. Table 20-3. NMI and INTP0 to INTP3 Pins Valid Edge Specification INTF0n 0 0 1 1 INTR0n 0 1 0 1 Valid edge specification (n = 2 to 6) No edge detection Rising edge Falling edge Both edges Remark n = 2: Control of NMI pin n = 3 to 6: Control of INTP0 to INTP3 pins 642 User's Manual U16889EJ1V0UD CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) External interrupt rising and falling edge specification registers 9H (INTR9H, INTF9H) These are 8-bit registers that specify detection of the rising edge of the INTP4 to INTP6 pins. These registers can be read or written in 8-bit or 1-bit units. After reset, these registers are cleared to 00H. Caution When switching to the port function from the external interrupt function (alternate function), edge detection may be performed. Therefore, set the port mode after setting the INTF9n and INTR9n bits = 00. After reset: 00H R/W Address: INTR9H FFFFFC33H, INTF9H FFFFFC13H INTR9H INTR915 INTR914 INTR913 INTP6 INTP5 INTP4 0 0 0 0 0 INTF9H INTF915 INTF914 INTF913 INTP6 INTP5 INTP4 0 0 0 0 0 Remark For specification of the valid edge, refer to Table 20-4. Table 20-4. INTP4 to INTP6 Pins Valid Edge Specification INTF9n 0 0 1 1 INTR9n 0 1 0 1 Valid edge specification (n = 13 to 15) No edge detection Rising edge Falling edge Both edges Remark n = 13 to 15: Control of INTP4 to INTP6 pins User's Manual U16889EJ1V0UD 643 CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION 20.5 Software Exceptions A software exception is generated when the CPU executes the TRAP instruction. Software exceptions can always be acknowledged. 20.5.1 Operation If a software exception occurs, the CPU performs the following processing and transfers control to a handler routine. <1> Saves the restored PC to EIPC. <2> Saves the current PSW to EIPSW. <3> Writes an exception code to the lower 16 bits (EICC) of ECR (interrupt source). <4> Sets the PSW.EP and PSW.ID bits to 1. <5> Loads the handler address (00000040H or 00000050H) for the software exception routine to the PC and transfers control. Figure 20-8 shows the software exception processing flow. Figure 20-8. Software Exception Processing TRAP instructionNote CPU processing EIPC EIPSW ECR.EICC PSW.EP PSW.ID PC Restored PC PSW Exception code 1 1 Handler address Exception processing Note TRAP instruction format: TRAP vector (However, vector = 00H to 1FH) The handler address is determined by the operand (vector) of the TRAP instruction. If the vector is 00H to 1FH, the handler address is 00000040H, and if the vector is 10H to 1FH, the handler address is 00000050H. 644 User's Manual U16889EJ1V0UD CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION 20.5.2 Restore Execution is restored from software exception processing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC. <1> Loads the restored PC and PSW from EIPC and EIPSW because the PSW.EP bit is 1. <2> Transfers control to the address of the restored PC and PSW. Figure 20-9 shows the processing flow of the RETI instruction. Figure 20-9. RETI Instruction Processing RETI instruction 1 PSW.EP 0 PSW.NP 0 1 PC PSW EIPC EIPSW PC PSW FEPC FEPSW Original processing restored Caution When the EP bit and the NP bit are changed by the LDSR instruction during software exception processing, in order to restore the PC and PSW correctly during restoring by the RETI instruction, it is necessary to set the PSW.EP bit back to 1 using the LDSR instruction immediately before the RETI instruction. Remark The solid line shows the CPU processing flow. User's Manual U16889EJ1V0UD 645 CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION 20.5.3 EP flag The EP flag, which is bit 6 of the PSW, is a status flag that indicates that exception processing is in progress. It is set when an exception occurs. After reset: 00000020H PSW 0 NP EP ID SAT CY OV S Z EP 0 1 Exception processing status Exception processing not in progress Exception processing in progress 646 User's Manual U16889EJ1V0UD CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION 20.6 Exception Trap The exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the V850ES/KJ1, an illegal op code trap (ILGOP: illegal OP code trap) is considered as an exception trap. 20.6.1 Illegal op code An illegal op code is defined as an instruction with instruction op code (bits 10 to 5) = 111111B, sub-op code (bits 26 to 23) = 0111B to 1111B, and sub-op code (bit 16) = 0B. When such an instruction is executed, an exception trap is generated. 15 11 10 54 0 31 27 26 23 22 16 0111 XXXXX111111XXXXXXXXXX 1111 XXXXXX0 X: don't care Caution It is recommended not to use illegal op code because instructions may newly be assigned in the future. (1) Operation Upon generation of an exception trap, the CPU performs the following processing and transfers control to a handler routine. <1> Saves the restored PC to DBPC. <2> Saves the current PSW to DBPSW. <3> Sets the PSW.NP, PSW.EP, and PSW.ID bits. <4> Loads the handler address (00000060H) for the exception trap routine to the PC and transfers control. Figure 20-10 shows the exception trap processing flow. User's Manual U16889EJ1V0UD 647 CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 20-10. Exception Trap Processing Exception trap (ILGOP) occurs CPU processing DBPC DBPSW PSW.NP PSW.EP PSW.ID PC Restored PC PSW 1 1 1 00000060H Exception processing (2) Restore Execution is restored from exception trap processing by the DBRET instruction. When the DBRET instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC. <1> Loads the restored PC and PSW from DBPC and DBPSW. <2> Transfers control to the loaded address of the restored PC and PSW. Figure 20-11 shows the processing flow for restore from exception trap processing. Figure 20-11. Processing Flow for Restore from Exception Trap DBRET instruction PC PSW DBPC DBPSW Jump to restored PC address 648 User's Manual U16889EJ1V0UD CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION 20.6.2 Debug trap A debug trap is an exception that occurs upon execution of the DBTRAP instruction and that can be acknowledged at all times. When a debug trap occurs, the CPU performs the following processing. (1) Operation <1> Saves the restored PC to DBPC. <2> Saves the current PSW to DBPSW. <3> Sets the PSW.NP, PSW.EP, and PSW.ID bits to 1. <4> Sets the handler address (00000060H) for the debug trap routine to the PC and transfers control. Figure 20-12 shows the debug trap processing flow. Figure 20-12. Debug Trap Processing DBTRAP instruction CPU processing DBPC DBPSW PSW.NP PSW.EP PSW.ID PC Restored PC PSW 1 1 1 00000060H Debug monitor routine processing User's Manual U16889EJ1V0UD 649 CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Restore Execution is restored from debug trap processing by the DBRET instruction. When the DBRET instruction is executed, the CPU performs the following processing and transfers control to the address of the restored PC. <1> Loads the restored PC and PSW from DBPC and DBPSW. <2> Transfers control to the loaded address of the restored PC and PSW. Figure 20-13 shows the processing flow for restore from debug trap processing. Figure 20-13. Processing Flow for Restore from Debug Trap DBRET instruction PC PSW DBPC DBPSW Jump to restored PC address 650 User's Manual U16889EJ1V0UD CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION 20.7 Multiple Interrupt Servicing Control Multiple interrupt servicing control is a function that stops an interrupt service routine currently in progress if a higher priority interrupt request signal is generated, and processes the acknowledgment operation of the higher priority interrupt request signal. If an interrupt request signal with a lower or equal priority is generated and a service routine is currently in progress, the later interrupt request signal will be held pending. Multiple interrupt servicing control is performed when interrupts are enabled (PSW.ID bit = 0). Even in an interrupt servicing routine, multiple interrupt control must be performed while interrupts are enabled (ID bit = 0). If a maskable interrupt or software exception is generated in a maskable interrupt or software exception service program, EIPC and EIPSW must be saved. The following example illustrates the procedure. (1) To acknowledge maskable interrupt request signals in service program Service program for maskable interrupt or exception ... ... * EIPC saved to memory or register * EIPSW saved to memory or register * EI instruction (enables interrupt acknowledgment) ... ... ... ... * DI instruction (disables interrupt acknowledgment) * Saved value restored to EIPSW * Saved value restored to EIPC * RETI instruction Acknowledges maskable interrupt User's Manual U16889EJ1V0UD 651 CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) To generate exception in service program Service program for maskable interrupt or exception ... ... * EIPC saved to memory or register * EIPSW saved to memory or register ... * TRAP instruction ... * Saved value restored to EIPSW * Saved value restored to EIPC * RETI instruction Priorities 0 to 7 (0 is the highest) can be set for each maskable interrupt request in multiple interrupt servicing control by software. To set a priority level, write values to the xxICn.xxPRn0 to xxICn.xxPRn2 bits After reset, interrupt requests are masked by the corresponding to each maskable interrupt request. Acknowledges exceptions such as TRAP instruction. xxICn.xxMKn bit, and the priority is set to level 7 by the xxPRn0 to xxPRn2 bits. Priorities of maskable interrupts are as follows. (High) Level 0 > Level 1 > Level 2 > Level 3 > Level 4 > Level 5 > Level 6 > Level 7 (Low) Interrupt servicing that has been suspended as a result of multiple interrupt servicing control is resumed after the interrupt servicing of the higher priority has been completed and the RETI instruction has been executed. A pending interrupt request signal is acknowledged after the current interrupt servicing has been completed and the RETI instruction has been executed. Caution In a non-maskable interrupt servicing routine (in the time until the RETI instruction is executed), maskable interrupts are not acknowledged and held pending. 652 User's Manual U16889EJ1V0UD CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION 20.8 Interrupt Response Time Except in the following cases, the CPU interrupt response time is a minimum of 4 clocks. If inputting consecutive interrupt request signals, at least 4 clocks must be placed between each interrupt request signal. * IDLE/STOP mode * External bus access * Consecutive interrupt request non-sample instruction (refer to 20.9 Acknowledged by CPU) * Access to interrupt control register * Access to peripheral I/O register Figure 20-14. Pipeline Operation During Interrupt Request Signal Acknowledgment (Outline) Periods in Which Interrupts Are Not (1) Minimum interrupt response time 4 system clocks Internal clock Interrupt request Instruction 1 Instruction 2 Interrupt acknowledgment operation Instruction (first instruction of interrupt servicing routine) IF ID EX MEM WB IFX IDX INT1 INT2 INT3 INT4 IF ID EX (2) Maximum interrupt response time 6 system clocks Internal clock Interrupt request Instruction 1 Instruction 2 Interrupt acknowledgment operation Instruction (first instruction of interrupt servicing routine) IF ID EX MEM MEM MEM WB IFX IDX INT1 INT2 INT3 INT3 INT3 INT4 IF ID EX Remark INT1 to INT4: Interrupt acknowledgment processing IFX: Invalid instruction fetch IDX: Invalid instruction decode Interrupt response time (internal system clock) Internal interrupt Min. Max. 4 6 External interrupt 4 + analog delay 6 + analog delay Condition The following cases are excluded. * IDLE/STOP mode * External bus access * Consecutive interrupt request non-sample instruction * Access to interrupt control register * Access to peripheral I/O register User's Manual U16889EJ1V0UD 653 CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION 20.9 Periods in Which Interrupts Are Not Acknowledged by CPU Interrupts are acknowledged by the CPU while an instruction is being executed. acknowledged between an interrupt request non-sample instruction and the next instruction. The following instructions are interrupt request non-sample instructions. * EI instruction * DI instruction * LDSR reg2, 0x5 instructions (vs. PSW) * Store instruction for the PRCMD register * Store instruction and bit manipulation instruction for the following registers * Interrupt-related registers: Interrupt control register (xxlCn), interrupt mask registers 0 to 3 (IMR0 to IMR3) However, no interrupt is 20.10 Cautions Design the system so that restoring by the RETI instruction is as follows after a non-maskable interrupt triggered by a non-maskable interrupt request signal (INTWDT1/INTWDT2) is serviced. Figure 20-15. Restoring by RETI Instruction Generation of INTWDT1/INTWDT2 FEPC software reset processing address FEPSW value so that NP bit =1, EP bit = 1 RETI INTWDT1/INTWDT2 servicing routine Ten RETI instructions (FEPC and FEPSW must be set) PSW initial set value of PSW Initialization processing Software reset processing routine 654 User's Manual U16889EJ1V0UD CHAPTER 21 KEY INTERRUPT FUNCTION 21.1 Function A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input pins (KR0 to KR7) by setting the KRM register. Caution If any of the KR0 to KR7 pins is at low level, the INTKR signal is not generated even if a falling edge is input to another pin. Table 21-1. Assignment of Key Return Detection Pins Flag KRM0 KRM1 KRM2 KRM3 KRM4 KRM5 KRM6 KRM7 Pin Description Controls KR0 signal in 1-bit units Controls KR1 signal in 1-bit units Controls KR2 signal in 1-bit units Controls KR3 signal in 1-bit units Controls KR4 signal in 1-bit units Controls KR5 signal in 1-bit units Controls KR6 signal in 1-bit units Controls KR7 signal in 1-bit units Figure 21-1. Key Return Block Diagram KR7 KR6 KR5 KR4 INTKR KR3 KR2 KR1 KR0 KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 Key return mode register (KRM) User's Manual U16889EJ1V0UD 655 CHAPTER 21 KEY INTERRUPT FUNCTION 21.2 Register (1) Key return mode register (KRM) The KRM register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals. This register can be read or written in 8-bit or 1-bit units. After reset, KRM is cleared to 00H. After reset: 00H R/W Address: FFFFF300H KRM KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 KRMn 0 1 Key return mode control Does not detect key return signal Detects key return signal Caution If the KRM register is changed, an interrupt request signal (INTKR) may be generated. To prevent this, change the KRM register after disabling interrupts (DI), and then enable interrupts (EI) after clearing the interrupt request flag (KRIC.KRIF bit) to 0. Remark For the alternate-function pin settings, refer to Table 4-19 Settings When Port Pins Are Used for Alternate Functions. 656 User's Manual U16889EJ1V0UD CHAPTER 22 STANDBY FUNCTION 22.1 Overview The power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application. The available standby modes are listed in Table 22-1. Table 22-1. Standby Modes Mode HALT mode IDLE mode STOP mode Subclock operation mode Sub-IDLE mode Functional Outline Mode to stop only the operating clock of the CPU Mode to stop all the operations of the internal circuits except the oscillator Note 1 Mode to stop all the operations of the internal circuits except the subclock oscillator Mode to use the subclock as the internal system clock Note 2 Mode to stop all the operations of the internal circuits, except the oscillator, in the subclock operation mode Notes 1. The PLL does not stop. To realize low power consumption, stop the PLL and then shift to the IDLE mode. 2. Change to the clock-through mode, stop the PLL, then shift to the STOP mode. For details, refer to CHAPTER 6 CLOCK GENERATION FUNCTION. User's Manual U16889EJ1V0UD 657 CHAPTER 22 STANDBY FUNCTION Figure 22-1. Status Transition (1/2) Normal operation mode (operation with main clock) End of oscillation stabilization time count End of oscillation stabilization time count Interrupt requestNote 3 End of oscillation stabilization time count Interrupt request Note 2 Setting of HALT mode Wait for stabilization of oscillation Setting of IDLE mode Wait for stabilization of oscillation Setting of STOP mode ResetNote 1 Wait for stabilization of oscillation Interrupt requestNote 4 ResetNote 5 ResetNote 5 HALT mode IDLE mode STOP mode Notes 1. Reset by RESET pin input, watchdog timer 1 overflow (WDTRES1), or watchdog timer 2 overflow (WDTRES2). 2. Non-maskable interrupt request signal (NMI, INTWDT1, INTWDT2) or unmasked maskable interrupt request signal. 3. Non-maskable interrupt request signal (NMI pin input, INTWDT2 (when the CPU is operating on the subclock)), unmasked external interrupt request signal (INTP0 to INTP6 pin input), or unmasked internal interrupt request signal from peripheral functions operable in IDLE mode. 4. Non-maskable interrupt request signal (NMI pin input, INTWDT2 (when the CPU is operating on the subclock)), unmasked external interrupt request signal (INTP0 to INTP6 pin input), or unmasked internal interrupt request signal from peripheral functions operable in STOP mode. 5. Reset by RESET pin input or watchdog timer 2 (when the CPU is operating on the subclock) overflow (WDTRES2). 658 User's Manual U16889EJ1V0UD CHAPTER 22 STANDBY FUNCTION Figure 22-1. Status Transition (2/2) Normal operation mode (operation with main clock) End of oscillation stabilization time count End of oscillation stabilization time count Setting of subclock operation mode Wait for stabilization of oscillation Setting of normal operation mode Wait for stabilization of oscillation ResetNote 1 ResetNote 1 Interrupt requestNote 2 Subclock operation mode (operation with subclock) Setting of IDLE mode Sub-IDLE mode Notes 1. Reset by RESET pin input or watchdog timer 2 overflow (WDTRES2). 2. Non-maskable interrupt request signal (NMI pin input, INTWDT2 (when the CPU is operating on the subclock)), unmasked external interrupt request signal (INTP0 to INTP6 pin input), or unmasked internal interrupt request signal from peripheral functions operable in sub-IDLE mode. User's Manual U16889EJ1V0UD 659 CHAPTER 22 STANDBY FUNCTION 22.2 Registers (1) Power save control register (PSC) This is an 8-bit register that controls the standby function. The STP bit of this register is used to specify the standby mode. The PSC register is a special register that can be written to only in a special sequence (refer to 3.4.7 Special registers). This register can be read or written in 8-bit or 1-bit units. After reset, PSC is cleared to 00H. After reset: 00H <> PSC NMI2M R/W Address: FFFFF1FEH <> <> INTM 0 0 <> STP 0 0 NMI0M NMI2M 0 1 Control of releasing standby modeNote by INTWDT2 signal Releasing standby modeNote by INTWDT2 signal enabled Releasing standby modeNote by INTWDT2 signal disabled Control of releasing standby modeNote by NMI pin input Releasing standby modeNote by NMI pin input enabled Releasing standby modeNote by NMI pin input disabled NMI0M 0 1 INTM 0 1 Control of releasing standby modeNote by maskable interrupt request signals Releasing standby modeNote by maskable interrupt request signals enabled Releasing standby modeNote by maskable interrupt request signals disabled STP 0 1 Normal mode Standby modeNote Standby modeNote setting Note In this case, standby mode means the IDLE/STOP mode; it does not include the HALT mode. Cautions 1. If the NMI2M, NMI0M, and INTM bits, and the STP bit are set to 1 at the same time, the setting of NMI2M, NMI0M, and INTM bits becomes invalid. If there is an unmasked interrupt request signal being held pending when the IDLE/STOP mode is set, set the bit corresponding to the interrupt request signal (NMI2M, NMI0M, or INTM) to 1, and then set the STP bit to 1. 2. When the IDLE/STOP mode is set, set the PSMR.PSM bit and then set the STP bit. 660 User's Manual U16889EJ1V0UD CHAPTER 22 STANDBY FUNCTION (2) Power save mode register (PSMR) This is an 8-bit register that controls the operation status in the standby mode and the clock operation. This register can be read or written in 8-bit or 1-bit units. After reset, PSMR is cleared to 00H. After reset: 00H R/W After reset: FFFFF820H <> PSMR XTSTP 0 0 0 0 0 0 PSM XTSTP 0 1 Specification of subclock oscillator use Subclock oscillator used Subclock oscillator not used PSM 0 1 IDLE mode STOP mode Specification of operation in standby mode Cautions 1. Be sure to clear the XTSTP bit to 0 during subclock resonator connection. 2. Be sure to clear bits 1 to 6 of the PSMR register to 0. 3. The PSM bit is valid only when the PSC.STP bit is 1. User's Manual U16889EJ1V0UD 661 CHAPTER 22 STANDBY FUNCTION (3) Oscillation stabilization time selection register (OSTS) The wait time until the oscillation stabilizes after the STOP mode is released is controlled by the OSTS register. The OSTS register can be read or written in 8-bit units. After reset, OSTS is set to 01H. After reset: 01H R/W Address: FFFFF6C0H OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Selection of oscillation stabilization time fX 4 MHz 5 MHz 1.638 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms 419.4 ms 10 MHz 0.819 ms 3.277 ms 6.554 ms 13.11 ms 26.21 ms 52.43 ms 104.9 ms 209.7 ms 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 2 /fX 215/fX 2 /fX 2 /fX 2 /fX 219/fX 2 /fX 2 /fX 21 20 18 17 16 13 2.048 ms 8.192 ms 16.38 ms 32.77 ms 65.54 ms 131.1 ms 262.1 ms 524.3 ms Cautions 1. The wait time following release of the STOP mode does not include the time until the clock oscillation starts ("a" in the figure below) following release of the STOP mode, regardless of whether the STOP mode is released by reset or the occurrence of an interrupt request signal. STOP mode release Voltage waveform of X1 pin a VSS 2. Be sure to clear bits 3 to 7 to 0. 3. The oscillation stabilization time following reset release is 215/fX (because the initial value of the OSTS register = 01H). 4. The oscillation stabilization time is also inserted during external clock input. Remark fX: Main clock oscillation frequency 662 User's Manual U16889EJ1V0UD CHAPTER 22 STANDBY FUNCTION 22.3 HALT Mode 22.3.1 Setting and operation status The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode. In the HALT mode, the clock oscillator continues operating. Only clock supply to the CPU is stopped; clock supply to the other on-chip peripheral functions continues. As a result, program execution is stopped, and the internal RAM retains the contents before the HALT mode was set. The on-chip peripheral functions that are independent of instruction processing by the CPU continue operating. Table 22-3 shows the operation status in the HALT mode. The average power consumption of the system can be reduced by using the HALT mode in combination with the normal operation mode for intermittent operation. Cautions 1. Insert five or more NOP instructions after the HALT instruction. 2. If the HALT instruction is executed with an unmasked interrupt request signal held pending, the system shift to the HALT mode, but the HALT mode is immediately released by the pending interrupt request signal. 22.3.2 Releasing HALT mode The HALT mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT1, INTWDT2 signal), an unmasked maskable interrupt request signal, and reset signal (RESET pin input, WDTRES1, WDTRES2 signal). After the HALT mode has been released, the normal operation mode is restored. (1) Releasing HALT mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal The HALT mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request. If the HALT mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. (a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, only the HALT mode is released, and that interrupt request signal is not acknowledged. The interrupt request signal itself is retained. (b) If an interrupt request with a priority higher than that of the interrupt request signal currently being serviced is issued (including a non-maskable interrupt request signal), the HALT mode is released and that interrupt request signal is acknowledged. Table 22-2. Operation After Releasing HALT Mode by Interrupt Request Signal Release Source Non-maskable interrupt request signal Maskable interrupt request signal Interrupt Enabled (EI) Status Execution branches to the handler address Execution branches to the handler address or the next instruction is executed The next instruction is executed Interrupt Disabled (DI) Status (2) Releasing HALT mode by reset The same operation as the normal reset operation is performed. User's Manual U16889EJ1V0UD 663 CHAPTER 22 STANDBY FUNCTION Table 22-3. Operation Status in HALT Mode Setting of HALT Mode Item CPU ROM correction Main clock oscillator Subclock oscillator Interrupt controller Timer P (TMP0) Note 1 When CPU Is Operating with Main Clock When Subclock Is Not Used Stops operation Stops operation Oscillation enabled - Operable Operable Operable Operable Operable Operable when main clock output is selected as count clock Operable Oscillation enabled When Subclock Is Used 16-bit timers (TM00 to TM05) 8-bit timers (TM50, TM51) Timer H (TMH0, TMH1) Watch timer Watchdog timer 1 Watchdog timer 2 Operable Operable when main clock is selected as count clock Operable Serial interface CSI00 to CSI02 CSIA0, CSIA1 I C0 2 Note 2 Operable Operable Operable Operable Operable Operable Operable when real-time output mode is selected Operable Retains status before HALT mode was set. Refer to CHAPTER 5 BUS CONTROL FUNCTION. The CPU registers, statuses, data, and all other internal data such as the contents of the internal RAM are retained as they were before the HALT mode was set. , I C1 2 Note 2 UART0 to UART2 Key interrupt function A/D converter D/A converter Real-time output Port function External bus interface Internal data Notes 1. 2. Only in the PD70F3218H, 70F3218HY Only in the PD703216Y, 703217Y, 70F3217Y, 70F3217HY, 70F3218HY 664 User's Manual U16889EJ1V0UD CHAPTER 22 STANDBY FUNCTION 22.4 IDLE Mode 22.4.1 Setting and operation status The IDLE mode is set by clearing the PSMR.PSM bit to 0 and setting the PSC.STP bit to 1 in the normal operation mode. In the IDLE mode, the clock oscillator continues operation but clock supply to the CPU and other on-chip peripheral functions stops. As a result, program execution stops and the contents of the internal RAM before the IDLE mode was set are retained. The CPU and other on-chip peripheral functions stop operating. However, the on-chip peripheral functions that can operate with the subclock or an external clock continue operating. Table 22-5 shows the operation status in the IDLE mode. The IDLE mode can reduce the power consumption more than the HALT mode because it stops the operation of the on-chip peripheral functions. The main clock oscillator does not stop, so the normal operation mode can be restored without waiting for the oscillation stabilization time after the IDLE mode has been released, in the same manner as when the HALT mode is released. Caution Insert five or more NOP instructions after the instruction that stores data in the PSC register to set the IDLE mode. 22.4.2 Releasing IDLE mode The IDLE mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal (when the CPU is operating on the subclock)), unmasked external interrupt request signal (INTP0 to INTP6 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the IDLE mode, or reset (RESET pin input, WDTRES2 signal (when the CPU is operating on the subclock)). After the IDLE mode has been released, the normal operation mode is restored. (1) Releasing IDLE mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal The IDLE mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request. If the IDLE mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is processed as follows. (a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, only the IDLE mode is released, and that interrupt request signal is not acknowledged. The interrupt request signal itself is retained. (b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the IDLE mode is released and that interrupt request signal is acknowledged. Table 22-4. Operation After Releasing IDLE Mode by Interrupt Request Signal Release Source Non-maskable interrupt request signal Maskable interrupt request signal Interrupt Enabled (EI) Status Execution branches to the handler address Execution branches to the handler address or the next instruction is executed The next instruction is executed Interrupt Disabled (DI) Status User's Manual U16889EJ1V0UD 665 CHAPTER 22 STANDBY FUNCTION (2) Releasing IDLE mode by reset The same operation as the normal reset operation is performed. Table 22-5. Operation Status in IDLE Mode Setting of IDLE Mode Item CPU ROM correction Main clock oscillator Subclock oscillator Interrupt controller Timer P (TMP0) Note 1 When CPU Is Operating with Main Clock When Subclock Is Not Used Stops operation Stops operation Oscillation enabled - Stops operation Stops operation TM00, TM02 to TM05: Stop operation TM01: Operable when INTWT is selected as count clock and fBRG is selected as count clock of WT TM00, TM02 to TM05: Stop operation TM01: Operable when INTWT is selected as count clock Oscillation enabled When Subclock Is Used 16-bit timers (TM00 to TM05) 8-bit timers (TM50, TM51) Timer H (TMH0) Timer H (TMH1) Watch timer Watchdog timer 1 Watchdog timer 2 Serial interface CSI00 to CSI02 CSIA0, CSIA1 I C0 2 Note 2 2 Note 2 * Operable when TI5m is selected as count clock * Operable when INTTM010 is selected as count clock and TM01 is enabled in IDLE mode Stops operation Stops operation Operable when main clock is selected as count clock Stops operation Stops operation Operable when fXT is selected as count clock Operable when fXT is selected as count clock Operable Operable when SCK0n input clock is selected as operation clock Stops operation Stops operation Operable when ASCK0 is selected as count clock Stops operation Operable Stops operation Stops operation (retains output) Note 3 Note 3 , I C1 UART0 UART1, UART2 Key interrupt function A/D converter D/A converter ch0: Stops operation (retains output) ch1: (For other conditions than following, refer to Note 3.) Operable when real-time output mode is selected and fXT is selected as count clock of TMH1 Real-time output Port function External bus interface Internal data Operable when INTTM5m is selected as real-time output trigger and TM5m is enabled in IDLE mode Retains status before IDLE mode was set. Refer to CHAPTER 5 BUS CONTROL FUNCTION. The CPU registers, statuses, data, and all other internal data such as the contents of the internal RAM are retained as they were before the IDLE mode was set. Notes 1. 2. 3. Only in the PD70F3218H, 70F3218HY Only in the PD703216Y, 703217Y, 70F3217Y, 70F3217HY, 70F3218HY If the IDLE mode is set immediately after D/A conversion has started (during conversion), the D/A converter continues operating until D/A conversion is complete and retains the output at the end of D/A conversion. Remark m = 0, 1 n = 0 to 2 666 User's Manual U16889EJ1V0UD CHAPTER 22 STANDBY FUNCTION 22.5 STOP Mode 22.5.1 Setting and operation status The STOP mode is set when the PSMR.PSM bit is set to 1 and the PSC.STP bit is set to 1 in the normal operation mode. In the STOP mode, the subclock oscillator continues operating but the main clock oscillator stops. Clock supply to the CPU and the on-chip peripheral functions is stopped. As a result, program execution is stopped, and the contents of the internal RAM before the STOP mode was set are retained. The on-chip peripheral functions that operate with the clock oscillated by the subclock oscillator or an external clock continue operating. Table 22-7 shows the operation status in the STOP mode. Because the STOP stops operation of the main clock oscillator, it reduces the power consumption to a level lower than the IDLE mode. If the subclock oscillator and external clock are not used, the power consumption can be minimized with only leakage current flowing. Caution Insert five or more NOP instructions after the instruction that stores data in the PSC register to set the STOP mode. 22.5.2 Releasing STOP mode The STOP mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal (when the CPU is operating on the subclock)), unmasked external interrupt request signal (INTP0 to INTP6 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the STOP mode, or reset (RESET pin input, WDTRES2 signal (when the CPU is operating on the subclock)). After the STOP mode has been released, the normal operation mode is restored after the oscillation stabilization time has been secured. (1) Releasing STOP mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal The STOP mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request. If the software STOP mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows. (a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, only the STOP mode is released, and that interrupt request signal is not acknowledged. The interrupt request signal itself is retained. (b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the STOP mode is released and that interrupt request signal is acknowledged. Table 22-6. Operation After Releasing STOP Mode by Interrupt Request Signal Release Source Non-maskable interrupt request signal Maskable interrupt request signal Interrupt Enabled (EI) Status Execution branches to the handler address Execution branches to the handler address or the next instruction is executed The next instruction is executed Interrupt Disabled (DI) Status (2) Releasing STOP mode by reset The same operation as the normal reset operation is performed. User's Manual U16889EJ1V0UD 667 CHAPTER 22 STANDBY FUNCTION Table 22-7. Operation Status in STOP Mode Setting of STOP Mode Item CPU ROM correction Main clock oscillator Subclock oscillator Interrupt controller Timer P (TMP0) Note 1 When CPU Is Operating with Main Clock When Subclock Is Not Used Stops operation Stops operation Oscillation stops - Stops operation Stops operation Stops operation TM00, TM02 to TM05: Stop operation TM01: Operable when INTWT is selected as count clock and fXT is selected as count clock of WT Operable when TI5m is selected as count clock or when INTTM010 is selected as count clock and TM01 is enabled in STOP mode Oscillation enabled When Subclock Is Used 16-bit timers (TM00 to TM05) 8-bit timers (TM50, TM51) Operable when TI5m is selected as count clock Timer H (TMH0) Timer H (TMH1) Watch timer Watchdog timer 1 Watchdog timer 2 Serial interface CSI00 to CSI02 CSIA0, CSIA1 I C0 2 Note 2 2 Note 2 Stops operation Stops operation Stops operation Stops operation Stops operation Operable when fXT is selected as count clock Operable when fXT is selected as count clock Operable when fXT is selected as count clock Operable when SCK0n input clock is selected as operation clock Stops operation Stops operation Operable when ASCK0 is selected as count clock Stops operation Operable Stops operation Stops operation (retains output) Note 3 Note 3 , I C1 UART0 UART1, UART2 Key interrupt function A/D converter D/A converter ch0: Stops operation (retains output) ch1: (For conditions other than the following, refer to Note 3.) Operable when real-time output mode is selected and fXT is selected as count clock of TMH1 Real-time output Port function External bus interface Internal data Operable when INTTM5m is selected as real-time output trigger and TM5m is enabled in STOP mode Retains status before STOP mode was set. Refer to CHAPTER 5 BUS CONTROL FUNCTION. The CPU registers, statuses, data, and all other internal data such as the contents of the internal RAM are retained as they were before the STOP mode was set. Notes 1. 2. 3. Only in the PD70F3218H, 70F3218HY Only in the PD703216Y, 703217Y, 70F3217Y, 70F3217HY, 70F3218HY If the STOP mode is set immediately after D/A conversion has started (during conversion), the D/A converter continues operating until D/A conversion is complete, and retains the output at the end of D/A conversion. Remark m = 0, 1 n = 0 to 2 668 User's Manual U16889EJ1V0UD CHAPTER 22 STANDBY FUNCTION 22.5.3 Securing oscillation stabilization time when STOP mode is released When the STOP mode is released, only the oscillation stabilization time set by the OSTS register elapses. If the STOP mode has been released by reset, however, the reset value of the OSTS register, 215/fX (8.192 ms at fX = 4 MHz) elapses. The operation performed when the STOP mode is released by an interrupt request signal is shown below. Figure 22-2. Oscillation Stabilization Time Oscillated waveform Main clock STOP mode status Interrupt request Main clock oscillator stops Oscillation stabilization time count Caution For details of the OSTS register, refer to 22.2 (3) register (OSTS). Oscillation stabilization time selection User's Manual U16889EJ1V0UD 669 CHAPTER 22 STANDBY FUNCTION 22.6 Subclock Operation Mode 22.6.1 Setting and operation status The subclock operation mode is set when the PCC.CK3 bit is set to 1 in the normal operation mode. When the subclock operation mode is set, the internal system clock is changed from the main clock to the subclock. When the PCC.MCK bit is set to 1, the operation of the main clock oscillator is stopped. As a result, the system operates only with the subclock. Table 22-8 shows the operation status in subclock operation mode. In the subclock operation mode, the power consumption can be reduced to a level lower than in the normal operation mode because the subclock is used as the internal system clock. In addition, the power consumption can be further reduced to the level of the STOP mode by stopping the operation of the main clock oscillator. Cautions 1. When manipulating the CK3 bit, do not change the set values of the PCC.CK2 to PCC.CK0 bits (using a bit manipulation instruction to manipulate the bit is recommended). For details, refer to 6.3 (1) Processor clock control register (PCC). 2. If the following conditions are not satisfied, change the CK2 to CK0 bits so that the conditions are satisfied and set the subclock operation mode. Main clock (fXX) > Subclock (fXT: 32.768 kHz) x 4 22.6.2 Releasing subclock operation mode The subclock operation mode is released when the CK3 bit is cleared to 0 or by reset (RESET pin input, WDTRES1, WDTRES2 signal). If the main clock is stopped (MCK bit = 1), set the MCK bit to 1, secure the oscillation stabilization time of the main clock by software, and clear the CK3 bit to 0. The normal operation mode is restored when the subclock operation mode is released. Caution When manipulating the CK3 bit, do not change the set values of the CK2 to CK0 bits (using a bit manipulation instruction to manipulate the bit is recommended). For details, refer to 6.3 (1) Processor clock control register (PCC). 670 User's Manual U16889EJ1V0UD CHAPTER 22 STANDBY FUNCTION Table 22-8. Operation Status in Subclock Operation Mode Setting of Subclock Operation Item CPU ROM correction Subclock oscillator Interrupt controller Timer P (TMP0) Note 1 Operation Status When Main Clock Is Oscillating Operable Operable Oscillation enabled Operable Operable Operable Stops operation TM00, TM02 to TM05: Stop operation TM01: Operable when INTWT is selected as count clock and fXT is selected as count clock of WT * Operable when TI5m is selected as count clock * Operable when INTTM010 is selected as count clock and when TM01 is enabled in subclock operation mode Stops operation Operable when fXT is selected as count clock Operable when fXT is selected as count clock Stops operation Operable when fXT is selected as count clock Operable when SCK0n input clock is selected as operation clock Stops operation Stops operation Operable when ASCK0 is selected as count clock Stops operation When Main Clock Is Stopped Mode 16-bit timers (TM00 to TM05) 8-bit timers (TM50, TM51) Operable Timer H (TMH0) Timer H (TMH1) Watch timer Watchdog timer 1 Watchdog timer 2 Serial interface CSI00 to CSI02 CSIA0, CSIA1 I C0 2 Note 2 Operable Operable Operable Operable Operable Operable Operable Operable Operable Operable Operable Operable Operable , I C1 2 Note 2 UART0 UART1, UART2 Key interrupt function A/D converter D/A converter Stops operation ch0: Operable when normal mode is selected ch1: Operable under the following conditions * When normal mode is selected * When real-time output mode is selected and fXT is selected as count clock of TMH1 Operable when INTTM5m is selected as real-time output trigger and TI5m is selected as count clock of TM5m Real-time output Operable Port function External bus interface Internal data Settable Operable Settable Notes 1. 2. Only in the PD70F3218H, 70F3218HY Only in the PD703216Y, 703217Y, 70F3217Y, 70F3217HY, 70F3218HY Remark m = 0, 1 n = 0 to 2 User's Manual U16889EJ1V0UD 671 CHAPTER 22 STANDBY FUNCTION 22.7 Sub-IDLE Mode 22.7.1 Setting and operation status The sub-IDLE mode is set when the PSMR.PSM bit is cleared to 0 and the PSC.STP bit is set to 1 in the subclock operation mode. In this mode, the clock oscillator continues operation but clock supply to the CPU and the other on-chip peripheral functions is stopped. As a result, program execution is stopped and the contents of the internal RAM before the sub-IDLE mode was set are retained. The CPU and the other on-chip peripheral functions are stopped. However, the on-chip peripheral functions that can operate with the subclock or an external clock continue operating. Table 22-10 shows the operation status in the sub-IDLE mode. Because the sub-IDLE mode stops operation of the CPU and other on-chip peripheral functions, it can reduce the power consumption more than the subclock operation mode. If the sub-IDLE mode is set after the main clock has been stopped, the power consumption can be reduced to a level as low as that in the STOP mode. 22.7.2 Releasing sub-IDLE mode The sub-IDLE mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal (when the CPU is operating on the subclock)), unmasked external interrupt request signal (INTP0 to INTP6 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the sub-IDLE mode, or reset (RESET pin input, WDTRES2 signal (when the CPU is operating on the subclock)). When the sub-IDLE mode is released by an interrupt request signal, the subclock operation mode is set. If it is released by reset, the normal operation mode is restored. (1) Releasing sub-IDLE mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal The sub-IDLE mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request. If the sub-IDLE mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later is serviced as follows. (a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, only the sub-IDLE mode is released, and that interrupt request signal is not acknowledged. The interrupt request signal itself is retained. (b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the sub-IDLE mode is released and that interrupt request signal is acknowledged. Table 22-9. Operation After Releasing Sub-IDLE Mode by Interrupt Request Signal Release Source Non-maskable interrupt request signal Maskable interrupt request signal Interrupt Enabled (EI) Status Execution branches to the handler address Execution branches to the handler address or the next instruction is executed The next instruction is executed Interrupt Disabled (DI) Status (2) Releasing sub-IDLE mode by reset The same operation as the normal reset operation is performed. 672 User's Manual U16889EJ1V0UD CHAPTER 22 STANDBY FUNCTION Table 22-10. Operation Status in Sub-IDLE Mode Setting of Sub-IDLE Item CPU ROM correction Subclock oscillator Interrupt controller Timer P (TMP0) Note 1 Operation Status When Main Clock Is Oscillating Stops operation Stops operation Oscillation enabled Stops operation Stops operation TM00, TM02 to TM05: Stop operation TM01: Operable when INTWT is selected as count clock * Operable when TI5m is selected as count clock * Operable when INTTM010 is selected as count clock and INTWT is selected as count clock of TM01 Stops operation Operable when fXT is selected as count clock Stops operation Operable Operable when fXT is selected as count clock Operable when fXT is selected as count clock Stops operation TM00, TM02 to TM05: Stop operation TM01: Operable when INTWT is selected as count clock and fXT is selected as count clock of WT * Operable when TI5m is selected as count clock * Operable when INTTM010 is selected as count clock and when TM01 is enabled in sub-IDLE mode When Main Clock Is Stopped Mode 16-bit timers (TM00 to TM05) 8-bit timers (TM50, TM51) Timer H (TMH0) Timer H (TMH1) Watch timer Watchdog timer 1 Watchdog timer 2 Serial interface CSI00 to CSI02 CSIA0, CSIA1 I C0 2 Note 2 Stops operation Stops operation Stops operation Operable when SCK0n input clock is selected as operation clock , I C1 2 Note 2 UART0 UART1, UART2 Key interrupt function A/D converter D/A converter Operable when ASCK0 is selected as count clock Stops operation Operable Stops operation ch0: Stops operation (retains output) ch1: (For other than the following conditions, refer to Note 3.) Operable when real-time output mode is selected and fXT is selected as count clock of TMH1. Operable when INTTM5m is selected as real-time output trigger and TI5m is selected as count clock of TM5m Retains status before sub-IDLE mode was set. Refer to CHAPTER 5 BUS CONTROL FUNCTION. The CPU registers, statuses, data, and all other internal data such as the contents of the internal RAM are retained as they were before the sub-IDLE mode was set. Note 3 Real-time output Port function External bus interface Internal data Notes 1. 2. 3. Only in the PD70F3218H, 70F3218HY Only in the PD703216Y, 703217Y, 70F3217Y, 70F3217HY, 70F3218HY If the sub-IDLE mode is set immediately after D/A conversion has started (during conversion), the D/A converter continues operating until D/A conversion is complete and retains the output at the end of D/A conversion. Remark m = 0, 1 n = 0 to 2 User's Manual U16889EJ1V0UD 673 CHAPTER 23 RESET FUNCTION 23.1 Overview The following reset functions are available. * Reset function by RESET pin input * Reset function by overflow of watchdog timer 1 (WDTRES1) * Reset function by overflow of watchdog timer 2 (WDTRES2) If the RESET pin goes high, the reset status is released, and the CPU starts executing the program. Initialize the contents of each register in the program as necessary. The RESET pin has a noise eliminator that operates by analog delay to prevent malfunction caused by noise. 23.2 Configuration Figure 23-1. Reset Block Diagram RESET Analog delay circuit Reset signal to CPU WDTRES1 issued due to overflow Reset signal to CG Reset controller Reset signal to other peripheral macros Count clock Watchdog timer 1 Count clock Watchdog timer 2 WDTRES2 issued due to overflow 674 User's Manual U16889EJ1V0UD CHAPTER 23 RESET FUNCTION 23.3 Operation The system is reset, initializing each hardware unit, when a low level is input to the RESET pin or if watchdog timer 1 or watchdog timer 2 overflows (WDTRES1 or WDTRES2). While a low level is being input to the RESET pin, the main clock oscillator stops. Therefore, the overall power consumption of the system can be reduced. If the RESET pin goes high or if the WDTRES1 or WDTRES2 signal is received, the reset status is released. If the reset status is released by RESET pin input or the WDTRES2 signal, the oscillation stabilization time elapses (reset value of OSTS register: 215/fXX) and then the CPU starts program execution. If the reset status is released by the WDTRES1 signal, the oscillation stabilization time is not inserted because the main system clock oscillator does not stop. User's Manual U16889EJ1V0UD 675 CHAPTER 23 RESET FUNCTION Table 23-1. Hardware Status on RESET Pin Input or Occurrence of WDTRES2 Signal Item Main clock oscillator (fX) Subclock oscillator (fXT) Peripheral clock (fXX to fXX/1024), internal system clock (fCLK), CPU clock (fCPU) During Reset Oscillation stops (fX = 0 level). After Reset Oscillation starts Note 1 Oscillation can continue without effect from reset Operation stops . Operation starts. However, operation stops during oscillation stabilization time count. Note 2 Watchdog timer 1 clock (fXW) Internal RAM Operation stops Operation starts Undefined if power-on reset occurs or writing data to RAM and reset conflict (data loss); otherwise, retains values immediately before reset input. I/O lines (ports) On-chip peripheral I/O registers Other on-chip peripheral functions High impedance Initialized to specified status Operation stops Operation can be started Notes 1. The on-chip feedback resistor is "connected" by default (refer to 6.3 (1) Processor clock control register (PCC)). 2. The clock is in the initialized status (interval timer mode). Table 23-2. Hardware Status on Occurrence of WDTRES1 Signal Item Main clock oscillator (fX) Subclock oscillator (fXT) Peripheral clock (fXX to fXX/1024), internal system clock (fCLK), CPU clock (fCPU) Watchdog timer 1 clock (fXW) Internal RAM Operation continues Undefined if writing data to RAM and reset conflict (data loss); otherwise, retains values immediately before reset input. I/O lines (ports) On-chip peripheral I/O registers Other on-chip peripheral functions High impedance Initialized to specified status Operation stops Operation can be started During Reset Oscillation continues Note After Reset Oscillation can continue without effect from reset Operation stops Note . Operation starts Note The on-chip feedback resistor is "connected" by default (refer to 6.3 (1) Processor clock control register (PCC)). 676 User's Manual U16889EJ1V0UD CHAPTER 23 RESET FUNCTION Figure 23-2. Hardware Status on RESET Input fX fCLK Initialized to fXX/8 operation RESET Analog delay (eliminated as noise) Internal system reset signal Analog Analog delay Analog delay (eliminated as noise) delay Oscillation stabilization time count Overflow of timer for oscillation stabilization Figure 23-3. Operation on Power Application VDD fX fCLK Initialized to fXX/8 operation RESET Analog delay Internal system reset signal Oscillation stabilization time count Overflow of timer for oscillation stabilization User's Manual U16889EJ1V0UD 677 CHAPTER 24 REGULATOR 24.1 Overview The V850ES/KJ1 includes a regulator to reduce the power consumption and noise. This regulator supplies a stepped-down VDD power supply voltage to the oscillator block and internal logic circuits (except the A/D converter, D/A converter, and output buffer). The regulator output voltage is set to 3.6 V (TYP.). Figure 24-1. Regulator AVREF0 A/D converter 2.7 to 5.5 V D/A converter 2.7 to 5.5 V Flash memory BVDD I/O buffer 2.7 to 5.5 V BVDD Bidirectional level shifter AVREF1 VPP VDD REGC Regulator Main/sub oscillator Internal digital circuits 3.6 V (TYP.) EVDD EVDD I/O buffer (normal port) 2.7 to 5.5 V Caution Use the regulator with a setting of VDD = EVDD = AVREF0 = AVREF1 BVDD. 24.2 Operation The regulator stops operating in the following modes (but only when REGC = VDD). * During reset * In STOP mode * In sub-IDLE mode When using the regulator, be sure to connect a capacitor (10 F) to the REGC pin to stabilize the regulator output. A diagram of the regulator pin connections is shown below. 678 User's Manual U16889EJ1V0UD CHAPTER 24 REGULATOR Figure 24-2. REGC Pin Connection (a) When REGC = VDD VDD Input voltage = 2.7 to 5.5 V REG REGC Voltage supply to oscillator/internal logic = 2.7 to 5.5 V (b) When connecting REGC pin to VSS via a capacitor VDD Input voltage = 4.0 to 5.5 V REG REGC Voltage supply to oscillator/internal logic = 3.6 V 10 F (recommended) User's Manual U16889EJ1V0UD 679 CHAPTER 25 ROM CORRECTION FUNCTION 25.1 Overview The ROM correction function is used to replace part of the program in the internal ROM with the program of an external memory or the internal RAM. By using this function, program bugs found in the internal ROM can be corrected. Up to four address can be specified for correction. Figure 25-1. Block Diagram of ROM Correction Instruction address bus Correction address register n (CORADn) Comparator DBTRAP instruction generation block ROM Correction control register (CORENn bit) Block replacing bug with DBTRAP instruction Data bus Remark n = 0 to 3 680 User's Manual U16889EJ1V0UD CHAPTER 25 ROM CORRECTION FUNCTION 25.2 Registers (1) Correction address registers 0 to 3 (CORAD0 to CORAD3) These registers are used to set the first address of the program to be corrected. The program can be corrected at up to four places because four CORADn registers are provided. The CORADn register can be read or written in 32-bit units. If the higher 16 bits of the CORADn register are used as the CORADnH register, and the lower 16 bits as the CORADnL register, these registers can be read or written in 16-bit units. After reset, CORADn is cleared to 00000000H. Because the ROM capacity differs depending on the product, set correction addresses in the following ranges. PD703216, 703216Y (96 KB): 0000000H to 0017FFEH PD703217, 703217Y, 70F3217, 70F3217Y, 70F3217H, 70F3217HY (128 KB): 0000000H to 001FFFEH PD70F3218H, 70F3218HY (256 KB): 0000000H to 003FFFEH Bits 0 and 20 to 31 are fixed to 0. After reset: 00000000H R/W (a) 96 KB, 128 KB 31 CORADn Fixed to 0 (n = 0 to 3) Address: CORAD0 FFFFF840H, CORAD0L FFFFF840H, CORAD0H FFFFF842H, CORAD1 FFFFF844H, CORAD1L FFFFF844H, CORAD1H FFFFF846H, CORAD2 FFFFF848H, CORAD2L FFFFF848H, CORAD2H FFFFF84AH, CORAD3 FFFFF84CH, CORAD3L FFFFF84CH, CORAD3H FFFFF84EH 20 19 17 16 10 Note Correction address 0 (b) 256 KB 31 CORADn Fixed to 0 (n = 0 to 3) Note Correction address 0 20 19 18 17 10 Note Be sure to clear these bits to 0. User's Manual U16889EJ1V0UD 681 CHAPTER 25 ROM CORRECTION FUNCTION (2) Correction control register (CORCN) This register disables or enables the correction operation at the address specified by the CORADn register. Each channel can be enabled or disabled by this register. This register can be read or written in 8-bit or 1-bit units. After reset, CORCN is cleared to 00H. After reset: 00H R/W Address: FFFFF880H <> <> <> <> CORCN 0 0 0 0 COREN3 COREN2 COREN1 COREN0 CORENn 0 1 Disabled Enabled Correction operation enable/disable Remark n = 0 to 3 Table 25-1. Correspondence Between CORCN Register Bits and CORADn Registers CORCN Register Bit COREN3 COREN2 COREN1 COREN0 Corresponding CORADn Register CORAD3 CORAD2 CORAD1 CORAD0 25.3 ROM Correction Operation and Program Flow <1> If the address to be corrected and the fetch address of the internal ROM match, the fetch code is replaced by the DBTRAP instruction. <2> When the DBTRAP instruction is executed, execution branches to address 00000060H. <3> Software processing after branching causes the result of ROM correction to be judged (the fetch address and ROM correction operation are confirmed) and execution to branch to the correction software. <4> After the correction software has been executed, the return address is set, and return processing is started by the DBRET instruction. Cautions 1. The software that performs <3> and <4> must be executed in the internal ROM/RAM. 2. When setting an address to be corrected to the CORADn register, clear the higher bits to 0 in accordance with the capacity of the internal ROM. 3. The ROM correction function cannot be used to correct the data of the internal ROM. It can only be used to correct instruction codes. If ROM correction is used to correct data, that data is replaced with the DBTRAP instruction code. 682 User's Manual U16889EJ1V0UD CHAPTER 25 ROM CORRECTION FUNCTION Figure 25-2. ROM Correction Operation and Program Flow Reset & start Initialize microcontroller Set CORADn register Load program for judgment of ROM correction and correction codes Set CORCN register Read data for setting ROM correction from external memory CORENn bit = 1? Yes No Execute fetch code Fetch address = CORADn? Yes Change fetch code to DBTRAP instruction Execute DBTRAP instruction Jump to address 00000060H Branch to ROM correction judgment address No Execute fetch code CORADn = DBPC - 2? Yes Branch to correction code address of corresponding channel n Execute correction code No ILGOP processing Write return address to DBPC. Write value of PSW to DBPSW as necessary. Execute DBRET instruction Remarks 1. : Processing by user program (software) : Processing by ROM correction (hardware) 2. n = 0 to 3 User's Manual U16889EJ1V0UD 683 CHAPTER 26 FLASH MEMORY (SINGLE POWER) The following products are the flash memory versions (single power) of the V850ES/KJ1. Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing and application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluation for the commercial samples (not engineering samples) of the mask ROM version. For the electrical specifications related to the flash memory rewriting, refer to CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET). * PD70F3217H, 70F3217HY: 128 KB flash memory * PD70F3218H, 70F3218HY: 256 KB flash memory Flash memory versions are commonly used in the following development environments and mass production applications. For altering software after the V850ES/KJ1 is soldered onto the target system. For data adjustment when starting mass production. For differentiating software according to the specification in small scale production of various models. For facilitating inventory management. For updating software after shipment. 26.1 Features 4-byte/1-clock access (when instruction is fetched) Capacity: 256/128 KB Write voltage: Erase/write with a single power supply Rewriting method * Rewriting by communication with dedicated flash programmer via serial interface (on-board/off-board programming) * Rewriting flash memory by user program (self programming) Flash memory write prohibit function supported (security function) Safe rewriting of entire flash memory area by self programming using boot swap function Interrupts can be acknowledged during self programming. Caution When writing/erasing the flash memory using a flash programmer, a single-power flash memory differs from a two-power flash memory in the following points. * A flash programming mode setting pin (FLMD1 pin) must be connected in addition to the pins connected in a two-power flash memory. * The pin used as a handshake signal differs when writing/erasing the flash memory with CSI + HS communication. Two-power flash memory: PCS1/CS1 Single-power flash memory: PCM0/WAIT 684 User's Manual U16889EJ1V0UD CHAPTER 26 FLASH MEMORY (SINGLE POWER) 26.2 Memory Configuration The 256/128 KB internal flash memory area is divided into 128/64 blocks and can be programmed/erased in block units. All the blocks can also be erased at once. When the boot swap function is used, the physical memory (blocks 0 to 3) located at the addresses of boot area 0 is replaced by the physical memory (blocks 4 to 7) located at the addresses of boot area 1. For details of the boot swap function, refer to 26.5 Rewriting by Self Programming. Figure 26-1. Flash Memory Mapping 003FFFFH Block 127 (2 KB) 003F800H 003F7FFH On-chip peripheral I/O area (4 KB) 3FEC000H 3FEBFFFH Internal RAM area (60 KB) 3FF0000H 3FEFFFFH 3FFFFFFH Block 126 (2 KB) 003F000H 003EFFFH Block 125 (2 KB) 003E800H 003E7FFH 0020000H 001FFFFH Block 63 (2 KB) Use prohibited Block 63 (2 KB) 0005000H 0004FFFH 0004800H 00047FFH Block 8 (2 KB) 1000000H 0FFFFFFH Block 8 (2 KB) 0004000H 0003FFFH Block 7 (2 KB) Block 7 (2 KB) 0003800H 00037FFH Block 6 (2 KB) Block 6 (2 KB) 0003000H 0002FFFH External memory area (14 MB) Block 5 (2 KB) Block 5 (2 KB) 0002800H 00027FFH Block 4 (2 KB) Block 4 (2 KB) 0002000H 0001FFFH 0200000H 01FFFFFH 0100000H 00FFFFFH Block 3 (2 KB) External memory area (1 MB) Use prohibited Block 1 (2 KB) Internal flash memory area (256/128 KB) 0000000H Block 1 (2 KB) 0000800H 00007FFH Block 0 (2 KB) Block 0 (2 KB) 0000000H Block 3 (2 KB) 0001800H 00017FFH Block 2 (2 KB) Block 2 (2 KB) 0001000H 0000FFFH Boot area 0Note (8 KB) Boot area 1Note (8 KB) Note Boot area 0 (blocks 0 to 3): Boot area Boot area 1 (blocks 4 to 7): Area used to replace boot area via boot swap function User's Manual U16889EJ1V0UD 685 CHAPTER 26 FLASH MEMORY (SINGLE POWER) 26.3 Functional Outline The internal flash memory of the V850ES/KJ1 can be rewritten by using the rewrite function of the dedicated flash programmer, regardless of whether the V850ES/KJ1 has already been mounted on the target system or not (onboard/off-board programming). In addition, a security function that prohibits rewriting the user program written to the internal flash memory is also supported, so that the program cannot be changed by an unauthorized person. The rewrite function using the user program (self programming) is ideal for an application where it is assumed that the program is changed after production/shipment of the target system. A boot swap function that rewrites the entire flash memory area safely is also supported. In addition, interrupt servicing is supported during self programming, so that the flash memory can be rewritten under various conditions, such as while communicating with an external device. Table 26-1. Rewrite Method Rewrite Method On-board programming Functional Outline Flash memory can be rewritten after the device is mounted on the target system, by using a dedicated flash programmer. Flash memory can be rewritten before the device is mounted on the target system, by using a dedicated flash programmer and a dedicated program adapter board (FA series). Self programming Flash memory can be rewritten by executing a user program that has been written to the flash memory in advance by means of on-board/offboard programming. (During self-programming, instructions cannot be fetched from or data access cannot be made to the internal flash memory area. Therefore, the rewrite program must be transferred to the internal RAM or external memory in advance). Normal operation mode Operation Mode Flash memory programming mode Off-board programming Remark The FA series is a product of Naito Densei Machida Mfg. Co., Ltd. 686 User's Manual U16889EJ1V0UD CHAPTER 26 FLASH MEMORY (SINGLE POWER) Table 26-2. Basic Functions Function Functional Outline Support ( : Supported, x: Not supported) On-Board/Off-Board Programming Block erasure The contents of specified memory blocks are erased. The contents of the entire memory area are erased all at once. Write Writing to specified addresses, and a verify check to see if write level is secured are performed. Verify/checksum Data read from the flash memory is compared with data transferred from the flash programmer. Blank check The erasure status of the entire memory is checked. Security setting Use of the block erase command, chip erase command, and program command can be prohibited. x (Only values set by onboard/off-board programming can be retained) x (Can be read by user program) x Self Programming Chip erasure The following table lists the security functions. The block erase command prohibit, chip erase command prohibit, and program command prohibit functions are enabled by default after shipment, and security can be set by rewriting via on-board/off-board programming. Each security function can be used in combination with the others at the same time. Table 26-3. Security Functions Function Function Outline Rewriting Operation When Prohibited ( : Executable, x: Not Executable) On-Board/Off-Board Programming Block erase command prohibit Execution of a block erase command on all blocks is prohibited. Setting of prohibition can be initialized by execution of a chip erase command. Execution of block erase and chip erase commands on all the blocks is prohibited. Once prohibition is set, setting of prohibition cannot be initialized because the chip erase command cannot be executed. Program command prohibit Write and block erase commands on all the blocks are prohibited. Setting of prohibition can be initialized by execution of the chip erase command. Block erase command: x Chip erase command: Program command: x Block erase command: x Chip erase command: Program command: Block erase command: x Chip erase command: x Program command: Can always be rewritten regardless of setting of prohibition Self Programming Chip erase command prohibit User's Manual U16889EJ1V0UD 687 CHAPTER 26 FLASH MEMORY (SINGLE POWER) 26.4 Rewriting by Dedicated Flash Programmer The flash memory can be rewritten by using a dedicated flash programmer after the V850ES/KJ1 is mounted on the target system (on-board programming). The flash memory can also be rewritten before the device is mounted on the target system (off-board programming) by using a dedicated program adapter (FA series). 26.4.1 Programming environment The following shows the environment required for writing programs to the flash memory of the V850ES/KJ1. Figure 26-2. Environment Required for Writing Programs to Flash Memory RS-232C XXXX YYYY FLMD0 FLMD1 Bxxxxx Cxxxxxx XXXX XXXXXX Axxxx XXX YYY PG-FP4 (Flash Pro4) USB Dedicated flash programmer Host machine XXXXX STATVE VDD VSS RESET UART0/CSI00 V850ES/KJ1 A host machine is required for controlling the dedicated flash programmer. UART0 or CSI00 is used for the interface between the dedicated flash programmer and the V850ES/KJ1 to perform writing, erasing, etc. A dedicated program adapter (FA series) is required for off-board writing. Remark The FA series is a product of Naito Densei Machida Mfg. Co., Ltd. 688 User's Manual U16889EJ1V0UD CHAPTER 26 FLASH MEMORY (SINGLE POWER) 26.4.2 Communication mode Communication between the dedicated flash programmer and the V850ES/KJ1 is performed by serial communication using the UART0 or CSI00 interfaces of the V850ES/KJ1. (1) UART0 Transfer rate: 9,600 to 153,600 bps Figure 26-3. Communication with Dedicated Flash Programmer (UART0) FLMD0 FLMD1 XXXX YYYY FLMD0 FLMD1 Bxxxxx Cxxxxxx STATVE XXX YYY XXXXX XXXX XXXXXX Axxxx VDD GND RESET RxD TxD CLK VDD VSS RESET TXD0 RXD0 X1 X2 V850ES/KJ1 PG-FP4 (Flash Pro4) Dedicated flash programmer (2) CSI00 Serial clock: 2.4 kHz to 2.5 MHz (MSB first) Figure 26-4. Communication with Dedicated Flash Programmer (CSI00) FLMD0 FLMD1 FLMD0 FLMD1 VDD XXXXXX VDD VSS RESET SO00 SI00 SCK00 X1 X2 V850ES/KJ1 Axxxx XXXX YYYY Bxxxxx Cxxxxxx STATVE GND RESET XXX YYY PG-FP4 (Flash Pro4) XXXXX XXXX Dedicated flash programmer SI SO SCK CLK User's Manual U16889EJ1V0UD 689 CHAPTER 26 FLASH MEMORY (SINGLE POWER) (3) CSI00 + HS Serial clock: 2.4 kHz to 2.5 MHz (MSB first) Figure 26-5. Communication with Dedicated Flash Programmer (CSI00 + HS) FLMD0 FLMD1 FLMD0 FLMD1 VDD XXXX YYYY VDD VSS RESET SO00 SI00 SCK00 X1 X2 V850ES/KJ1 Bxxxxx Cxxxxxx STATVE XXXX XXXXXX Axxxx GND RESET SI SO SCK CLK XXX YYY PG-FP4 (Flash Pro4) Dedicated flash programmer XXXXX HS PCM0 The dedicated flash programmer outputs the transfer clock, and the V850ES/KJ1 operates as a slave. When the PG-FP4 is used as the dedicated flash programmer, it generates the following signals to the V850ES/KJ1. For details, refer to the PG-FP4 User's Manual (U15260E). Table 26-4. Signal Connections of Dedicated Flash Programmer (PG-FP4) PG-FP4 Signal Name FLMD0 FLMD1 VDD GND CLK RESET SI/RxD SO/TxD SCK HS V850ES/KJ1 Pin Function Pin Name FLMD0 FLMD1 VDD VSS X1, X2 RESET SO00 SI00 SCK00 PCM0 x x Processing for Connection UART0 CSI00 CSI00 + HS I/O Output Output - - Output Output Input Output Output Input Write enable/disable Write enable/disable VDD voltage generation/voltage monitor Ground Clock output to V850ES/KJ1 Reset signal Receive signal Transmit signal Transfer clock Handshake signal for CSI00 + HS communication Note 1 Note 1 Note 1 x Note 2 x Note 2 x Note 2 x Note 3 x Note 3 x Note 3 x Notes 1. Wire the pin as shown in Figure 26-6, or connect it to GND on board via a pull-down resistor. 2. Connect the pin to supply power from the PG-FP4. 3. Connect these pins to supply a clock from the PG-FP4 (wire as shown in Figure 26-6, or create an oscillator on board and supply the clock). Remark : Must be connected. x: Does not have to be connected. 690 User's Manual U16889EJ1V0UD CHAPTER 26 FLASH MEMORY (SINGLE POWER) Table 26-5. Wiring Between PD70F3217H, 70F3217HY, 70F3218H, and 70F3218HY, and PG-FP4 Pin Configuration of Flash Programmer (PG-FP4) Signal Name SI/RXD SO/TXD SCK CLK I/O Input Output Output Output Pin Function Receive signal Transmit signal Transfer clock Clock to V850ES/KJ1 Pin Name on FA Board SI SO SCK X1 X2 /RESET FLMD0 FLMD1 Output Input Input Reset signal Write voltage Write voltage /RESET FLMD0 FLMD1 With CSI00-HS Pin Name P41/SO00 P40/SI00 Pin No. 23 22 With CSI00 Pin Name P41/SO00 P40/SI00 Pin No. 23 22 With UART0 Pin Name P30/TXD0 P31/RXD0 Pin No. 25 26 P42/SCK00 24 X1 X2 Note 1 P42/SCK00 24 X1 X2 Note 1 Not needed Not needed X1 X2 Note 1 12 13 14 8 12 13 14 8 12 13 14 8 RESET FLMD0 RESET FLMD0 RESET FLMD0 PDL5/AD5/ 110 FLMD1 PDL5/AD5/ 110 FLMD1 PDL5/AD5/ 110 FLMD1 HS Input Handshake signal for CSI00 + HS communication RESERVE /HS PCM0/ WAITNote 2 85 Not needed Not needed Not needed Not needed VDD - VDD voltage generation/voltage monitor VDD VDD BVDD EVDD AVREF0 AVREF1 9 104 34 1 5 11 2 103 33 VDD BVDD EVDD AVREF0 AVREF1 VSS AVSS BVSS EVSS 9 104 34 1 5 11 2 69 33 VDD BVDD EVDD AVREF0 AVREF1 VSS AVSS BVSS EVSS 9 104 34 1 5 11 2 69 33 GND - Ground GND VSS AVSS BVSS EVSS Notes 1. When using the clock out of the flash programmer, connect CLK of the programmer to X1, and connect its inverse signal to X2. 2. The pin differs when it is used in a two-power flash memory. Cautions 1. Be sure to connect the REGC pin in either of the following ways. * Connect to GND via a 10 F capacitor * Directly connect to VDD 2. When connecting the REGC pin to GND via a 10 F capacitor, the clock cannot be supplied from the CLK pin of the flash programmer. Supply the clock by creating an oscillator on the board. User's Manual U16889EJ1V0UD 691 CHAPTER 26 FLASH MEMORY (SINGLE POWER) Figure 26-6. Wiring Example of V850ES/KJ1 Flash Writing Adapter (FA-144GJ-UEN) (1/2) VD D G N D D VD D N G 104103 85 110 Note 1 PD70F3217H, PD70F3217HY, PD70F3218H, PD70F3218HY Connect to GND. Connect to VDD. Note 2 12 G N D VD D G 5 8 9 10 11 12 13 14 22 23 24 33 34 N D VD D RFU-3 RFU-2 RFU-1 VDE FLMD1Note 3 FLMD0 SI SO SCK X1 X2 /RESET VPP RESERVE/HSNote 4 692 User's Manual U16889EJ1V0UD CHAPTER 26 FLASH MEMORY (SINGLE POWER) Figure 26-6. Wiring Example of V850ES/KJ1 Flash Writing Adapter (FA-144GJ-UEN) (2/2) Notes 1. Wire the FLMD1 pin as shown in the figure, or connect it to GND on board via a pull-down resistor. 2. Be sure to connect the REGC pin in either of the following ways. * Connect to GND via a 10 F capacitor. * Directly connect to VDD. When connecting the REGC pin to GND via a 10 F capacitor, the clock cannot be supplied from the CLK pin of the flash programmer. Supply the clock by creating an oscillator on the board. 3. Unlike a two-power flash memory, a flash programming mode setting pin is required in a singlepower flash memory. 4. The pin differs when it is used in a two-power flash memory. Remarks 1. Handle the pins not described above in accordance with the specified handling of unused pins (refer to 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins). When connecting to VDD via a resistor, use of a resistor of 1 k to 10 k is recommended. 2. This adapter is for a 144-pin plastic LQFP (fine pitch) package. 3. This diagram shows the wiring when using a handshake-supporting CSI. User's Manual U16889EJ1V0UD 693 CHAPTER 26 FLASH MEMORY (SINGLE POWER) 26.4.3 Flash memory control The following shows the procedure for manipulating the flash memory. Figure 26-7. Procedure for Manipulating Flash Memory Start Supplies FLMD0 pulse Switch to flash memory programming mode Select communication system Manipulate flash memory End? Yes End No 694 User's Manual U16889EJ1V0UD CHAPTER 26 FLASH MEMORY (SINGLE POWER) 26.4.4 Selection of communication mode In the V850ES/KJ1, the communication mode is selected by inputting pulses (12 pulses max.) to the FLMD0 pin after switching to the flash memory programming mode. The FLMD0 pulse is generated by the dedicated flash programmer. The following shows the relationship between the number of pulses and the communication mode. Figure 26-8. Selection of Communication Mode VDD VDD VSS VDD RESET (input) VSS VDD FLMD1 (input) VSS VDD FLMD0 (input) VSS VDD RXD0 (input) VSS VDD TXD0 (output) VSS Oscillation stabilized Power on Reset released Communication mode selected Flash control command communication (erasure, write, etc.) (Note) Note The number of clocks is as follows depending on the communication mode. FLMD0 Pulse 0 8 11 Other Communication Mode UART0 CSI00 CSI00 + HS RFU Remarks Communication rate: 9600 bps (after reset), LSB first V850ES/KJ1 performs slave operation, MSB first V850ES/KJ1 performs slave operation, MSB first Setting prohibited Caution When UART0 is selected, the receive clock is calculated based on the reset command sent from the dedicated flash programmer after receiving the FLMD0 pulse. User's Manual U16889EJ1V0UD 695 CHAPTER 26 FLASH MEMORY (SINGLE POWER) 26.4.5 Communication commands The V850ES/KJ1 communicates with the dedicated flash programmer by means of commands. The signals sent from the dedicated flash programmer to the V850ES/KJ1 are called "commands". The response signals sent from the V850ES/KJ1 to the dedicated flash programmer are called "response commands". Figure 26-9. Communication Commands Command XXXX YYYY Bxxxxx Cxxxxxx XXX YYY PG-FP4 (Flash Pro4) XXXXX STATVE XXXX XXXXXX Axxxx Response command V850ES/KJ1 Dedicated flash programmer The following shows the commands for flash memory control in the V850ES/KJ1. All of these commands are issued from the dedicated flash programmer, and the V850ES/KJ1 performs the processing corresponding to the commands. Table 26-6. Flash Memory Control Commands Classification Command Name CSI00 Blank check Block blank check command Erase Chip erase command Block erase command Support CSI00 + HS UART0 Checks if the contents of the memory in the specified block have been correctly erased. Erases the contents of the entire memory. Erases the contents of the memory of the specified block. Write Write command Writes the specified address range, and executes a contents verify check. Verify Verify command Compares the contents of memory in the specified address range with data transferred from the flash programmer. Checksum command Reads the checksum in the specified address range. System setting, control Silicon signature command Security setting command Disables the chip erase command, enables the block erase command, and disables the write command. Reads silicon signature information. Function 696 User's Manual U16889EJ1V0UD CHAPTER 26 FLASH MEMORY (SINGLE POWER) 26.4.6 Pin connection When performing on-board writing, mount a connector on the target system to connect to the dedicated flash programmer. Also, incorporate a function on-board to switch from the normal operation mode to the flash memory programming mode. In the flash memory programming mode, all the pins not used for flash memory programming become the same status as that immediately after reset. Therefore, pin handling is required when the external device does not acknowledge the status immediately after a reset. (1) FLMD0 pin In the normal operation mode, input a voltage of VSS level to the FLMD0 pin. programming mode, supply a write voltage of VDD level to the FLMD0 pin. Because the FLMD0 pin serves as a write protection pin in the self programming mode, a voltage of VDD level must be supplied to the FLMD0 pin via port control, etc., before writing to the flash memory. For details, refer to 26.5.5 (1) FLMD0 pin. Figure 26-10. FLMD0 Pin Connection Example In the flash memory V850ES/KJ1 Dedicated flash programmer connection pin FLMD0 Pull-down resistor (RFLMD0) User's Manual U16889EJ1V0UD 697 CHAPTER 26 FLASH MEMORY (SINGLE POWER) (2) FLMD1 pin When 0 V is input to the FLMD0 pin, the FLMD1 pin does not function. When VDD is supplied to the FLMD0 pin, the flash memory programming mode is entered, so 0 V must be input to the FLMD1 pin. The following shows an example of the connection of the FLMD1 pin. Figure 26-11. FLMD1 Pin Connection Example V850ES/KJ1 FLMD1 Other device Pull-down resistor (RFLMD1) Caution If the VDD signal is input to the FLMD1 pin from another device during on-board writing and immediately after reset, isolate this signal. Table 26-7. Relationship Between FLMD0 and FLMD1 Pins and Operation Mode When Reset Is Released FLMD0 0 VDD VDD FLMD1 don't care 0 VDD Operation Mode Normal operation mode Flash memory programming mode Setting prohibited 698 User's Manual U16889EJ1V0UD CHAPTER 26 FLASH MEMORY (SINGLE POWER) (3) Serial interface pin The following shows the pins used by each serial interface. Table 26-8. Pins Used by Serial Interfaces Serial Interface UART0 CSI00 CSI00 + HS Pins Used TXD0, RXD0 SO00, SI00, SCK00 SO00, SI00, SCK00, PCM0 When connecting a dedicated flash programmer to a serial interface pin that is connected to another device on-board, care should be taken to avoid conflict of signals and malfunction of the other device. (a) Conflict of signals When the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the other device or set the other device to the output high-impedance status. Figure 26-12. Conflict of Signals (Serial Interface Input Pin) V850ES/KJ1 Conflict of signals Input pin Other device Output pin Dedicated flash programmer connection pins In the flash memory programming mode, the signal that the dedicated flash programmer sends out conflicts with signals another device outputs. Therefore, isolate the signals on the other device side. User's Manual U16889EJ1V0UD 699 CHAPTER 26 FLASH MEMORY (SINGLE POWER) (b) Malfunction of other device When the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), the signal is output to the other device, causing the device to malfunction. To avoid this, isolate the connection to the other device. Figure 26-13. Malfunction of Other Device V850ES/KJ1 Dedicated flash programmer connection pin Pin Other device Input pin In the flash memory programming mode, if the signal the V850ES/KJ1 outputs affects the other device, isolate the signal on the other device side. V850ES/KJ1 Dedicated flash programmer connection pin Pin Other device Input pin In the flash memory programming mode, if the signal the dedicated flash programmer outputs affects the other device, isolate the signal on the other device side. 700 User's Manual U16889EJ1V0UD CHAPTER 26 FLASH MEMORY (SINGLE POWER) (4) RESET pin When the reset signals of the dedicated flash programmer are connected to the RESET pin that is connected to the reset signal generator on-board, a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the reset signal generator. When a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly. Therefore, do not input signals other than the reset signals from the dedicated flash programmer. Figure 26-14. Conflict of Signals (RESET Pin) V850ES/KJ1 Conflict of signals RESET Reset signal generator Output pin Dedicated flash programmer connection pin In the flash memory programming mode, the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs. Therefore, isolate the signals on the reset signal generator side. (5) Port pins (including NMI) When the system shifts to the flash memory programming mode, all the pins that are not used for flash memory programming are in the same status as that immediately after reset. If the external device connected to each port does not recognize the status of the port immediately after reset, pins require appropriate processing, such as connecting to VDD via a resistor or connecting to VSS via a resistor. (6) Other signal pins Connect X1, X2, XT1, XT2, and REGC in the same status as that in the normal operation mode. (7) Power supply Supply the same power (VDD, VSS, EVDD, EVSS, AVSS, BVDD, BVSS, AVREF0, AVREF1) as in normal operation mode. User's Manual U16889EJ1V0UD 701 CHAPTER 26 FLASH MEMORY (SINGLE POWER) 26.5 Rewriting by Self Programming 26.5.1 Overview The V850ES/KJ1 supports a flash macro service that allows the user program to rewrite the internal flash memory by itself. By using this interface and a self programming library that is used to rewrite the flash memory with a user application program, the flash memory can be rewritten by a user application transferred in advance to the internal RAM or external memory. Consequently, the user program can be upgraded and constant data can be rewritten in the field. Figure 26-15. Concept of Self Programming Application program Self programming library Flash function execution Flash information Flash macro service Erase, write Flash memory 702 User's Manual U16889EJ1V0UD CHAPTER 26 FLASH MEMORY (SINGLE POWER) 26.5.2 Features (1) Secure self programming (boot swap function) The V850ES/KJ1 supports a boot swap function that can exchange the physical memory (blocks 0 to 3) of boot area 0 with the physical memory (blocks 4 to 7) of boot area 1. By writing the start program to be rewritten to boot area 1 in advance and then swapping the physical memory, the entire area can be safely rewritten even if a power failure occurs during rewriting because the correct user program always exists in boot area 0. Figure 26-16. Rewriting Entire Memory Area (Boot Swap) Block N Block N Block N Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1 Block 0 Rewriting boot areas 0 and 1 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1 Block 0 Boot swap Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1 Block 0 Remark 256 KB products: N = 127 128 KB products: N = 63 (2) Interrupt support Instructions cannot be fetched from the flash memory during self programming. Conventionally, therefore, a user handler written to the flash memory could not be used even if an interrupt occurred. interrupt servicing can be performed by internal RAM or external memory execution. With the V850ES/KJ1, a user handler can be registered to an entry RAM area by using a library function, so that User's Manual U16889EJ1V0UD 703 CHAPTER 26 FLASH MEMORY (SINGLE POWER) 26.5.3 Standard self programming flow The entire processing to rewrite the flash memory by flash self programming is illustrated below. Figure 26-17. Standard Self Programming Flow Flash memory manipulation Flash environment initialization processing * Disable accessing flash area * Disable setting of STOP mode * Disable stopping clock Erase processing Write processing Flash information setting processingNote 1 Internal verify processing All blocks end? Yes Boot area swapping processingNote 2 No Flash environment end processing End of processing Notes 1. If a security setting is not performed, flash information setting processing does not have to be executed. 2. If boot swap is not used, flash information setting processing and boot area swap processing do not have to be executed. 704 User's Manual U16889EJ1V0UD CHAPTER 26 FLASH MEMORY (SINGLE POWER) 26.5.4 Flash functions Table 26-9. Flash Function List Function Name FlashEnv FlashBlockErase FlashWordWrite FlashBlockIVerify FlashBlockBlankCheck FlashFLMDCheck FlashGetInfo FlashSetInfo FlashBootSwap FlashWordRead Outline Initialization of flash control macro Erasure of only specified one block Writing from specified address Internal verification of specified block Blank check of specified block Check of FLMD pin Reading of flash information Setting of flash information Swapping of boot area Reading data from specified address Support 26.5.5 Pin processing (1) FLMD0 pin The FLMD0 pin is used to set the operation mode when reset is released and to protect the flash memory from being written during self rewriting. It is therefore necessary to keep the voltage applied to the FLMD0 pin at 0 V when reset is released and a normal operation is executed. It is also necessary to apply a voltage of VDD level to the FLMD0 pin during the self programming mode period via port control before the memory is rewritten. When self programming has been completed, the voltage on the FLMD0 pin must be returned to 0 V. Figure 26-18. Mode Change Timing RESET signal VDD 0V Self programming mode VDD FLMD0 pin 0V Normal operation mode Normal operation mode Caution Make sure that the FLMD0 pin is at 0 V when reset is released. User's Manual U16889EJ1V0UD 705 CHAPTER 26 FLASH MEMORY (SINGLE POWER) 26.5.6 Internal resources used The following table lists the internal resources used for self programming. These internal resources can also be used freely for purposes other than self programming. Table 26-10. Internal Resources Used Resource Name Entry RAM area (internal RAM/external RAM size Note Note Description Routines and parameters used for the flash macro service are located in this area. The ) entry program and default parameters are copied by calling a library initialization function. An extension of the stack used by the user is used by the library (can be used in both the internal RAM and external RAM). Stack area (stack size ) Library code (code size Note ) Program entity of library (can be used anywhere other than the flash memory block to be manipulated). Application program Executed as user application. Calls flash functions. Maskable interrupt Can be used in user application execution status or self programming status. To use this interrupt in the self programming status, the interrupt servicing start address must be registered in advance by a registration function. NMI interrupt Can be used in user application execution status or self programming status. To use this interrupt in the self programming status the interrupt servicing start address must be registered in advance by a registration function. Note For the capacity to be used, refer to the V850 Series Flash Memory Self Programming (Single Power Supply Flash Memory) User's Manual (under preparation). 706 User's Manual U16889EJ1V0UD CHAPTER 27 FLASH MEMORY (TWO POWER) The following products are the on-chip flash memory versions (two power) of the V850ES/KJ1. Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing and application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluation for the commercial samples (not engineering samples) of the mask ROM version. For the electrical specifications related to the flash memory rewriting, refer to CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWOPOWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS). * PD70F3217, 70F3217Y: Products with 128 KB flash memory When an instruction is fetched from this flash memory, 4 bytes can be accessed with 1 clock, in the same manner as the mask ROM versions. Data can be written to the flash memory with the flash memory mounted on the target system (on-board). Connect a dedicated flash programmer to the target system to write the flash memory. The following are the assumed environments and applications of flash memory. Changing software after soldering the V850ES/KJ1 onto the target system Producing many variations of a product in small quantities by changing the software Adjusting data when mass production is started 27.1 Features * 4-byte/1-clock access (during instruction fetch access) * Erasing all areas at once * Communication with dedicated flash programmer via serial interface * Erase/write voltage: VPP = 10 V * On-board programming Remark For the differences between a two-power flash memory and single-power flash memory, refer to Caution in 26.1 Features. User's Manual U16889EJ1V0UD 707 CHAPTER 27 FLASH MEMORY (TWO POWER) 27.2 Writing with Flash Programmer Data can be written to the flash memory on-board or off-board, by using a dedicated flash programmer. (1) On-board programming The contents of the flash memory can be rewritten after the V850ES/KJ1 has been mounted on the target system. The connectors that connect the dedicated flash programmer must be mounted on the target system. (2) Off-board programming Data can be written to the flash memory with a dedicated program adapter (FA series) before the V850ES/KJ1 is mounted on the target system. Remark The FA series is a product of Naito Densei Machida Mfg. Co., Ltd. 708 User's Manual U16889EJ1V0UD CHAPTER 27 FLASH MEMORY (TWO POWER) Table 27-1. Wiring Between PD70F3217 and 70F3217Y, and PG-FP4 Pin Configuration of Flash Programmer (PG-FP4) Signal Name SI/RXD SO/TXD SCK CLK I/O Input Output Output Output Pin Function Receive signal Transmit signal Transfer clock Clock to V850ES/KJ1 Pin Name on FA Board SI SO SCK X1 X2 /RESET VPP HS Output Output Input Reset signal Write voltage Handshake signal for CSI00 + HS communication VDD I/O VDD voltage generation/voltage monitor EVDD AVREF0 AVREF1 GND - Ground GND VSS AVSS BVSS EVSS 34 1 5 11 2 103 33 EVDD AVREF0 AVREF1 VSS AVSS BVSS EVSS 34 1 5 11 2 69 33 EVDD AVREF0 AVREF1 VSS AVSS BVSS EVSS 34 1 5 11 2 69 33 VDD VDD BVDD 9 104 VDD BVDD 9 104 VDD BVDD 9 104 /RESET VPP RESERVE /HS With CSI00-HS Pin Name P41/SO00 P40/SI00 Pin No. 23 22 With CSI00 Pin Name P41/SO00 P40/SI00 Pin No. 23 22 With UART0 Pin Name P30/TXD0 P31/RXD0 Pin No. 25 26 P42/SCK00 24 X1 X2 Note 1 P42/SCK00 24 X1 X2 Note 1 Not needed Not needed X1 X2 Note 1 12 13 14 8 82 12 13 14 8 12 13 14 8 RESET VPP PCS1/ CS1Note 2 RESET VPP RESET VPP Not needed Not needed Not needed Not needed Notes 1. When using the clock out of the flash programmer, connect CLK of the programmer to X1, and connect its inverse signal to X2. 2. The pin differs when it is used in a single-power flash memory. Cautions 1. Be sure to connect the REGC pin in either of the following ways. * Connect to GND via a 10 F capacitor * Directly connect to VDD 2. When connecting the REGC pin to GND via a 10 F capacitor, the clock cannot be supplied from the CLK pin of the flash programmer. Supply the clock by creating an oscillator on the board. User's Manual U16889EJ1V0UD 709 CHAPTER 27 FLASH MEMORY (TWO POWER) Figure 27-1. Wiring Example of V850ES/KJ1 Flash Writing Adapter (FA-144GJ-UEN) VD D D N G D VD D N G 104103 82 PD70F3217, PD70F3217Y Connect to GND. Connect to VDD. Note 1 12 G N D G 5 8 9 10 11 12 13 14 22 23 24 33 34 N D VD D Notes 1. Be sure to connect the REGC pin in either of the following ways. * Connect to GND via a 10 F capacitor. * Directly connect to VDD. When connecting the REGC pin to GND via a 10 F capacitor, the clock cannot be supplied from the CLK pin of the flash programmer. Supply the clock by creating an oscillator on the board. 2. The pin differs when it is used in a single-power flash memory. Remarks 1. Handle the pins not described above in accordance with the specified handling of unused pins (refer to 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins). When connecting to VDD via a resistor, use of a resistor of 1 k to 10 k is recommended. 2. This adapter is for a 144-pin plastic LQFP (fine pitch) package. 3. This diagram shows the wiring when using a handshake-supporting CSI. VD D SI SO SCK X1 X2 /RESET VPP RESERVE/HSNote 2 710 User's Manual U16889EJ1V0UD CHAPTER 27 FLASH MEMORY (TWO POWER) 27.3 Programming Environment The environment required for writing a program to the flash memory of the V850ES/KJ1 is illustrated below. Figure 27-2. Environment for Writing Program to Flash Memory VPP XXXX YYYY Bxxxxx Cxxxxxx XXXX XXXXXX RS-232-C USB Axxxx VDD PG-FP4 (Flash Pro4) XXXXX XXX YYY STATVE VSS RESET V850ES/KJ1 Dedicated flash programmer Host machine UART0/CSI00 A host machine that controls the dedicated flash programmer is necessary. To interface between the flash programmer and the V850ES/KJ1, UART0 or CSI00 is used for manipulation such as writing and erasing. To write the flash memory off-board, a dedicated program adapter (FA series) is necessary. 27.4 Communication Mode Communication between the dedicated flash programmer and the V850ES/KJ1 is established by serial communication via UART0 or CSI00 of the V850ES/KJ1. (1) UART0 Transfer rate: 9600 to 153600 bps (LSB first) Figure 27-3. Communication with Dedicated Flash Programmer (UART0) VPP VDD XXXX YYYY VPP VDD VSS RESET RXD0 TXD0 X1 X2 V850ES/KJ1 Bxxxxx Cxxxxxx XXX YYY PG-FP4 (Flash Pro4) XXXXX STATVE XXXX XXXXXX Axxxx GND RESET Dedicated flash programmer TXD RXD CLK User's Manual U16889EJ1V0UD 711 CHAPTER 27 FLASH MEMORY (TWO POWER) (2) CSI00 Transfer rate: 2.4 kHz to 2.5 MHz (MSB first) Figure 27-4. Communication with Dedicated Flash Programmer (CSI00) VPP VDD XXXX YYYY VPP VDD VSS RESET SO00 SI00 SCK00 X1 X2 V850ES/KJ1 Bxxxxx Cxxxxxx XXXX XXXXXX Axxxx GND RESET SI XXX YYY PG-FP4 (Flash Pro4) XXXXX STATVE Dedicated flash programmer SO SCK CLK (3) CSI communication mode supporting handshake Transfer rate: 2.4 kHz to 2.5 MHz (MSB first) Figure 27-5. Communication with Flash Programmer (CSI00 + H/S) VPP VDD XXXX YYYY VPP VDD VSS RESET SO00 SI00 SCK00 X1 X2 PCS1 V850ES/KJ1 Bxxxxx Cxxxxxx XXXX XXXXXX Axxxx GND PG-FP4 (Flash Pro4) XXXXX XXX YYY STATVE RESET SI Dedicated flash programmer SO SCK CLK H/S 712 User's Manual U16889EJ1V0UD CHAPTER 27 FLASH MEMORY (TWO POWER) If the PG-FP4 is used as the flash programmer, the PG-FP4 generates the following signals for the V850ES/KJ1. For details, refer to the PG-FP4 User's Manual (U15260E). Table 27-2. Signals Generated by Dedicated Flash Programmer (PG-FP4) PG-FP4 Signal Name VPP VDD Note 1 V850ES/KJ1 Pin Function Pin Name VPP VDD VSS X1, X2 Note 2 Connection CSI00 UART0 I/O Output I/O - Output Output Input Output Output Input Write voltage VDD voltage generation Ground Clock output to V850ES/KJ1 Reset signal Receive signal Transmit signal Transfer clock Handshake signal of CSI00 + HS communication GND CLK RESET SI/RxD SO/TxD SCK H/S RESET SO00/TXD0 SI00/RXD0 SCK00 PCS1 x x Notes 1. The PG-FP3 has a VDD voltage monitoring function. 2. For off-board writing only: connect the clock output of the flash programmer to X1 and its inverse signal to X2. Remark : Be sure to connect the pin. : The pin does not have to be connected if the signal is generated on the target board. x: The pin does not have to be connected. : In handshake mode User's Manual U16889EJ1V0UD 713 CHAPTER 27 FLASH MEMORY (TWO POWER) 27.5 Pin Processing To write the flash memory on-board, connectors that connect the flash programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board. When the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after reset. Therefore, if the external device does not recognize the state immediately after reset, the pins must be processed as described below. 27.5.1 VPP pin In the normal operation mode, connect the VPP pin to VSS. In the flash memory programming mode, a write voltage of 10 V is supplied to the VPP pin. An example of connection of the VPP pin is illustrated below. Figure 27-6. Example of Connection of VPP Pin V850ES/KJ1 Flash programmer connection pin VPP Pull-down resistor (RVPP) 714 User's Manual U16889EJ1V0UD CHAPTER 27 FLASH MEMORY (TWO POWER) 27.5.2 Serial interface pins The pins used by each serial interface are listed below. Table 27-3. Pins Used by Each Serial Interface Serial Interface CSI00 CSI00 + HS UART0 Pins Used SO00, SI00, SCK00 SO00, SI00, SCK00, PCS1 TXD0, RXD0 To connect the dedicated flash programmer to the pins of a serial interface that is connected to another device on the board, care must be exercised so that signals do not collide or that the other device does not malfunction. (1) Signal collision If the flash programmer (output) is connected to a pin (input) of a serial interface connected to another device (output), signal collision takes place. To avoid this collision, either isolate the connection with the other device, or make the other device go into an output high-impedance state. Figure 27-7. Signal Collision (Input Pin of Serial Interface) V850ES/KJ1 Signal collision Input pin Flash programmer connection pin Other device Output pin In the flash memory programming mode, the signal output by the device collides with the signal sent from the flash programmer. Therefore, isolate the signal of the other device. User's Manual U16889EJ1V0UD 715 CHAPTER 27 FLASH MEMORY (TWO POWER) (2) Malfunction of other device If the dedicated flash programmer (output or input) is connected to a pin (input or output) of a serial interface connected to another device (input), a signal may be output to the other device, causing the device to malfunction. To avoid this malfunction, isolate the connection with the other device. Figure 27-8. Malfunction of Other Device V850ES/KJ1 Flash programmer connection pin Other device Input pin Pin If the signal output by the V850ES/KJ1 in the flash memory programming mode affects the other device, isolate the signal of the other device. V850ES/KJ1 Flash programmer connection pin Other device Input pin Pin If the signal output by the flash programmer in the flash memory programming mode affects the other device, isolate the signal of the other device. 716 User's Manual U16889EJ1V0UD CHAPTER 27 FLASH MEMORY (TWO POWER) 27.5.3 RESET pin If the reset signal of the flash programmer is connected to the RESET pin that is connected to the reset signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the reset signal generator. If the reset signal is input from the user system while the flash memory programming mode is set, the flash memory will not be correctly programmed. Do not input any signal other than the reset signal of the flash programmer. Figure 27-9. Signal Collision (RESET Pin) V850ES/KJ1 Signal collision RESET Flash programmer connection signal Reset signal generator Output pin In the flash memory programming mode, the signal output by the reset signal generator collides with the signal output by the flash programmer. Therefore, isolate the signal of the reset signal generator. 27.5.4 Port pins When the system shifts to the flash memory programming mode, all the pins that are not used for flash memory programming are in the same status as that immediately after reset. If the external device connected to each port does not recognize the status of the port immediately after reset, pins require appropriate processing, such as connecting to VDD via a resistor or connecting to VSS via a resistor. 27.5.5 Other signal pins Connect the X1, X2, XT1, XT2, and REGC pins in the same status as in the normal operation mode. To input the operating clock from the programmer, however, connect the clock out of the programmer to X1, and its inverse signal to X2. 27.5.6 Power supply Supply the same power as in the normal operation mode for the power supply (VDD, VSS, AVREF0, AVREF1, AVSS, BVDD, BVSS, EVDD, and EVSS). Caution VDD of the flash programmer (PG-FP3) has a power monitor function. Be sure to connect VDD and VSS to VDD and GND of the flash programmer. User's Manual U16889EJ1V0UD 717 CHAPTER 27 FLASH MEMORY (TWO POWER) 27.6 Programming Method 27.6.1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory. Figure 27-10. Flash Memory Manipulation Procedure Start VPP pulse supply Flash memory programming mode is set Selecting communication mode Manipulate flash memory End? Yes End No 718 User's Manual U16889EJ1V0UD CHAPTER 27 FLASH MEMORY (TWO POWER) 27.6.2 Flash memory programming mode To rewrite the contents of the flash memory by using the dedicated flash programmer, set the V850ES/KJ1 in the flash memory programming mode. To set the mode, set the VPP pin and clear the reset signal. Change the mode by using a jumper when writing the flash memory on-board. Figure 27-11. Flash Memory Programming Mode Flash memory programming mode 10 V VPP VDD VSS RESET 1 2 *** n VPP VSS 10 V Normal operation mode Operation mode Flash memory programming mode 27.6.3 Selecting communication mode In the V850ES/KJ1 a communication mode is selected by inputting pulses (up to 8 pulses) to the VPP pin after the flash memory programming mode is entered. These VPP pulses are generated by the flash programmer. The following table shows the relationship between the number of pulses and communication modes. Table 27-4. Communication Modes VPP Pulse 0 3 8 Other Communication Mode CSI00 CSI00 + HS UART0 RFU Remark V850ES/KJ1 operates as slave with MSB first. V850ES/KJ1 operates as slave with MSB first. Communication rate: 9600 bps (after reset), LSB first Setting prohibited Caution When UART0 is selected, the receive clock is calculated based on the reset command sent from the dedicated flash programmer after the VPP pulse has been received. User's Manual U16889EJ1V0UD 719 CHAPTER 27 FLASH MEMORY (TWO POWER) 27.6.4 Communication commands The V850ES/KJ1 communicates with the flash programmer by using commands. The signals sent from the flash programmer to the V850ES/KJ1 are called "commands", and the commands sent from the V850ES/KJ1 to the flash programmer are called "response commands". Figure 27-12. Communication Commands Command XXXX YYYY Bxxxxx Cxxxxxx XXX YYY PG-FP4 (Flash Pro4) XXXXX STATVE XXXX XXXXXX Axxxx Response command V850ES/KJ1 Flash programmer The flash memory control commands of the V850ES/KJ1 are listed in the table below. All these commands are issued from the programmer and the V850ES/KJ1 performs processing corresponding to the respective commands. Table 27-5. Flash Memory Control Commands Classification Verify Command Name Batch verify command Function Compares the contents of the entire memory with the input data. Erase Blank check Data write Batch erase command Batch blank check command High-speed write command Erases the contents of the entire memory. Checks the erasure status of the entire memory. Writes data by specifying the write address and number of bytes to be written, and executes a verify check. Successive write command Writes data from the address following that of the high-speed write command executed immediately before, and executes a verify check. System setting, control Status read command Oscillation frequency setting command Erase time setting command Write time setting command Baud rate setting command Silicon signature command Reset command Obtains the operation status Sets the oscillation frequency Sets the erase time for batch erase Sets the write time for writing data Sets the baud rate when UART is used Reads the silicon signature information Escapes from each status The V850ES/KJ1 returns a response command for the command issued by the dedicated flash programmer. The response commands sent from the V850ES/KJ1 are listed below. Table 27-6. Response Commands Command Name ACK NAK Function Acknowledges command/data. Acknowledges illegal command/data. 720 User's Manual U16889EJ1V0UD CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) Single-power flash memory versions are as follows. PD70F3217H, 70F3217HY, 70F3218H, 70F3218HY Absolute Maximum Ratings (TA = 25C) (1/2) Parameter Supply voltage Symbol VDD BVDD EVDD AVREF0 AVREF1 Conditions VDD = EVDD = AVREF0 BVDD VDD VDD = EVDD = AVREF0 VDD = EVDD = AVREF0 AVREF1 VDD (D/A output mode) AVREF1 = AVREF0 = VDD (port mode) VSS AVSS BVSS EVSS Input voltage VI1 VSS = EVSS = BVSS = AVSS VSS = EVSS = BVSS = AVSS VSS = EVSS = BVSS = AVSS VSS = EVSS = BVSS = AVSS P00 to P06, P30 to P35, P38, P39, P40 to P42, P50 to P55, P60 to P613, P80, P81, P90 to P915, RESET, FLMD0 VI2 PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7, PDL0 to PDL15, PDH0 to PDH7 VI3 VI4 VI5 Analog input voltage VIAN P10, P11 P36, P37, P614, P615 X1, X2, XT1, XT2 P70 to P715 -0.3 to AVREF1 + 0.3 -0.3 to +13 Note Note Ratings -0.3 to +6.5 -0.3 to VDD + 0.3 -0.3 to +6.5 -0.3 to +6.5 -0.3 to VDD + 0.3 -0.3 to +0.3 -0.3 to +0.3 -0.3 to +0.3 -0.3 to +0.3 -0.3 to EVDD + 0.3 Note Note Note Unit V V V V V V V V V V -0.3 to BVDD + 0.3 Note V V V -0.3 to VDD + 0.3 Note V V -0.3 to AVREF0 + 0.3 Note Note Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage. User's Manual U16889EJ1V0UD 721 CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) Absolute Maximum Ratings (TA = 25C) (2/2) Parameter Output current, low Symbol IOL Conditions P00 to P06, P10, P11, P30 to P35, P40 to P42, P50 to P55, P60 to P613, P80, P81, P90 to P915, PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7, PDL0 to PDL15, PDH0 to PDH7 P36 to P39, P614, P615 P00 to P06, P30 to P39, P40 to P42 P50 to P55, P60 to P615, P80, P81, P90 to P915 PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7 PDL0 to PDL15, PDH0 to PDH7 Output current, high IOH Per pin P00 to P06, P30 to P35, P40 to P42 P50 to P55, P60 to P613, P80, P81, P90 to P915 PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7 PDL0 to PDL15, PDH0 to PDH7 Operating ambient temperature Storage temperature TA Normal operation mode Flash programming mode Tstg Total of all pins: -60 mA Total of all pins: -60 mA Total of all pins: 70 mA Total of all pins: 70 mA Per pin Ratings 20 Unit mA 30 35 35 35 35 -10 -30 -30 -30 -30 -40 to +85 T.B.D. -40 to +125 mA mA mA mA mA mA mA mA mA mA C C C Cautions 1. Do not directly connect the output (or I/O) pins of IC products to each other, or to VDD, VCC, and GND. Open-drain pins or open-collector pins, however, can be directly connected to each other. Direct connection of the output pins between an IC product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Capacitance (TA = 25C, VDD = EVDD = AVREF0 = BVDD = AVREF1 = VSS = EVSS = BVSS = AVSS = 0 V) Parameter Input capacitance I/O capacitance Symbol CI CIO Conditions fX = 1 MHz Unmeasured pins returned to 0 V P70 to P715 Note P36 to P39, P614, P615 MIN. TYP. MAX. 15 15 20 Unit pF pF pF Note P00 to P06, P10, P11, P30 to P35, P40 to P42, P50 to P55, P60 to P613, P80, P81, P90 to P915, PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7, PDL0 to PDL15, PDH0 to PDH7 Remark fX: Main clock oscillation frequency 722 User's Manual U16889EJ1V0UD CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) Operating Conditions (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Internal system clock frequency Symbol fCLK In PLL mode Conditions REGC = VDD = 4.5 to 5.5 V REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V REGC = VDD = 2.7 to 5.5 V In clock-through mode REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V REGC = VDD = 2.7 to 5.5 V Operating with subclock REGC = VDD = 2.7 to 5.5 V 0.0625 32.768 8 Note MIN. 0.25 0.25 0.25 TYP. MAX. 20 16 8 Note Unit MHz MHz MHz 0.25 0.0625 0.0625 8 Note MHz MHz MHz 10 8 Note MHz kHz Note These values may change after evaluation. Internal System Clock Frequency vs. Supply Voltage 100 When REGC = Capacity Internal system clock frequency fCLK [MHz] 20.0 16.0 10.0 1.0 0.1 0.032 0.01 2.0 3.0 4.0 Supply voltage VDD [V] 5.0 6.0 User's Manual U16889EJ1V0UD 723 CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) Main Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V, VSS = 0 V) Resonator Ceramic resonator X1 X2 Recommended Circuit Parameter Oscillation frequency (fX) Note 1 Conditions In PLL mode REGC = VDD = 4.5 to 5.5 V REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V REGC = VDD = 2.7 to 5.5 V Note 3 REGC = VDD = 2.7 to 5.5 V MIN. 2 2 2 TYP. MAX. 5 4 4 Unit MHz MHz MHz 2 2 2 /fX Note 4 2 2 2 15 2.5 10 MHz MHz s s Oscillation stabilization time Crystal resonator X1 X2 Note 2 After reset is released After STOP mode is released In PLL mode REGC = VDD = 4.5 to 5.5 V REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V REGC = VDD = 2.7 to 5.5 V Note 3 REGC = VDD = 2.7 to 5.5 V 2 2 Oscillation frequency (fX) Note 1 5 4 4 MHz MHz MHz 2.5 10 2 /fX Note 4 15 MHz MHz s s Oscillation stabilization time External clock X1 X2 Note 2 After reset is released After STOP mode is released REGC = VDD = 4.5 to 5.5 V REGC = VDD = 4.0 to 5.5 V REGC = VDD = 2.7 to 5.5 V Note 3 REGC = VDD = 2.7 to 5.5 V 2 2 2 2 X1, X2 input In PLL mode frequency (fX) 5 4 2.5 10 MHz MHz MHz MHz External clock Notes 1. Indicates only oscillator characteristics. 2. Time required to stabilize the resonator after reset or STOP mode is released. 3. In clock-through mode 4. The value differs depending on the OSTS register settings. Cautions 1. When using the main clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main clock is stopped and the device is operating on the subclock, wait until the oscillation stabilization time has been secured by the program before switching back to the main clock. 724 User's Manual U16889EJ1V0UD CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) Subclock Oscillator Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V, VSS = 0 V) Resonator Crystal resonator XT1 XT2 Recommended Circuit Parameter Oscillation frequency (fXT) Note 1 Conditions MIN. 32 TYP. 32.768 MAX. 35 Unit kHz Oscillation stabilization time Note 2 10 s External clock XT1 XT2 XT1 input frequency (fXT) Note 1 REGC = VDD 32 35 kHz Duty = 50% 5% External clock Notes 1. Indicates only oscillator characteristics. 2. Time required from when VDD reaches oscillation voltage range (2.7 V (MIN.)) to when the crystal resonator stabilizes. Cautions 1. When using the subclock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subclock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the main clock oscillator. Particular care is therefore required with the wiring method when the subclock is used. PLL Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V, VSS = 0 V) Parameter Input frequency Output frequency Lock time Symbol fX fXX tPLL After VDD reaches 2.7 V (MIN.) Conditions MIN. 2 8 TYP. MAX. 5 20 200 Unit MHz MHz s User's Manual U16889EJ1V0UD 725 CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) DC Characteristics (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) (1/5) Parameter Output current, high Symbol IOH1 Conditions Per pin for P00 to P06, P10, P11, P30 to P35, P40 to P42, P50 to P55, P60 to P613, P80, P81, P90 to P915 Total of P00 to P06, P30 to P35, P40 to P42 Total of P50 to P55, P60 to P613, P80, P81, P90 to P915 IOH2 EVDD = 4.0 to 5.5 V EVDD = 2.7 to 5.5 V EVDD = 4.0 to 5.5 V EVDD = 2.7 to 5.5 V -30 -15 -30 -15 -5.0 -30 -15 -30 -15 10 mA mA mA mA mA MAX. -5.0 Unit mA Per pin for PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7, PDH0 to PDH7, PDL0 to PDL15 Total of PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7 Total of PDL0 to PDL15, PDH0 to PDH7 BVDD = 4.0 to 5.5 V BVDD = 2.7 to 5.5 V BVDD = 4.0 to 5.5 V BVDD = 2.7 to 5.5 V mA mA mA mA mA Output current, low IOL1 Per pin for P00 to P06, P10, P11, P30 to P35, P40 to P42, P50 to P55, P60 to P613, P80, P81, P90 to P915 Per pin for P36 to P39 EVDD = 4.0 to 5.5 V EVDD = 2.7 to 5.5 V Per pin for P614, P615 EVDD = 4.0 to 5.5 V EVDD = 2.7 to 5.5 V Total of P00 to P06, P30 to P37, P40 to P42 Total of P38, P39, P50 to P55, P60 to P615, P80, P81, P90 to P915 15 8 10 5 30 30 mA mA mA mA mA mA IOL2 Per pin for PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7, PDH0 to PDH7, PDL0 to PDL15 Total of PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7 Total of PDL0 to PDL15, PDH0 to PDH7 10 mA 30 mA 30 mA 726 User's Manual U16889EJ1V0UD CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) DC Characteristics (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) (2/5) Parameter Input voltage, high Symbol VIH1 VIH2 VIH3 VIH4 VIH5 VIH6 VIH7 Input voltage, low VIL1 VIL2 VIL3 VIL4 VIL5 VIL6 VIL7 Note 1 Note 2 Note 3 P70 to P715 P10, P11 Note 4 Conditions MIN. 0.7EVDD 0.8EVDD 0.7BVDD 0.7AVREF0 0.7AVREF1 0.7EVDD VDD - 0.5 EVSS EVSS BVSS AVSS AVSS EVSS VSS TYP. MAX. EVDD EVDD BVDD AVREF0 AVREF1 12 VDD 0.3EVDD 0.2EVDD 0.3BVDD 0.3AVREF0 0.3AVREF1 0.3EVDD 0.4 Unit V V V V V V V V V V V V V V P36, P37, P614, P615 X1, X2, XT1, XT2 Note 1 Note 2 Note 3 P70 to P715 P10, P11 Note 4 P36, P37, P614, P615 X1, X2, XT1, XT2 Notes 1. P00, P01, P30, P41, P60 to P65, P67, P611, P98, P911 and their alternate-function pins. 2. RESET, P02 to P06, P31 to P35, P38, P39, P40, P42, P50 to P55, P66, P68 to P610, P612, P613, P80, P81, P90 to P97, P99, P910, P912 to P915 and their alternate-function pins. 3. PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7, PDL0 to PDL15, PDH0 to PDH7 and their alternate-function pins. 4. When used as port pins, set AVREF1 = AVREF0 = VDD. User's Manual U16889EJ1V0UD 727 CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) DC Characteristics (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) (3/5) Parameter Output voltage, high Symbol VOH1 Note 1 Conditions IOH = -2.0 mA, EVDD = 4.0 to 5.5 V Note 2 IOH = -0.1 mA, EVDD = 2.7 to 5.5 V VOH2 Note 3 IOH = -2.0 mA, BVDD = 4.0 to 5.5 V Note 4 Note 5 MIN. EVDD - 1.0 EVDD - 0.5 BVDD - 1.0 BVDD - 0.5 AVREF1 - 1.0 AVREF1 - 0.5 0 0 0 0 TYP. MAX. EVDD Unit V EVDD V BVDD V IOH = -0.1 mA, BVDD = 2.7 to 5.5 V IOH = -2.0 mA IOH = -0.1 mA BVDD V VOH3 P10, P11 AVREF1 AVREF1 0.8 0.8 0.8 2.0 V V V V V V Output voltage, low VOL1 VOL2 VOL3 VOL4 Note 6 Note 8 P10, P11 Note 5 IOL = 2.0 mA IOL = 2.0 mA IOL = 2.0 mA IOL = 15 mA, Note 7 P36 to P39 EVDD = 4.0 to 5.5 V IOL = 8 mA, EVDD = 3.0 to 5.5 V IOL = 5 mA, EVDD = 2.7 to 5.5 V VOL5 P614, P615 IOL = 10 mA, EVDD = 4.0 to 5.5 V IOL = 5 mA, EVDD = 2.7 to 5.5 V Input leakage current, high Input leakage current, low Output leakage current, high Output leakage current, low Pull-up resistor ILIH ILIL ILOH ILOL RL VIN = VDD VIN = 0 V VO = VDD VO = 0 V VIN = 0 V 10 30 3.0 -3.0 3.0 -3.0 100 0 1.0 V 0 2.0 V 0 1.0 V 0 1.0 V A A A A k Notes 1. Total of P00 to P06, P30 to P35, P40 to P42 and their alternate-function pins: IOH = -30 mA, total of P50 to P55, P60 to P613, P80, P81, P90 to P915 and their alternate-function pins: IOH = -30 mA. 2. Total of P00 to P06, P30 to P35, P40 to P42 and their alternate-function pins: IOH = -15 mA, total of P50 to P55, P60 to P613, P80, P81, P90 to P915 and their alternate-function pins: IOH = -15 mA. 3. Total of PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7: IOH = -30 mA, total of PDH0 to PDH7, PDL0 to PDL15 and their alternate-function pins: IOH = -30 mA. 4. Total of PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7: IOH = -15 mA, total of PDH0 to PDH7, PDL0 to PDL15 and their alternate-function pins: IOH = -15 mA. 5. When used as port pins, set AVREF1 = AVREF0 = VDD. 6. Total of P00 to P06, P30 to P37, P40 to P42 and their alternate-function pins: IOL = 30 mA, total of P38, P39, P50 to P55, P60 to P615, P80, P81, P90 to P915 and their alternate-function pins: IOL = 30 mA. 7. Refer to IOL1 for IOL of P36 to P39, P614, and P615. 8. Total of PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7 and their alternate-function pins: IOL = 30 mA, total of PDH0 to PDH7, PDL0 to PDL15 and their alternate-function pins: IOL = 30 mA. 728 User's Manual U16889EJ1V0UD CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) DC Characteristics (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) (4/5) Parameter Supply current 70F3218HY) Note Symbol IDD1 Normal operation Conditions fXX = 20 MHz (fX = 5 MHz) (in PLL mode) REGC = VDD = 5 V 10% fXX = T.B.D. (in clock-through mode) REGC = VDD = 3 V 10% MIN. TYP. 55 MAX. 75 Unit mA (PD70F3218H, T.B.D. T.B.D. mA IDD2 HALT mode fXX = 20 MHz (fX = 5 MHz) (in PLL mode) REGC = VDD = 5 V 10% fXX = T.B.D. (in clock-through mode) REGC = VDD = 3 V 10% 29 43 mA T.B.D. T.B.D. mA IDD3 IDLE mode fX = 5 MHz (when PLL mode off) REGC = VDD = 5 V 10% fX = T.B.D. (in clock-through mode) REGC = VDD = 3 V 10% 2.1 3.3 mA T.B.D. T.B.D. mA IDD4 Subclock operating mode fXT = 32.768 kHz Main clock stopped 250 420 A IDD5 Subclock IDLE mode fXT = 32.768 kHz Main clock stopped, watch timer operating 20 75 A IDD6 STOP mode Subclock operating Subclock stopped (XT1 = VSS, when PSMR.XTSTP bit = 1) 15 0.1 60 30 A A IDD7 Flash memory erase/write fXX = 20 MHz (fX = 5 MHz) (in PLL mode) REGC = VDD = 5 V 10% fXX = T.B.D. (in clock-through mode) REGC = VDD = 3 V 10% 65 90 mA T.B.D. T.B.D. mA Note Total current of VDD, EVDD, and BVDD (all ports stopped). AVREF0 is not included. Remark fXX: Main clock frequency fX: Main clock oscillation frequency fXT: Subclock frequency User's Manual U16889EJ1V0UD 729 CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) DC Characteristics (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) (5/5) Parameter Supply current 70F3217HY) Note Symbol IDD1 Normal operation Conditions fXX = 20 MHz (fX = 5 MHz) (in PLL mode) REGC = VDD = 5 V 10% fXX = T.B.D. (in clock-through mode) REGC = VDD = 3 V 10% MIN. TYP. 51 MAX. 70 Unit mA (PD70F3217H, T.B.D. T.B.D. mA IDD2 HALT mode fXX = 20 MHz (fX = 5 MHz) (in PLL mode) REGC = VDD = 5 V 10% fXX = T.B.D. (in clock-through mode) REGC = VDD = 3 V 10% 25 38 mA T.B.D. T.B.D. mA IDD3 IDLE mode fX = 5 MHz (when PLL mode off) REGC = VDD = 5 V 10% fX = T.B.D. (in clock-through mode) REGC = VDD = 3 V 10% 1.8 2.9 mA T.B.D. T.B.D. mA IDD4 Subclock operating mode fXT = 32.768 kHz Main clock stopped 240 400 A IDD5 Subclock IDLE mode fXT = 32.768 kHz Main clock stopped, watch timer operating 20 75 A IDD6 STOP mode Subclock operating Subclock stopped (XT1 = VSS, when PSMR.XTSTP bit = 1) 15 0.1 60 30 A A IDD7 Flash memory erase/write fXX = 20 MHz (fX = 5 MHz) (in PLL mode) REGC = VDD = 5 V 10% fXX = T.B.D. (in clock-through mode) REGC = VDD = 3 V 10% 61 85 mA T.B.D. T.B.D. mA Note Total current of VDD, EVDD, and BVDD (all ports stopped). AVREF0 is not included. Remark fXX: Main clock frequency fX: Main clock oscillation frequency fXT: Subclock frequency 730 User's Manual U16889EJ1V0UD CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) Data Retention Characteristics STOP Mode (TA = -40 to +85C) Parameter Data retention voltage STOP release signal input time Symbol VDDDR tDREL Conditions STOP mode MIN. 2.0 0 TYP. MAX. 5.5 Unit V s Caution Shifting to STOP mode and restoring from STOP mode must be performed within the rated operating range. STOP mode setting Operating voltage lower limit VDD STOP release signal input VDDDR tDREL RESET (input) STOP mode release interrupt (NMI, etc.) (Released by falling edge) STOP mode release interrupt (NMI, etc.) (Released by rising edge) User's Manual U16889EJ1V0UD 731 CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) AC Characteristics AC Test Input Measurement Points (VDD, AVREF0, EVDD, BVDD) VDD VIH Measurement points VIH VIL 0V VIL AC Test Output Measurement Points VOH Measurement points VOH VOL VOL Load Conditions DUT (Device under measurement) CL = 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means. 732 User's Manual U16889EJ1V0UD CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) CLKOUT Output Timing (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Output cycle High-level width Symbol tCYK tWKH <1> <2> VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V Low-level width tWKL <3> VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V Rise time tKR <4> VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V Fall time tKF <5> VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V Conditions MIN. 50 ns tCYK/2 - 17 tCYK/2 - 26 tCYK/2 - 17 tCYK/2 - 26 17 26 17 26 MAX. 30.6 s ns ns ns ns ns ns ns ns Unit Clock Timing <1> <2> <3> CLKOUT (output) <4> <5> User's Manual U16889EJ1V0UD 733 CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) Bus Timing (1) In multiplex bus mode (a) Read/write cycle (CLKOUT asynchronous) (TA = -40 to +85C, VDD = EVDD = AVREF0 = 4.0 to 5.5 V, 4.0 V BVDD VDD, 4.0 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (1/2) Parameter Address setup time (to ASTB) Address hold time (from ASTB) Delay time from RD to address float Data input setup time from address Data input setup time from RD Delay time from ASTB to RD, WRm Data input hold time (from RD) Address output time from RD Delay time from RD, WRm to ASTB Delay time from RD to ASTB RD, WRm low-level width ASTB high-level width Data output time from WRm Data output setup time (to WRm) Data output hold time (from WRm) WAIT setup time (to address) tSAST tHSTA tFRDA tSAID tSRID tDSTRDWR tHRDID tDRDA tDRDWRST tDRDST tWRDWRL tWSTH tDWROD tSODWR tHWROD tSAWT1 tSAWT2 WAIT hold time (from address) tHAWT1 tHAWT2 WAIT setup time (to ASTB) tSSTWT1 tSSTWT2 WAIT hold time (from ASTB) tHSTWT1 tHSTWT2 Symbol <6> <7> <8> <9> <10> <11> <12> <13> <14> <15> <16> <17> <18> <19> <20> <21> <22> <23> <24> <25> <26> <27> <28> n1 (n + tAHW)T (1 + n + tAHW)T n1 n1 (0.5 + n + tASW + tAHW)T (1.5 + n + tASW + tAHW)T (1 + tAHW)T - 32 (1 + n + tAHW)T - 32 n1 (1 + n)T - 25 T - 15 (1.5 + tASW + tAHW)T - 45 (1.5 + n + tASW + tAHW)T - 45 (0.5 + tAHW)T - 20 0 (1 + i)T - 16 0.5T - 10 (1.5 + i + tASW)T - 10 (1 + n)T - 10 (1 + tASW)T - 25 20 Conditions MIN. (0.5 + tASW)T - 23 (0.5 + tASW)T - 15 16 (2 + n + tASW + tAHW)T - 40 (1 + n + tASW + tAHW)T - 25 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks 1. tASW: Number of address setup wait clocks tAHW: Number of address hold wait clocks 2. T = 1/fCPU (fCPU: CPU operating clock frequency) 3. n: Number of wait clocks inserted in the bus cycle The sampling timing changes when a programmable wait is inserted. 4. m = 0, 1 5. i: Number of idle states inserted after a read cycle (0 or 1) 6. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. 734 User's Manual U16889EJ1V0UD CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (2/2) Parameter Address setup time (to ASTB) Address hold time (from ASTB) Delay time from RD to address float Data input setup time from address Data input setup time from RD Delay time from ASTB to RD, WRm Data input hold time (from RD) Address output time from RD Delay time from RD, WRm to ASTB Delay time from RD to ASTB RD, WRm low-level width ASTB high-level width Data output time from WRm Data output setup time (to WRm) Data output hold time (from WRm) WAIT setup time (to address) tSAST tHSTA tFRDA tSAID tSRID tDSTRDWR tHRDID tDRDA tDRDWRST tDRDST tWRDWRL tWSTH tDWROD tSODWR tHWROD tSAWT1 tSAWT2 WAIT hold time (from address) tHAWT1 tHAWT2 WAIT setup time (to ASTB) tSSTWT1 tSSTWT2 WAIT hold time (from ASTB) tHSTWT1 tHSTWT2 Symbol <6> <7> <8> <9> <10> <11> <12> <13> <14> <15> <16> <17> <18> <19> <20> <21> <22> <23> <24> <25> <26> <27> <28> n1 (n + tAHW)T (1 + n + tAHW)T n1 n1 (0.5 + n + tASW + tAHW)T (1.5 + n + tASW + tAHW)T (1 + tAHW)T - 60 (1 + n + tAHW)T - 60 n1 (1 + n)T - 40 T - 30 (1.5 + tASW + tAHW)T - 80 (1.5 + n + tASW + tAHW)T - 80 (0.5 + tAHW)T - 35 0 (1 + i)T - 32 0.5T - 20 (1.5 + i + tASW)T - 20 (1 + n)T - 20 (1 + tASW)T - 50 35 Conditions MIN. (0.5 + tASW)T - 42 (0.5 + tASW)T - 30 32 (2 + n + tASW + tAHW)T - 72 (1 + n + tASW + tAHW)T - 40 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Caution Set the following in accordance with the usage conditions of the CPU operating clock frequency (k = 0 to 3). * 70 ns < 1/fCPU < 84 ns Set an address setup wait (AWC.ASWk bit = 1). * 62.5 ns < 1/fCPU < 70 ns Set an address setup wait (ASWk bit = 1) and address hold wait (AWC.AHWk bit = 1). Remarks 1. tASW: Number of address setup wait clocks tAHW: Number of address hold wait clocks 2. T = 1/fCPU (fCPU: CPU operating clock frequency) 3. n: Number of wait clocks inserted in the bus cycle The sampling timing changes when a programmable wait is inserted. 4. m = 0, 1 5. i: Number of idle states inserted after a read cycle (0 or 1) 6. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. User's Manual U16889EJ1V0UD 735 CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) Read Cycle (CLKOUT Asynchronous): In Multiplex Bus Mode T1 T2 TW T3 CLKOUT (output) A16 to A23 (output) CS0 to CS3 (output) <9> AD0 to AD15 (I/O) Address Hi-Z Data <6> <7> <12> ASTB (output) <17> <13> <11> <8> <10> <14> <15> RD (output) <16> <25> <27> <26> <28> WAIT (input) <21> <23> <22> <24> Remark WR0 and WR1 are high level. 736 User's Manual U16889EJ1V0UD CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) Write Cycle (CLKOUT Asynchronous): In Multiplex Bus Mode T1 T2 TW T3 CLKOUT (output) A16 to A23 (output) CS0 to CS3 (output) AD0 to AD15 (I/O) Address Data <6> <7> ASTB (output) <17> <18> <11> <19> <14> <20> WR0 (output), WR1 (output) <16> <25> <27> <26> <28> WAIT (input) <21> <23> <22> <24> Remark RD is high level. User's Manual U16889EJ1V0UD 737 CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) (b) Read/write cycle (CLKOUT synchronous): In multiplex bus mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 4.0 to 5.5 V, 4.0 V BVDD VDD, 4.0 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (1/2) Parameter Delay time from CLKOUT to address Delay time from CLKOUT to address float Delay time from CLKOUT to ASTB Delay time from CLKOUT to RD, WRm Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Data output delay time from CLKOUT WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) tDKST tDKRDWR tSIDK tHKID tDKOD tSWTK tHKWT <31> <32> <33> <34> <35> <36> <37> 15 0 0 -22 15 0 19 23 0 ns ns ns ns ns ns ns tDKA tFKA Symbol <29> <30> Conditions MIN. 0 0 MAX. 19 14 Unit ns ns Remarks 1. m = 0, 1 2. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (2/2) Parameter Delay time from CLKOUT to address Delay time from CLKOUT to address float Delay time from CLKOUT to ASTB Delay time from CLKOUT to RD, WRm Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Data output delay time from CLKOUT WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) tDKST tDKRDWR tSIDK tHKID tDKOD tSWTK tHKWT <31> <32> <33> <34> <35> <36> <37> 25 0 0 -22 30 0 19 55 0 ns ns ns ns ns ns ns tDKA tFKA Symbol <29> <30> Conditions MIN. 0 0 MAX. 19 18 Unit ns ns Remarks 1. m = 0, 1 2. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. 738 User's Manual U16889EJ1V0UD CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) Read Cycle (CLKOUT Synchronous): In Multiplex Bus Mode T1 T2 TW T3 CLKOUT (output) <29> A16 to A23 (output) CS0 to CS3 (output) <33> <30> Hi-Z <34> AD0 to AD15 (I/O) Address Data <31> <31> ASTB (output) <32> <32> RD (output) WAIT (input) <36> <37> <36> <37> Remark WR0 and WR1 are high level. User's Manual U16889EJ1V0UD 739 CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) Write Cycle (CLKOUT Synchronous): In Multiplex Bus Mode T1 T2 TW T3 CLKOUT (output) <29> A16 to A23 (output) CS0 to CS3 (output) <35> AD0 to AD15 (I/O) Address <31> Data <31> ASTB (output) WR0 (output), WR1 (output) <32> <32> WAIT (input) <36> <37> <36> <37> Remark RD is high level. 740 User's Manual U16889EJ1V0UD CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) (2) In separate bus mode (a) Read cycle (CLKOUT asynchronous): In separate bus mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 4.0 to 5.5 V, 4.0 V BVDD VDD, 4.0 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (1/2) Parameter Address setup time (to RD) Address hold time (from RD) RD low-level width Data setup time (to RD) Data hold time (from RD) Data setup time (to address) WAIT setup time (to RD) tSARD tHARD tWRDL tSISD tHISD tSAID tSRDWT1 tSRDWT2 WAIT hold time (from RD) tHRDWT1 tHRDWT2 WAIT setup time (to address) tSAWT1 tSAWT2 WAIT hold time (from address) tHAWT1 tHAWT2 Symbol <38> <39> <40> <41> <42> <43> <44> <45> <46> <47> <48> <49> <50> <51> (n + tASW + tAHW)T (1 + n + tASW + tAHW)T (n - 0.5 + tAHW)T (n + 0.5 + tAHW)T (1 + tASW + tAHW)T - 65 (1 + n + tASW + tAHW)T - 65 Conditions MIN. (0.5 + tASW)T - 50 i - 13 (1.5 + n + tAHW)T - 15 30 0 (2 + n + tASW + tAHW)T - 65 (0.5 + tAHW)T - 32 (0.5 + n + tAHW)T - 32 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Caution Set the following in accordance with the usage conditions of the CPU operating clock frequency (k = 0 to 3). * 1/fCPU < 100 ns Set an address setup wait (ASWk bit = 1). Remarks 1. tASW: Number of address setup wait clocks tAHW: Number of address hold wait clocks 2. T = 1/fCPU (fCPU: CPU operating clock frequency) 3. n: Number of wait clocks inserted in the bus cycle The sampling timing changes when a programmable wait is inserted 4. i: Number of idle states inserted after a read cycle (0 or 1) 5. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. User's Manual U16889EJ1V0UD 741 CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (2/2) Parameter Address setup time (to RD) Address hold time (from RD) RD low-level width Data setup time (to RD) Data hold time (from RD) Data setup time (to address) WAIT setup time (to RD) Symbol tSARD tHARD tWRDL tSISD tHISD tSAID tSRDWT1 tSRDWT2 WAIT hold time (from RD) tHRDWT1 tHRDWT2 WAIT setup time (to address) tSAWT1 tSAWT2 WAIT hold time (from address) tHAWT1 tHAWT2 <38> <39> <40> <41> <42> <43> <44> <45> <46> <47> <48> <49> <50> <51> (n + tASW + tAHW)T (1 + n + tASW + tAHW)T (n - 0.5 + tAHW)T (n + 0.5 + tAHW)T (1 + tASW + tAHW)T - 130 (1 + n + tASW + tAHW)T - 130 Conditions MIN. (0.5 + tASW)T - 100 i - 26 (1.5 + n + tAHW)T - 30 60 0 (2 + n + tASW + tAHW)T - 120 (0.5 + tAHW)T - 50 (0.5 + n + tAHW)T - 50 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Caution Set the following in accordance with the usage conditions of the CPU operating clock frequency (k = 0 to 3). * 1/fCPU < 200 ns Set an address setup wait (ASWk bit = 1). Remarks 1. tASW: Number of address setup wait clocks tAHW: Number of address hold wait clocks 2. T = 1/fCPU (fCPU: CPU operating clock frequency) 3. n: Number of wait clocks inserted in the bus cycle The sampling timing changes when a programmable wait is inserted. 4. i: Number of idle states inserted after a read cycle (0 or 1) 5. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. 742 User's Manual U16889EJ1V0UD CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) Read Cycle (CLKOUT Asynchronous): In Separate Bus Mode T1 TW T2 CLKOUT (output) CS0 to CS3 (output) A0 to A23 (output) <39> <43> AD0 to AD15 (I/O) Hi-Z <42> <41> <40> RD (output) <47> <45> <46> <44> WAIT (input) <48> <50> <49> <51> Hi-Z <38> Remark WR0 and WR1 are high level. User's Manual U16889EJ1V0UD 743 CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) (b) Write cycle (CLKOUT asynchronous): In separate bus mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 4.0 to 5.5 V, 4.0 V BVDD VDD, 4.0 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (1/2) Parameter Address setup time (to WRm) Address hold time (from WRm) WRm low-level width Data output time from WRm Data setup time (to WRm) Data hold time (from WRm) Data setup time (to address) WAIT setup time (to WRm) Symbol tSAWR tHAWR tWWRL tDOSDW tSOSDW tHOSDW tSAOD tSWRWT1 tSWRWT2 WAIT hold time (from WRm) tHWRWT1 tHWRWT2 WAIT setup time (to address) tSAWT1 tSAWT2 WAIT hold time (from address) tHAWT1 tHAWT2 <52> <53> <54> <55> <56> <57> <58> <59> <60> <61> <62> <63> <64> <65> <66> (n + tASW + tAHW)T (1 + n + tASW + tAHW)T 0 nT (1 + tASW + tAHW)T - 45 (1 + n + tASW + tAHW)T - 45 Conditions MIN. (1 + tASW + tAHW)T - 60 0.5T - 10 (0.5 + n)T - 10 -5 (0.5 + n)T - 20 0.5T - 20 (1 + tASW + tAHW)T - 30 30 nT - 30 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Caution Set the following in accordance with the usage conditions of the CPU operating clock frequency (k = 0 to 3). * 1/fCPU < 60 ns Set an address setup wait (ASWk bit = 1). Remarks 1. m = 0, 1 2. tASW: Number of address setup wait clocks tAHW: Number of address hold wait clocks 3. T = 1/fCPU (fCPU: CPU operating clock frequency) 4. n: Number of wait clocks inserted in the bus cycle The sampling timing changes when a programmable wait is inserted. 5. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. 744 User's Manual U16889EJ1V0UD CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (2/2) Parameter Address setup time (to WRm) Address hold time (from WRm) WRm low-level width Data output time from WRm Data setup time (to WRm) Data hold time (from WRm) Data setup time (to address) WAIT setup time (to WRm) Symbol tSAWR tHAWR tWWRL tDOSDW tSOSDW tHOSDW tSAOD tSWRWT1 tSWRWT2 WAIT hold time (from WRm) tHWRWT1 tHWRWT2 WAIT setup time (to address) tSAWT1 tSAWT2 WAIT hold time (from address) tHAWT1 tHAWT2 <52> <53> <54> <55> <56> <57> <58> <59> <60> <61> <62> <63> <64> <65> <66> (n + tASW + tAHW)T (1 + n + tASW + tAHW)T 0 nT (1 + tASW + tAHW)T - 100 (1 + n + tASW + tAHW)T - 100 Conditions MIN. (1 + tASW + tAHW)T - 100 0.5T - 10 (0.5 + n)T - 10 -5 (0.5 + n)T - 35 0.5T - 35 (1 + tASW + tAHW)T - 55 50 nT - 50 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Caution Set the following in accordance with the usage conditions of the CPU operating clock frequency (k = 0 to 3). * 1/fCPU < 100 ns Set an address setup wait (ASWk bit = 1). Remarks 1. m = 0, 1 2. tASW: Number of address setup wait clocks tAHW: Number of address hold wait clocks 3. T = 1/fCPU (fCPU: CPU operating clock frequency) 4. n: Number of wait clocks inserted in the bus cycle The sampling timing changes when a programmable wait is inserted. 5. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. User's Manual U16889EJ1V0UD 745 CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) Write Cycle (CLKOUT Asynchronous): In Separate Bus Mode T1 TW T2 CLKOUT (output) CS0 to CS3 (output) A0 to A23 (output) <53> <58> AD0 to AD15 (I/O) Hi-Z <55> <52> <57> <56> <54> WR0, WR1 (output) <62> <60> <59> <61> WAIT (input) <63> <65> <64> <66> Hi-Z Remark RD is high level. 746 User's Manual U16889EJ1V0UD CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) (c) Read cycle (CLKOUT synchronous): In separate bus mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 4.0 to 5.5 V, 4.0 V BVDD VDD, 4.0 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (1/2) Parameter Delay time from CLKOUT to address, CS Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Delay time from CLKOUT to RD WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) tSISDK tHKISD tDKSR tSWTK tHKWT <68> <69> <70> <71> <72> 15 0 0 20 0 6 ns ns ns ns ns Symbol tDKSA <67> Conditions MIN. 0 MAX. 35 Unit ns Remark The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (2/2) Parameter Delay time from CLKOUT to address, CS Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Delay time from CLKOUT to RD WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) tSISDK tHKISD tDKSR tSWTK tHKWT <68> <69> <70> <71> <72> 30 0 0 40 0 10 ns ns ns ns ns Symbol tDKSA <67> Conditions MIN. 0 MAX. 65 Unit ns Remark The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. User's Manual U16889EJ1V0UD 747 CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) Read Cycle (CLKOUT Synchronous, 1 Wait): In Separate Bus Mode T1 TW T2 CLKOUT (output) <67> <67> CS0 to CS3 (output) A0 to A23 (output) <68> Hi-Z <69> Hi-Z <70> AD0 to AD15 (I/O) <70> RD (output) <71> <72> <71> <72> WAIT (input) Remark WR0 and WR1 are high level. 748 User's Manual U16889EJ1V0UD CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) (d) Write cycle (CLKOUT synchronous): In separate bus mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 4.0 to 5.5 V, 4.0 V BVDD VDD, 4.0 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (1/2) Parameter Delay time from CLKOUT to address, CS Data output delay time from CLKOUT Delay time from CLKOUT to WRm WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) tDKSW tSWTK tHKWT <75> <76> <77> 0 20 0 10 ns ns ns tDKSD <74> 0 10 ns Symbol tDKSA <73> Conditions MIN. 0 MAX. 35 Unit ns Remarks 1. m = 0, 1 2. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (2/2) Parameter Delay time from CLKOUT to address, CS Data output delay time from CLKOUT Delay time from CLKOUT to WRm WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) tDKSW tSWTK tHKWT <75> <76> <77> 0 40 0 15 ns ns ns tDKSD <74> 0 15 ns Symbol tDKSA <73> Conditions MIN. 0 MAX. 65 Unit ns Remarks 1. m = 0, 1 2. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. User's Manual U16889EJ1V0UD 749 CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) Write Cycle (CLKOUT Synchronous): In Separate Bus Mode T1 TW T2 CLKOUT (output) <73> <73> CS0 to CS3 (output) A0 to A23 (output) <74> Hi-Z <74> Hi-Z AD0 to AD15 (I/O) <75> <75> WR0, WR1 (output) <76> <77> <76> <77> WAIT (input) Remark RD is high level. 750 User's Manual U16889EJ1V0UD CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) (3) Bus hold (a) CLKOUT asynchronous (TA = -40 to +85C, VDD = EVDD = AVREF0 = 4.0 to 5.5 V, 4.0 V BVDD VDD, 4.0 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (1/2) Parameter HLDRQ high-level width HLDAK low-level width Delay time from HLDAK to bus output Delay time from HLDRQ to HLDAK Delay time from HLDRQ to HLDAK tWHQH tWHAL tDHAC tDHQHA1 tDHQHA2 Symbol <78> <79> <80> <81> <82> 0.5T Conditions MIN. T + 10 T - 15 -40 (2n + 7.5)T + 40 1.5T + 40 MAX. Unit ns ns ns ns ns Remarks 1. T = 1/fCPU (fCPU: CPU operating clock frequency) 2. n: Number of wait clocks inserted in the bus cycle The sampling timing changes when a programmable wait is inserted. 3. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (2/2) Parameter HLDRQ high-level width HLDAK low-level width Delay time from HLDAK to bus output Delay time from HLDRQ to HLDAK Delay time from HLDRQ to HLDAK tWHQH tWHAL tDHAC tDHQHA1 tDHQHA2 Symbol <78> <79> <80> <81> <82> 0.5T Conditions MIN. T + 10 T - 15 -80 (2n + 7.5)T + 70 1.5T + 70 MAX. Unit ns ns ns ns ns Remarks 1. T = 1/fCPU (fCPU: CPU operating clock frequency) 2. n: Number of wait clocks inserted in the bus cycle The sampling timing changes when a programmable wait is inserted. 3. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. User's Manual U16889EJ1V0UD 751 CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) Bus Hold (CLKOUT Asynchronous) TI CLKOUT (output) TH TH TH TI <78> HLDRQ (input) <81> <82> HLDAK (output) <79> Address bus (output) Data bus (I/O) Hi-Z <80> CS0 to CS3 (output) Hi-Z ASTB (output) Hi-Z RD (output), WR0 (output), WR1 (output) Hi-Z 752 User's Manual U16889EJ1V0UD CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) (b) CLKOUT synchronous (TA = -40 to +85C, VDD = EVDD = AVREF0 = 4.0 to 5.5 V, 4.0 V BVDD VDD, 4.0 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (1/2) Parameter HLDRQ setup time (to CLKOUT) HLDRQ hold time (from CLKOUT) Delay time from CLKOUT to bus float Delay time from CLKOUT to HLDAK tSHQK tHKHQ tDKF tDKHA Symbol <83> <84> <85> <86> Conditions MIN. 15 0 20 20 MAX. Unit ns ns ns ns Remark The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (2/2) Parameter HLDRQ setup time (to CLKOUT) HLDRQ hold time (from CLKOUT) Delay time from CLKOUT to bus float Delay time from CLKOUT to HLDAK tSHQK tHKHQ tDKF tDKHA Symbol <83> <84> <85> <86> Conditions MIN. 25 0 40 40 MAX. Unit ns ns ns ns Remark The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. User's Manual U16889EJ1V0UD 753 CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) Bus Hold (CLKOUT Synchronous) T2 CLKOUT (output) T3 TI TH TH TH TI <83> <84> <83> HLDRQ (input) <86> <86> HLDAK (output) <85> Address bus (output) Data bus (I/O) Hi-Z CS0 to CS3 (output) Hi-Z ASTB (output) Hi-Z RD (output), WR0 (output), WR1 (output) Hi-Z 754 User's Manual U16889EJ1V0UD CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) Basic Operation (1) Reset/external interrupt timing (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter RESET low-level width Symbol tWRSL1 tWRSL2 <87> <88> Conditions Reset in power-on status Power-on-reset when REGC = VDD Note tVR > 150 s tVR 150 s NMI high-level width NMI low-level width INTPn high-level width INTPn low-level width tWNIH tWNIL tWITH tWITL <89> <90> <91> <92> Analog noise elimination Analog noise elimination n = 0 to 6 (analog noise elimination) n = 0 to 6 (analog noise elimination) MIN. 2 2 10 40 1 1 600 600 MAX. Unit s s s s s s ns ns Note Power-on-reset when REGC = Capacity Remarks 1. tVR: Time required for VDD to reach 0 V to 4.0 V (= operation lower-limit voltage) 2. The above specification shows the pulse width that is accurately detected as a valid edge. If a pulse narrower than the above specification is input, therefore, it may also be detected as a valid edge. Reset/Interrupt VDD tVR RESET (input) <88> <87> <89> <90> NMI (input) <91> <92> INTPn (input) Remark n = 0 to 6 User's Manual U16889EJ1V0UD 755 CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) Timer Timing (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter TI0n high-level width Symbol tTI0H <93> Conditions REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V TI0n low-level width tTI0L <94> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V TI5m high-level width tTI5H <95> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V TI5m low-level width tTI5L <96> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V TIP0m high-level width tTIPH <97> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V TIP0m low-level width tTIPL <98> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V np x Tsmpp + 100 np x Tsmpp + 200 Note 2 MIN. 2Tsmp0 + 100 2Tsmp0 + 200 Note 1 MAX. Unit ns ns Note 1 2Tsmp0 + 100 2Tsmp0 + 200 Note 1 ns ns Note 1 50 100 ns ns 50 100 np x Tsmpp + 100 np x Tsmpp + 200 Note 2 ns ns ns ns Note 2 ns ns Note 2 Notes 1. Tsmp0: Timer 0 count clock cycle However, Tsmp0 = 4/fXX when TI0n is used as an external clock. 2. Tsmpp: Digital noise elimination sampling clock cycle of TIP0m pin If TIP00 is used as an external clock or an external clear, however, Tsmpp = 0 (digital noise is not eliminated). Remarks 1. n = 00, 01, 10, 11, 20, 21, 30, 31, 40, 41, 50, 51 m = 0, 1 2. The above specification shows the pulse width that is accurately detected as a valid edge. If a pulse narrower than the above specification is input, therefore, it may also be detected as a valid edge. Timer Input Timing <93>/<95>/<97> TI0n (input) TI5m (input) TIP0m (input) <94>/<96>/<98> Remark n = 00, 01, 10, 11, 20, 21, 30, 31, 40, 41, 50, 51 m = 0, 1 756 User's Manual U16889EJ1V0UD CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) UART Timing (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Transmit rate ASCK0 frequency REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V Symbol Conditions MIN. MAX. 312.5 12 6 Unit kbps MHz MHz User's Manual U16889EJ1V0UD 757 CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) CSI0 Timing (1) Master mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter SCK0n cycle time tKCY1 Symbol <99> Conditions REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V SCK0n high-/low-level width SI0n setup time (to SCK0n) tKH1, tKL1 tSIK1 <100> <101> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V SI0n hold time (from SCK0n) tKSI1 <102> REGC = VDD = 5 V 10% REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V Delay time from SCK0n to SO0n output tKSO1 <103> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V 30 60 ns ns 30 50 ns ns tKCY1/2 - 30 30 50 ns ns ns MIN. 200 400 MAX. Unit ns ns Remark n = 0 to 2 (2) Slave mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter SCK0n cycle time tKCY2 Symbol <99> Conditions REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V SCK0n high-/low-level width tKH2, tKL2 <100> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V SI0n setup time (to SCK0n) tSIK2 <101> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V SI0n hold time (from SCK0n) tKSI2 <102> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V Delay time from SCK0n to SO0n output tKSO2 <103> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V 50 100 ns ns 30 60 ns ns 30 60 ns ns 45 90 ns ns MIN. 200 400 MAX. Unit ns ns Remark n = 0 to 2 758 User's Manual U16889EJ1V0UD CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) <99> <100> SCK0n (I/O) <100> <101> <102> Hi-Z SI0n (input) Input data Hi-Z <103> SO0n (output) Output data Remarks 1. When transmit/receive type 1 (CSICn.CKPn, CSICn.DAPn bits = 00) 2. n = 0 to 2 User's Manual U16889EJ1V0UD 759 CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) CSIA Timing (1) Master mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter SCKAn cycle time tKCY3 Symbol <99> Conditions REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V SCKAn high-/low-level width tKH3, tKL3 SIAn setup time (to SCKAn) tSIK3 <101> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V SIAn hold time (from SCKAn) tKSI3 <102> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V Delay time from SCKAn to SOAn output tKSO3 <103> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V 30 60 ns ns 30 60 ns ns 30 60 ns ns <100> tKCY3/2 - 30 ns MIN. 500 1000 MAX. Unit ns ns Remark n = 0, 1 (2) Slave mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter SCKAn cycle time tKCY4 Symbol <99> Conditions REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V SCKAn high-/low-level width SIAn setup time (to SCKAn) tKH4, tKL4 tSIK4 <100> <101> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V SIAn hold time (from SCKAn) tKSI4 <102> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V Delay time from SCKAn to SOAn output tKSO4 <103> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V tCY x 2 + 30 tCY x 2 + 60 Note MIN. 840 1700 tKCY4/2 - 30 50 100 tCY x 2 + 15 tCY x 2 + 30 Note MAX. Unit ns ns ns ns ns ns ns Note ns ns Note Note tCY: Internal clock output cycle fXX (CSISn.CKSAn1, CSISn.CKSAn0 bits = 00), fXX/2 (CKSAn1, CKSAn0 bits = 01) fXX/22 (CKSAn1, CKSAn0 bits = 10), fXX/23 (CKSAn1, CKSAn0 bits = 11) Remark n = 0, 1 760 User's Manual U16889EJ1V0UD CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) <99> <100> SCKAn (I/O) <100> <101> <102> Hi-Z SIAn (input) Input data Hi-Z <103> SOAn (output) Output data Remark n = 0, 1 User's Manual U16889EJ1V0UD 761 CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) I2C Bus Mode (Y Products (Products with On-Chip I2C) Only) (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Normal Mode MIN. SCLn clock frequency Bus free time (Between start and stop conditions) Hold time Note 1 High-Speed Mode MIN. 0 1.3 MAX. 400 - Unit MAX. 100 - fCLK tBUF <104> 0 4.7 kHz s s s s s s s ns ns ns tHD:STA tLOW tHIGH tSU:STA <105> <106> <107> <108> <109> 4.0 4.7 4.0 4.7 - - - - - - - 1000 300 - - 0.6 1.3 0.6 0.6 - Note 2 - - - - - Note 3 SCLn clock low-level width SCLn clock high-level width Setup time for start/restart conditions Data hold time CBUS compatible master I C mode Data setup time SDAn and SCLn signal rise time SDAn and SCLn signal fall time Stop condition setup time Pulse width of spike suppressed by input filter Capacitance load of each bus line 2 tHD:DAT 5.0 Note 2 0 tSU:DAT tR tF tSU:STO tSP <110> <111> <112> <113> <114> 0 0.9 250 - - 4.0 - - 100 Note 4 - Note 5 20 + 0.1Cb 300 300 - 50 20 + 0.1Cb 0.6 0 - Note 5 s ns Cb 400 400 pF Notes 1. At the start condition, the first clock pulse is generated after the hold time. 2. The system requires a minimum of 300 ns hold time internally for the SDAn signal (at VIHmin. of SCLn signal) in order to occupy the undefined area at the falling edge of SCLn. 3. If the system does not extend the SCLn signal low hold time (tLOW), only the maximum data hold time (tHD:DAT) needs to be satisfied. 4. The high-speed mode I2C bus can be used in the normal-mode I2C bus system. In this case, set the highspeed mode I C bus so that it meets the following conditions. * If the system does not extend the SCLn signal's low state hold time: tSU:DAT 250 ns * If the system extends the SCLn signal's low state hold time: Transmit the following data bit to the SDAn line prior to the SCLn line release (tRmax. + tSU:DAT = 1000 + 250 = 1250 ns: Normal mode I2C bus specification). 5. Cb: Total capacitance of one bus line (unit: pF) Remark n = 0, 1 2 762 User's Manual U16889EJ1V0UD CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) I2C Bus Mode (Y Products (Products with On-Chip I2C) Only) <106> <107> SCLn (I/O) <112> <111> <105> <109> <110> <108> <105> <114> <113> SDAn (I/O) <104> <111> <112> Stop condition Start condition Restart condition Stop condition Remark n = 0, 1 User's Manual U16889EJ1V0UD 763 CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) A/D Converter (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Resolution Overall error Note 1 Symbol Conditions MIN. 10 TYP. 10 0.2 0.3 MAX. 10 0.4 0.6 100 100 0.4 0.6 0.4 0.6 2.5 4.5 1.5 2.0 Unit bit %FSR %FSR AINL 4.0 AVREF0 5.5 V 2.7 AVREF0 4.0 V Conversion time tCONV 4.0 AVREF0 5.5 V 2.7 AVREF0 4.0 V 14 17 s s %FSR %FSR %FSR %FSR LSB LSB LSB LSB V mA Zero-scale error Note 1 EZS 4.0 AVREF0 5.5 V 2.7 AVREF0 4.0 V Full-scale error Note 1 Efs 4.0 AVREF0 5.5 V 2.7 AVREF0 4.0 V Non-linearity error Note 2 ILE 4.0 AVREF0 5.5 V 2.7 AVREF0 4.0 V Differential linearity error Note 2 DLE 4.0 AVREF0 5.5 V 2.7 AVREF0 4.0 V Analog input voltage AVREF0 current VIAN IAREF0 When using A/D converter When not using A/D converter 0 1.3 1.0 AVREF0 2.5 T.B.D. A Notes 1. Excluding quantization error (0.05 %FSR). 2. Excluding quantization error (0.5 LSB). Remark LSB: Least Significant Bit FSR: Full Scale Range D/A Converter (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Resolution Overall error Notes 1, 2 Symbol Conditions MIN. TYP. MAX. 8 Unit bit %FSR %FSR %FSR Load condition = 2 M Load condition = 4 M Load condition = 10 M 1.2 0.8 0.6 10 15 8 1.5 1.0 3.0 10 Settling time Note 2 C = 30 pF VDD = 4.5 to 5.5 V VDD = 2.7 to 4.5 V s s k mA Output resistance AVREF1 current Note 3 RO IAVREF1 Output data: DACSn register = 55H During D/A conversion When D/A conversion stopped Note 4 A Notes 1. Excluding quantization error (0.2 %FSR). 2. R is the D/A converter output pin load resistance, and C is the D/A converter output pin load capacitance. 3. Value of 1 channel of D/A converter 4. Value of 2 channels of D/A converter Remark n = 0, 1 User's Manual U16889EJ1V0UD 764 CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) Flash Memory Programming Characteristics (TA = -10 to +65C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (1) Basic characteristics Parameter Programming operation frequency Symbol Conditions REGC = VDD = 4.5 to 5.5 V REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V REGC = VDD = 2.7 to 5.5 V Supply voltage Overall erase time Write time Number of rewrites VDD tERA tWRW CERWR Note 2 MIN. 2 2 2 2 2.7 T.B.D. T.B.D. 100 TYP. MAX. 20 16 8 8 Note 1 Unit MHz MHz MHz MHz V s s Times Note 1 5.5 Notes 1. These values may change after evaluation. 2. When writing initially to shipped products, it is counted as one rewrite for both "erase to write" and "write only". Example (P: Write, E: Erase) Shipped product PEPEP: 3 rewrites Shipped product E PEPEP: 3 rewrites User's Manual U16889EJ1V0UD 765 CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) (2) Serial write operation characteristics Parameter Setup time from VDD to FLMD0 Release time from FLMD0 to RESET Start time from RESET to FLMD0 pulse input End time from RESET to FLMD0 pulse input FLMD0 pulse high-/low-level width Input time from RESET to 1st low data tPW tR1 When UART communication is selected Input time from 1st low data input to 2nd low data Input time from 2nd low data input to reset command Low data input width tL1/tL2 t2C t12 When UART communication is selected When UART communication is selected When UART communication is selected Input time from RESET to reset command tRC When CSI or CSI-HS communication is selected T.B.D. s 9600 bps T.B.D. s T.B.D. s T.B.D. T.B.D. T.B.D. tPRE T.B.D. ms Symbol tDP tPR tRP Conditions MIN. T.B.D. T.B.D. T.B.D. TYP. MAX. Unit s s s s s 766 User's Manual U16889EJ1V0UD CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) Flash Write Mode Setting Timing (a) Serial write operation timing (UART) VDD FLMD0 tDP FLMD1 0V RESET Reset command tPR TXD0 RXD0 tR1 tL1 t12 tL2 t2C Remark The FLMD0 pulse does not have to be input for UART0 communication. (b) Serial write operation timing (CSI, CSI-HS) VDD FLMD0 tDP FLMD1 0V tPW tPW RESET tRP tPR SCK00 tRPE Reset command SO00 SI00 tRC User's Manual U16889EJ1V0UD 767 CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) Standard products are as follows. PD703216, 703216Y, 703217, 703217Y, 70F3217, 70F3217Y (A) grade products are as follows. PD703216(A), 703216Y(A), 703217(A), 703217Y(A), 70F3217(A) , 70F3217Y(A) 768 User's Manual U16889EJ1V0UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) Absolute Maximum Ratings (TA = 25C) (1/2) Parameter Supply voltage Symbol VDD VPP BVDD EVDD AVREF0 AVREF1 Conditions VDD = EVDD = AVREF0 Flash memory version, Note 1 BVDD VDD VDD = EVDD = AVREF0 VDD = EVDD = AVREF0 AVREF1 VDD (D/A output mode) AVREF1 = AVREF0 = VDD (port mode) VSS AVSS BVSS EVSS Input voltage VI1 VSS = EVSS = BVSS = AVSS VSS = EVSS = BVSS = AVSS VSS = EVSS = BVSS = AVSS VSS = EVSS = BVSS = AVSS P00 to P06, P30 to P35, P38, P39, P40 to P42, P50 to P55, P60 to P613, P80, P81, P90 to P915, RESET VI2 PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7, PDL0 to PDL15, PDH0 to PDH7 VI3 VI4 VI5 Analog input voltage VIAN P10, P11 P36, P37, P614, P615 X1, X2, XT1, XT2 P70 to P715 -0.3 to AVREF1 + 0.3 -0.3 to +13 Note 3 Note 2 Ratings -0.3 to +6.5 -0.3 to +10.5 -0.3 to VDD + 0.3 -0.3 to +6.5 -0.3 to +6.5 -0.3 to VDD + 0.3 -0.3 to +0.3 -0.3 to +0.3 -0.3 to +0.3 -0.3 to +0.3 -0.3 to EVDD + 0.3 Note 2 Note 2 Note 2 Unit V V V V V V V V V V V -0.3 to BVDD + 0.3 Note 2 V V V V V -0.3 to VDD + 0.3 Note 2 -0.3 to AVREF0 + 0.3 Note 2 Notes 1. Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash memory is written. * When supply voltage rises VPP must exceed VDD 15 s or more after VDD has reached the lower-limit value (2.7 V) of the operating voltage range (see a in the figure below). * When supply voltage drops VDD must be lowered 10 s or more after VPP falls below the lower-limit value (2.7 V) of the operating voltage range of VDD (see b in the figure below). VDD 2.7 V 0V a b VPP 2.7 V 0V 2. Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage. 3. When an on-chip pull-up resistor is not specified by a mask option. The same as VI1 when a pull-up resistor is specified. User's Manual U16889EJ1V0UD 769 CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) Absolute Maximum Ratings (TA = 25C) (2/2) Parameter Output current, low Symbol IOL Conditions P00 to P06, P10, P11, P30 to P35, P40 to P42, P50 to P55, P60 to P613, P80, P81, P90 to P915, PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7, PDL0 to PDL15, PDH0 to PDH7 P36 to P39, P614, P615 P00 to P06, P30 to P39, P40 to P42 P50 to P55, P60 to P615, P80, P81, P90 to P915 PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7 PDL0 to PDL15, PDH0 to PDH7 Output current, high IOH Per pin P00 to P06, P30 to P35, P40 to P42 P50 to P55, P60 to P613, P80, P81, P90 to P915 PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7 PDL0 to PDL15, PDH0 to PDH7 Operating ambient temperature Storage temperature Tstg Mask ROM version Flash memory version -65 to +150 -40 to +125 C C TA Total of all pins: -60 mA Total of all pins: -60 mA -30 -40 to +85 mA C Total of all pins: 70 mA Total of all pins: 70 mA 35 -10 -30 -30 -30 mA mA mA mA mA 35 mA 30 35 35 mA mA mA Per pin Ratings 20 Unit mA Cautions 1. Do not directly connect the output (or I/O) pins of IC products to each other, or to VDD, VCC, and GND. Open-drain pins or open-collector pins, however, can be directly connected to each other. Direct connection of the output pins between an IC product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Capacitance (TA = 25C, VDD = EVDD = AVREF0 = BVDD = AVREF1 = VSS = EVSS = BVSS = AVSS = 0 V) Parameter Input capacitance I/O capacitance Symbol CI CIO fX = 1 MHz Unmeasured pins returned to 0 V Conditions P70 to P715 Note P36 to P39, P614, P615 MIN. TYP. MAX. 15 15 20 Unit pF pF pF Note P00 to P06, P10, P11, P30 to P35, P40 to P42, P50 to P55, P60 to P613, P80, P81, P90 to P915, PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7, PDL0 to PDL15, PDH0 to PDH7 Remark fX: Main clock oscillation frequency User's Manual U16889EJ1V0UD 770 CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) Operating Conditions (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Internal system clock frequency Symbol fCLK Conditions REGC = VDD = 5 V 10% In PLL mode (fX = 2 to 5 MHz) REGC = Capacity, VDD = 4.0 to 5.5 V In PLL mode (fX = 2 to 4 MHz) REGC = VDD = 2.7 to 5.5 V REGC = VDD = 2.7 to 5.5 V, operating with subclock 0.0625 32.768 10 MHz kHz 0.25 16 MHz MIN. 0.25 TYP. MAX. 20 Unit MHz Remark fX: Main clock oscillation frequency Internal System Clock Frequency vs. Supply Voltage 100 Internal system clock frequency fCLK [MHz] When REGC = Capacity 20.0 16.0 10.0 1.0 0.1 0.032 0.01 2.0 3.0 4.0 Supply voltage VDD [V] 5.0 6.0 PLL Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V, VSS = 0 V) Parameter Input frequency Output frequency Lock time Symbol fX fXX tPLL After VDD reaches 2.7 V (MIN.) Conditions MIN. 2 8 TYP. MAX. 5 20 200 Unit MHz MHz s User's Manual U16889EJ1V0UD 771 CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) Main Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V, VSS = 0 V) Resonator Ceramic resonator X1 X2 Recommended Circuit Parameter Oscillation frequency (fX) Note 1 Conditions MIN. 2 TYP. MAX. 10 Unit MHz Oscillation stabilization time Note 2 After reset is released After STOP mode is released 2 /fX 15 s Note 3 s Crystal resonator X1 X2 Oscillation frequency (fX) Note 1 2 15 10 MHz Oscillation stabilization time Note 2 After reset is released After STOP mode is released 2 /fX s Note 3 s External clock X1 X2 X1, X2 input frequency (fX) REGC = VDD Duty = 50% 5% 2 10 MHz External clock Notes 1. Indicates only oscillator characteristics. 2. Time required to stabilize the resonator after reset or STOP mode is released. 3. The value differs depending on the OSTS register settings. Cautions 1. When using the main clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main clock is stopped and the device is operating on the subclock, wait until the oscillation stabilization time has been secured by the program before switching back to the main clock. 772 User's Manual U16889EJ1V0UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) (i) Murata Manufacturing Co., Ltd.: Ceramic resonator (TA = -40 to +85C) Product Name Type Oscillation Frequency fXX (MHz) C1 (pF) 47 47 39 47 SMD 5.000 39 47 SMD 10.000 10 15 SMD SMD SMD SMD SMD 2.000 3.000 4.000 5.000 10.000 47 47 39 39 10 C2 (pF) 47 47 39 47 39 47 10 15 47 47 39 39 10 Rd (k) 0 0 0 0 0 0 0 0 0 0 0 0 0 Recommended Circuit Constant Oscillation Voltage Range MIN. (V) 2.7 2.7 2.7 2.7 2.7 2.7 2.7 2.7 2.7 2.7 2.7 2.7 2.7 MAX. (V) 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 Manufacturer Murata Mfg. Co., Ltd. CSTCC2M00G56-R0 CSTCC3M00G56-R0 CSTCR4M00G55-R0 CSTLS4M00G56-B0 CSTCR5M00G55-R0 CSTLS5M00G56-B0 CSTCE10M0G52-R0 CSTLS10M0G53-B0 CSTCC2M00G56A-R0 CSTCC3M00G56A-R0 CSTCR4M00G55A-R0 CSTCR5M00G55A-R0 CSTCE10M0G52A-R0 SMD SMD SMD 2.000 3.000 4.000 Caution This oscillator constant is a reference value based on evaluation under a specific environment by the resonator manufacturer. If optimization of oscillator characteristics is necessary in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the V850ES/KJ1 so that the internal operating conditions are within the specifications of the DC and AC characteristics. User's Manual U16889EJ1V0UD 773 CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) Subclock Oscillator Characteristics (TA = -40 to +85C, VDD = 2.7 to 5.5 V, VSS = 0 V) Resonator Crystal resonator XT1 XT2 Recommended Circuit Parameter Oscillation frequency (fXT) Note 1 Conditions MIN. 32 TYP. 32.768 MAX. 35 Unit kHz Oscillation stabilization time Note 2 10 s External clock XT1 XT2 XT1 input frequency (fXT) Note 1 REGC = VDD 32 35 kHz Duty = 50% 5% External clock Notes 1. Indicates only oscillator characteristics. 2. Time required from when VDD reaches oscillation voltage range (2.7 V (MIN.)) to when the crystal resonator stabilizes. Cautions 1. When using the subclock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subclock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the main clock oscillator. Particular care is therefore required with the wiring method when the subclock is used. 774 User's Manual U16889EJ1V0UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) DC Characteristics (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) (1/5) Parameter Output current, high Symbol IOH1 Conditions Per pin for P00 to P06, P10, P11, P30 to P35, P40 to P42, P50 to P55, P60 to P613, P80, P81, P90 to P915 Total of P00 to P06, P30 to P35, P40 to P42 Total of P50 to P55, P60 to P613, P80, P81, P90 to P915 IOH2 EVDD = 4.0 to 5.5 V EVDD = 2.7 to 5.5 V EVDD = 4.0 to 5.5 V EVDD = 2.7 to 5.5 V -30 -15 -30 -15 -5.0 -30 -15 -30 -15 10 mA mA mA mA mA MAX. -5.0 Unit mA Per pin for PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7, PDH0 to PDH7, PDL0 to PDL15 Total of PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7 Total of PDL0 to PDL15, PDH0 to PDH7 BVDD = 4.0 to 5.5 V BVDD = 2.7 to 5.5 V BVDD = 4.0 to 5.5 V BVDD = 2.7 to 5.5 V mA mA mA mA mA Output current, low IOL1 Per pin for P00 to P06, P10, P11, P30 to P35, P40 to P42, P50 to P55, P60 to P613, P80, P81, P90 to P915 Per pin for P36 to P39 EVDD = 4.0 to 5.5 V EVDD = 2.7 to 5.5 V Per pin for P614, P615 EVDD = 4.0 to 5.5 V EVDD = 2.7 to 5.5 V Total of P00 to P06, P30 to P37, P40 to P42 Total of P38, P39, P50 to P55, P60 to P615, P80, P81, P90 to P915 15 8 10 5 30 30 mA mA mA mA mA mA IOL2 Per pin for PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7, PDH0 to PDH7, PDL0 to PDL15 Total of PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7 Total of PDL0 to PDL15, PDH0 to PDH7 10 mA 30 mA 30 mA User's Manual U16889EJ1V0UD 775 CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) DC Characteristics (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) (2/5) Parameter Input voltage, high Symbol VIH1 VIH2 VIH3 VIH4 VIH5 VIH6 VIH7 Input voltage, low VIL1 VIL2 VIL3 VIL4 VIL5 VIL6 VIL7 Note 1 Note 2 Note 3 P70 to P715 P10, P11 Note 4 Conditions MIN. 0.7EVDD 0.8EVDD 0.7BVDD 0.7AVREF0 0.7AVREF1 0.7EVDD VDD - 0.5 EVSS EVSS BVSS AVSS AVSS EVSS VSS TYP. MAX. EVDD EVDD BVDD AVREF0 AVREF1 12 Note 5 Unit V V V V V V V V V V V V V V P36, P37, P614, P615 X1, X2, XT1, XT2 Note 1 Note 2 Note 3 P70 to P715 P10, P11 Note 4 VDD 0.3EVDD 0.2EVDD 0.3BVDD 0.3AVREF0 0.3AVREF1 0.3EVDD 0.4 P36, P37, P614, P615 X1, X2, XT1, XT2 Notes 1. P00, P01, P30, P41, P60 to P65, P67, P611, P98, P911 and their alternate-function pins. 2. RESET, P02 to P06, P31 to P35, P38, P39, P40, P42, P50 to P55, P66, P68 to P610, P612, P613, P80, P81, P90 to P97, P99, P910, P912 to P915 and their alternate-function pins. 3. PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7, PDL0 to PDL15, PDH0 to PDH7 and their alternate-function pins. 4. When used as port pins, set AVREF1 = AVREF0 = VDD. 5. When an on-chip pull-up resistor is not specified by a mask option. EVDD when a pull-up resistor is specified. 776 User's Manual U16889EJ1V0UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) DC Characteristics (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) (3/5) Parameter Output voltage, high Symbol VOH1 Note 1 Conditions IOH = -2.0 mA, EVDD = 4.0 to 5.5 V Note 2 IOH = -0.1 mA, EVDD = 2.7 to 5.5 V VOH2 Note 3 IOH = -2.0 mA, BVDD = 4.0 to 5.5 V Note 4 Note 5 MIN. EVDD - 1.0 EVDD - 0.5 BVDD - 1.0 BVDD - 0.5 AVREF1 - 1.0 AVREF1 - 0.5 0 0 0 0 TYP. MAX. EVDD Unit V EVDD V BVDD V IOH = -0.1 mA, BVDD = 2.7 to 5.5 V IOH = -2.0 mA IOH = -0.1 mA BVDD V VOH3 P10, P11 AVREF1 AVREF1 0.8 0.8 0.8 2.0 V V V V V V Output voltage, low VOL1 VOL2 VOL3 VOL4 Note 6 Note 8 P10, P11 Note 5 IOL = 2.0 mA IOL = 2.0 mA IOL = 2 mA IOL = 15 mA, Note 7 Note 7 P36 to P39 EVDD = 4.0 to 5.5 V IOL = 8 mA, EVDD = 3.0 to 5.5 V IOL = 5 mA, EVDD = 2.7 to 5.5 V VOL5 P614, P615 IOL = 10 mA, EVDD = 4.0 to 5.5 V IOL = 5 mA, EVDD = 2.7 to 5.5 V Input leakage current, high Input leakage current, low Output leakage current, high Output leakage current, low Pull-up resistor ILIH ILIL ILOH ILOL RL VIN = VDD VIN = 0 V VO = VDD VO = 0 V VIN = 0 V 10 30 3.0 -3.0 3.0 -3.0 100 0 1.0 V 0 2.0 V 0 1.0 V 0 1.0 V A A A A k Notes 1. Total of P00 to P06, P30 to P35, P40 to P42 and their alternate-function pins: IOH = -30 mA, total of P50 to P55, P60 to P613, P80, P81, P90 to P915 and their alternate-function pins: IOH = -30 mA. 2. Total of P00 to P06, P30 to P35, P40 to P42 and their alternate-function pins: IOH = -15 mA, total of P50 to P55, P60 to P613, P80, P81, P90 to P915 and their alternate-function pins: IOH = -15 mA. 3. Total of PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7: IOH = -30 mA, total of PDH0 to PDH7, PDL0 to PDL15 and their alternate-function pins: IOH = -30 mA. 4. Total of PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7: IOH = -15 mA, total of PDH0 to PDH7, PDL0 to PDL15 and their alternate-function pins: IOH = -15 mA. 5. When used as port pins, set AVREF1 = AVREF0 = VDD. 6. Total of P00 to P06, P30 to P37, P40 to P42 and their alternate-function pins: IOL = 30 mA, total of P38, P39, P50 to P55, P60 to P615, P80, P81, P90 to P915 and their alternate-function pins: IOL = 30 mA. 7. Refer to IOL1 for IOL of P36 to P39, P614, and P615. 8. Total of PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7 and their alternate-function pins: IOL = 30 mA, total of PDH0 to PDH7, PDL0 to PDL15 and their alternate-function pins: IOL = 30 mA. User's Manual U16889EJ1V0UD 777 CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) DC Characteristics (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) (4/5) Parameter Supply current Note Symbol IDD1 Normal operation Conditions fXX = 20 MHz (fX = 5 MHz) (in PLL mode) REGC = VDD = 5 V 10% fXX = 16 MHz (fX = 4 MHz) (in PLL mode) REGC = Capacity VDD = 5 V 10% fXX = 10 MHz (fX = 10 MHz) REGC = VDD = 3 V 10% MIN. TYP. 43 MAX. 60 Unit mA (flash memory version) 27 40 mA 14 29 mA IDD2 HALT mode fXX = 20 MHz (fX = 5 MHz) (in PLL mode) REGC = VDD = 5 V 10% fXX = 16 MHz (fX = 4 MHz) (in PLL mode) REGC = Capacity VDD = 5 V 10% fXX = 10 MHz (fX = 10 MHz) REGC = VDD = 3 V 10% 18 28 mA 11 20 mA 6 11 mA IDD3 IDLE mode fX = 5 MHz (when PLL mode off) REGC = VDD = 5 V 10% fX = 4 MHz (when PLL mode off) REGC = Capacity VDD = 5 V 10% fX = 10 MHz (when PLL mode off) REGC = VDD = 3 V 10% 1200 2000 A 900 1600 A 900 1600 A IDD4 Subclock operating mode fXT = 32.768 kHz Main clock stopped 190 320 A IDD5 Subclock IDLE mode fXT = 32.768 kHz Main clock stopped, watch timer operating 15 60 A IDD6 STOP mode Subclock stopped (XT1 = VSS, when PSMR.XTSTP bit = 1) 0.1 30 A Note Total current of VDD, EVDD, and BVDD (all ports stopped). AVREF0 is not included. Remark fXX: Main clock frequency fX: Main clock oscillation frequency fXT: Subclock frequency 778 User's Manual U16889EJ1V0UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) DC Characteristics (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) (5/5) Parameter Supply current Note 1 Symbol IDD1 Normal operation Conditions fXX = 20 MHz (fX = 5 MHz) (in PLL mode) REGC = VDD = 5 V 10% fXX = 16 MHz (fX = 4 MHz) (in PLL mode) REGC = Capacity VDD = 5 V 10% fXX = 10 MHz (fX = 10 MHz) REGC = VDD = 3 V 10% MIN. TYP. 30 MAX. 45 Unit mA (mask ROM version) 18 30 mA 9 18 mA IDD2 HALT mode fXX = 20 MHz (fX = 5 MHz) (in PLL mode) REGC = VDD = 5 V 10% fXX = 16 MHz (fX = 4 MHz) (in PLL mode) REGC = Capacity VDD = 5 V 10% fXX = 10 MHz (fX = 10 MHz) REGC = VDD = 3 V 10% 17 25 mA 10 18 mA 5 10 mA IDD3 IDLE mode fX = 5 MHz (when PLL mode off) REGC = VDD = 5 V 10% fX = 4 MHz (when PLL mode off) REGC = Capacity VDD = 5 V 10% fX = 10 MHz (when PLL mode off) REGC = VDD = 3 V 10% Note 2 900 1400 A 600 1000 A 600 1000 A IDD4 Subclock operating mode fXT = 32.768 kHz Main clock stopped fXT = 32.768 kHz Main clock stopped, watch timer operating 70 160 A A IDD5 Subclock IDLE mode 15 60 IDD6 STOP mode Subclock stopped (XT1 = VSS, when PSMR.XTSTP bit = 1) 0.1 30 A Notes 1. Total current of VDD, EVDD, and BVDD (all ports stopped). AVREF0 is not included. 2. When the capacitance of the capacitor in the oscillator is 15 pF. Remark fXX: Main clock frequency fX: Main clock oscillation frequency fXT: Subclock frequency User's Manual U16889EJ1V0UD 779 CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) Data Retention Characteristics STOP Mode (TA = -40 to +85C) Parameter Data retention voltage STOP release signal input time Symbol VDDDR tDREL Conditions STOP mode MIN. 2.0 0 TYP. MAX. 5.5 Unit V s Caution Shifting to STOP mode and restoring from STOP mode must be performed within the rated operating range. STOP mode setting Operating voltage lower limit VDD STOP release signal input VDDDR tDREL RESET (input) STOP mode release interrupt (NMI, etc.) (Released by falling edge) STOP mode release interrupt (NMI, etc.) (Released by rising edge) 780 User's Manual U16889EJ1V0UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) AC Characteristics AC Test Input Measurement Points (VDD, AVREF0, EVDD, BVDD) VDD VIH Measurement points VIH VIL 0V VIL AC Test Output Measurement Points VOH Measurement points VOH VOL VOL Load Conditions DUT (Device under measurement) CL = 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means. User's Manual U16889EJ1V0UD 781 CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) CLKOUT Output Timing (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Output cycle High-level width Symbol tCYK tWKH <1> <2> VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V Low-level width tWKL <3> VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V Rise time tKR <4> VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V Fall time tKF <5> VDD = 4.0 to 5.5 V VDD = 2.7 to 5.5 V Conditions MIN. 50 ns tCYK/2 - 17 tCYK/2 - 26 tCYK/2 - 17 tCYK/2 - 26 17 26 17 26 MAX. 30.6 s ns ns ns ns ns ns ns ns Unit Clock Timing <1> <2> <3> CLKOUT (output) <4> <5> 782 User's Manual U16889EJ1V0UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) Bus Timing (1) In multiplex bus mode (a) Read/write cycle (CLKOUT asynchronous) (TA = -40 to +85C, VDD = EVDD = AVREF0 = 4.0 to 5.5 V, 4.0 V BVDD VDD, 4.0 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (1/2) Parameter Address setup time (to ASTB) Address hold time (from ASTB) Delay time from RD to address float Data input setup time from address Data input setup time from RD Delay time from ASTB to RD, WRm Data input hold time (from RD) Address output time from RD Delay time from RD, WRm to ASTB Delay time from RD to ASTB RD, WRm low-level width ASTB high-level width Data output time from WRm Data output setup time (to WRm) Data output hold time (from WRm) WAIT setup time (to address) tSAST tHSTA tFRDA tSAID tSRID tDSTRDWR tHRDID tDRDA tDRDWRST tDRDST tWRDWRL tWSTH tDWROD tSODWR tHWROD tSAWT1 tSAWT2 WAIT hold time (from address) tHAWT1 tHAWT2 WAIT setup time (to ASTB) tSSTWT1 tSSTWT2 WAIT hold time (from ASTB) tHSTWT1 tHSTWT2 Symbol <6> <7> <8> <9> <10> <11> <12> <13> <14> <15> <16> <17> <18> <19> <20> <21> <22> <23> <24> <25> <26> <27> <28> n1 (n + tAHW)T (1 + n + tAHW)T n1 n1 (0.5 + n + tASW + tAHW)T (1.5 + n + tASW + tAHW)T (1 + tAHW)T - 32 (1 + n + tAHW)T - 32 n1 (1 + n)T - 25 T - 15 (1.5 + tASW + tAHW)T - 45 (1.5 + n + tASW + tAHW)T - 45 (0.5 + tAHW)T - 20 0 (1 + i)T - 16 0.5T - 10 (1.5 + i + tASW)T - 10 (1 + n)T - 10 (1 + tASW)T - 25 20 Conditions MIN. (0.5 + tASW)T - 23 (0.5 + tASW)T - 15 16 (2 + n + tASW + tAHW)T - 40 (1 + n + tASW + tAHW)T - 25 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks 1. tASW: Number of address setup wait clocks tAHW: Number of address hold wait clocks 2. T = 1/fCPU (fCPU: CPU operating clock frequency) 3. n: Number of wait clocks inserted in the bus cycle The sampling timing changes when a programmable wait is inserted. 4. m = 0, 1 5. i: Number of idle states inserted after a read cycle (0 or 1) 6. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. User's Manual U16889EJ1V0UD 783 CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (2/2) Parameter Address setup time (to ASTB) Address hold time (from ASTB) Delay time from RD to address float Data input setup time from address Data input setup time from RD Delay time from ASTB to RD, WRm Data input hold time (from RD) Address output time from RD Delay time from RD, WRm to ASTB Delay time from RD to ASTB RD, WRm low-level width ASTB high-level width Data output time from WRm Data output setup time (to WRm) Data output hold time (from WRm) WAIT setup time (to address) tSAST tHSTA tFRDA tSAID tSRID tDSTRDWR tHRDID tDRDA tDRDWRST tDRDST tWRDWRL tWSTH tDWROD tSODWR tHWROD tSAWT1 tSAWT2 WAIT hold time (from address) tHAWT1 tHAWT2 WAIT setup time (to ASTB) tSSTWT1 tSSTWT2 WAIT hold time (from ASTB) tHSTWT1 tHSTWT2 Symbol <6> <7> <8> <9> <10> <11> <12> <13> <14> <15> <16> <17> <18> <19> <20> <21> <22> <23> <24> <25> <26> <27> <28> n1 (n + tAHW)T (1 + n + tAHW)T n1 n1 (0.5 + n + tASW + tAHW)T (1.5 + n + tASW + tAHW)T (1 + tAHW)T - 60 (1 + n + tAHW)T - 60 n1 (1 + n)T - 40 T - 30 (1.5 + tASW + tAHW)T - 80 (1.5 + n + tASW + tAHW)T - 80 (0.5 + tAHW)T - 35 0 (1 + i)T - 32 0.5T - 20 (1.5 + i + tASW)T - 20 (1 + n)T - 20 (1 + tASW)T - 50 35 Conditions MIN. (0.5 + tASW)T - 42 (0.5 + tASW)T - 30 32 (2 + n + tASW + tAHW)T - 72 (1 + n + tASW + tAHW)T - 40 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Caution Set the following in accordance with the usage conditions of the CPU operating clock frequency (k = 0 to 3). * 70 ns < 1/fCPU < 84 ns Set an address setup wait (AWC.ASWk bit = 1). * 62.5 ns < 1/fCPU < 70 ns Set an address setup wait (ASWk bit = 1) and address hold wait (AWC.AHWk bit = 1). Remarks 1. tASW: Number of address setup wait clocks tAHW: Number of address hold wait clocks 2. T = 1/fCPU (fCPU: CPU operating clock frequency) 3. n: Number of wait clocks inserted in the bus cycle The sampling timing changes when a programmable wait is inserted. 4. m = 0, 1 5. i: Number of idle states inserted after a read cycle (0 or 1) 6. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. 784 User's Manual U16889EJ1V0UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) Read Cycle (CLKOUT Asynchronous): In Multiplex Bus Mode T1 T2 TW T3 CLKOUT (output) A16 to A23 (output) CS0 to CS3 (output) <9> AD0 to AD15 (I/O) Address Hi-Z Data <6> <7> <12> ASTB (output) <17> <13> <11> <8> <10> <14> <15> RD (output) <16> <25> <27> <26> <28> WAIT (input) <21> <23> <22> <24> Remark WR0 and WR1 are high level. User's Manual U16889EJ1V0UD 785 CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) Write Cycle (CLKOUT Asynchronous): In Multiplex Bus Mode T1 T2 TW T3 CLKOUT (output) A16 to A23 (output) CS0 to CS3 (output) AD0 to AD15 (I/O) Address Data <6> <7> ASTB (output) <17> <18> <11> <19> <14> <20> WR0 (output), WR1 (output) <16> <25> <27> <26> <28> WAIT (input) <21> <23> <22> <24> Remark RD is high level. 786 User's Manual U16889EJ1V0UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) (b) Read/write cycle (CLKOUT synchronous): In multiplex bus mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 4.0 to 5.5 V, 4.0 V BVDD VDD, 4.0 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (1/2) Parameter Delay time from CLKOUT to address Delay time from CLKOUT to address float Delay time from CLKOUT to ASTB Delay time from CLKOUT to RD, WRm Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Data output delay time from CLKOUT WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) tDKST tDKRDWR tSIDK tHKID tDKOD tSWTK tHKWT <31> <32> <33> <34> <35> <36> <37> 15 0 0 -22 15 0 19 23 0 ns ns ns ns ns ns ns tDKA tFKA Symbol <29> <30> Conditions MIN. 0 0 MAX. 19 14 Unit ns ns Remarks 1. m = 0, 1 2. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (2/2) Parameter Delay time from CLKOUT to address Delay time from CLKOUT to address float Delay time from CLKOUT to ASTB Delay time from CLKOUT to RD, WRm Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Data output delay time from CLKOUT WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) tDKST tDKRDWR tSIDK tHKID tDKOD tSWTK tHKWT <31> <32> <33> <34> <35> <36> <37> 25 0 0 -22 30 0 19 55 0 ns ns ns ns ns ns ns tDKA tFKA Symbol <29> <30> Conditions MIN. 0 0 MAX. 19 18 Unit ns ns Remarks 1. m = 0, 1 2. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. User's Manual U16889EJ1V0UD 787 CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) Read Cycle (CLKOUT Synchronous): In Multiplex Bus Mode T1 T2 TW T3 CLKOUT (output) <29> A16 to A23 (output) CS0 to CS3 (output) <33> <30> Hi-Z <34> AD0 to AD15 (I/O) Address Data <31> <31> ASTB (output) <32> <32> RD (output) WAIT (input) <36> <37> <36> <37> Remark WR0 and WR1 are high level. 788 User's Manual U16889EJ1V0UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) Write Cycle (CLKOUT Synchronous): In Multiplex Bus Mode T1 T2 TW T3 CLKOUT (output) <29> A16 to A23 (output) CS0 to CS3 (output) <35> AD0 to AD15 (I/O) Address <31> Data <31> ASTB (output) WR0 (output), WR1 (output) <32> <32> WAIT (input) <36> <37> <36> <37> Remark RD is high level. User's Manual U16889EJ1V0UD 789 CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) (2) In separate bus mode (a) Read cycle (CLKOUT asynchronous): In separate bus mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 4.0 to 5.5 V, 4.0 V BVDD VDD, 4.0 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (1/2) Parameter Address setup time (to RD) Address hold time (from RD) RD low-level width Data setup time (to RD) Data hold time (from RD) Data setup time (to address) WAIT setup time (to RD) tSARD tHARD tWRDL tSISD tHISD tSAID tSRDWT1 tSRDWT2 WAIT hold time (from RD) tHRDWT1 tHRDWT2 WAIT setup time (to address) tSAWT1 tSAWT2 WAIT hold time (from address) tHAWT1 tHAWT2 Symbol <38> <39> <40> <41> <42> <43> <44> <45> <46> <47> <48> <49> <50> <51> (n + tASW + tAHW)T (1 + n + tASW + tAHW)T (n - 0.5 + tAHW)T (n + 0.5 + tAHW)T (1 + tASW + tAHW)T - 65 (1 + n + tASW + tAHW)T - 65 Conditions MIN. (0.5 + tASW)T - 50 i - 13 (1.5 + n + tAHW)T - 15 30 0 (2 + n + tASW + tAHW)T - 65 (0.5 + tAHW)T - 32 (0.5 + n + tAHW)T - 32 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Caution Set the following in accordance with the usage conditions of the CPU operating clock frequency (k = 0 to 3). * 1/fCPU < 100 ns Set an address setup wait (ASWk bit = 1). Remarks 1. tASW: Number of address setup wait clocks tAHW: Number of address hold wait clocks 2. T = 1/fCPU (fCPU: CPU operating clock frequency) 3. n: Number of wait clocks inserted in the bus cycle The sampling timing changes when a programmable wait is inserted 4. i: Number of idle states inserted after a read cycle (0 or 1) 5. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. 790 User's Manual U16889EJ1V0UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (2/2) Parameter Address setup time (to RD) Address hold time (from RD) RD low-level width Data setup time (to RD) Data hold time (from RD) Data setup time (to address) WAIT setup time (to RD) Symbol tSARD tHARD tWRDL tSISD tHISD tSAID tSRDWT1 tSRDWT2 WAIT hold time (from RD) tHRDWT1 tHRDWT2 WAIT setup time (to address) tSAWT1 tSAWT2 WAIT hold time (from address) tHAWT1 tHAWT2 <38> <39> <40> <41> <42> <43> <44> <45> <46> <47> <48> <49> <50> <51> (n + tASW + tAHW)T (1 + n + tASW + tAHW)T (n - 0.5 + tAHW)T (n + 0.5 + tAHW)T (1 + tASW + tAHW)T - 130 (1 + n + tASW + tAHW)T - 130 Conditions MIN. (0.5 + tASW)T - 100 i - 26 (1.5 + n + tAHW)T - 30 60 0 (2 + n + tASW + tAHW)T - 120 (0.5 + tAHW)T - 50 (0.5 + n + tAHW)T - 50 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Caution Set the following in accordance with the usage conditions of the CPU operating clock frequency (k = 0 to 3). * 1/fCPU < 200 ns Set an address setup wait (ASWk bit = 1). Remarks 1. tASW: Number of address setup wait clocks tAHW: Number of address hold wait clocks 2. T = 1/fCPU (fCPU: CPU operating clock frequency) 3. n: Number of wait clocks inserted in the bus cycle The sampling timing changes when a programmable wait is inserted. 4. i: Number of idle states inserted after a read cycle (0 or 1) 5. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. User's Manual U16889EJ1V0UD 791 CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) Read Cycle (CLKOUT Asynchronous): In Separate Bus Mode T1 TW T2 CLKOUT (output) CS0 to CS3 (output) A0 to A23 (output) <39> <43> AD0 to AD15 (I/O) Hi-Z <42> <41> <40> RD (output) <47> <45> <46> <44> WAIT (input) <48> <50> <49> <51> Hi-Z <38> Remark WR0 and WR1 are high level. 792 User's Manual U16889EJ1V0UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) (b) Write cycle (CLKOUT asynchronous): In separate bus mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 4.0 to 5.5 V, 4.0 V BVDD VDD, 4.0 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (1/2) Parameter Address setup time (to WRm) Address hold time (from WRm) WRm low-level width Data output time from WRm Data setup time (to WRm) Data hold time (from WRm) Data setup time (to address) WAIT setup time (to WRm) Symbol tSAWR tHAWR tWWRL tDOSDW tSOSDW tHOSDW tSAOD tSWRWT1 tSWRWT2 WAIT hold time (from WRm) tHWRWT1 tHWRWT2 WAIT setup time (to address) tSAWT1 tSAWT2 WAIT hold time (from address) tHAWT1 tHAWT2 <52> <53> <54> <55> <56> <57> <58> <59> <60> <61> <62> <63> <64> <65> <66> (n + tASW + tAHW)T (1 + n + tASW + tAHW)T 0 nT (1 + tASW + tAHW)T - 45 (1 + n + tASW + tAHW)T - 45 Conditions MIN. (1 + tASW + tAHW)T - 60 0.5T - 10 (0.5 + n)T - 10 -5 (0.5 + n)T - 20 0.5T - 20 (1 + tASW + tAHW)T - 30 30 nT - 30 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Caution Set the following in accordance with the usage conditions of the CPU operating clock frequency (k = 0 to 3). * 1/fCPU < 60 ns Set an address setup wait (ASWk bit = 1). Remarks 1. m = 0, 1 2. tASW: Number of address setup wait clocks tAHW: Number of address hold wait clocks 3. T = 1/fCPU (fCPU: CPU operating clock frequency) 4. n: Number of wait clocks inserted in the bus cycle The sampling timing changes when a programmable wait is inserted. 5. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. User's Manual U16889EJ1V0UD 793 CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (2/2) Parameter Address setup time (to WRm) Address hold time (from WRm) WRm low-level width Data output time from WRm Data setup time (to WRm) Data hold time (from WRm) Data setup time (to address) WAIT setup time (to WRm) Symbol tSAWR tHAWR tWWRL tDOSDW tSOSDW tHOSDW tSAOD tSWRWT1 tSWRWT2 WAIT hold time (from WRm) tHWRWT1 tHWRWT2 WAIT setup time (to address) tSAWT1 tSAWT2 WAIT hold time (from address) tHAWT1 tHAWT2 <52> <53> <54> <55> <56> <57> <58> <59> <60> <61> <62> <63> <64> <65> <66> (n + tASW + tAHW)T (1 + n + tASW + tAHW)T 0 nT (1 + tASW + tAHW)T - 100 (1 + n + tASW + tAHW)T - 100 Conditions MIN. (1 + tASW + tAHW)T - 100 0.5T - 10 (0.5 + n)T - 10 -5 (0.5 + n)T - 35 0.5T - 35 (1 + tASW + tAHW)T - 55 50 nT - 50 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Caution Set the following in accordance with the usage conditions of the CPU operating clock frequency (k = 0 to 3). * 1/fCPU < 100 ns Set an address setup wait (ASWk bit = 1). Remarks 1. m = 0, 1 2. tASW: Number of address setup wait clocks tAHW: Number of address hold wait clocks 3. T = 1/fCPU (fCPU: CPU operating clock frequency) 4. n: Number of wait clocks inserted in the bus cycle The sampling timing changes when a programmable wait is inserted. 5. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. 794 User's Manual U16889EJ1V0UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) Write Cycle (CLKOUT Asynchronous): In Separate Bus Mode T1 TW T2 CLKOUT (output) CS0 to CS3 (output) A0 to A23 (output) <53> <58> AD0 to AD15 (I/O) Hi-Z <55> <52> <57> <56> <54> WR0, WR1 (output) <62> <60> <59> <61> WAIT (input) <63> <65> <64> <66> Hi-Z Remark RD is high level. User's Manual U16889EJ1V0UD 795 CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) (c) Read cycle (CLKOUT synchronous): In separate bus mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 4.0 to 5.5 V, 4.0 V BVDD VDD, 4.0 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (1/2) Parameter Delay time from CLKOUT to address, CS Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Delay time from CLKOUT to RD WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) tSISDK tHKISD tDKSR tSWTK tHKWT <68> <69> <70> <71> <72> 15 0 0 20 0 6 ns ns ns ns ns Symbol tDKSA <67> Conditions MIN. 0 MAX. 35 Unit ns Remark The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (2/2) Parameter Delay time from CLKOUT to address, CS Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Delay time from CLKOUT to RD WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) tSISDK tHKISD tDKSR tSWTK tHKWT <68> <69> <70> <71> <72> 30 0 0 40 0 10 ns ns ns ns ns Symbol tDKSA <67> Conditions MIN. 0 MAX. 65 Unit ns Remark The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. 796 User's Manual U16889EJ1V0UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) Read Cycle (CLKOUT Synchronous, 1 Wait): In Separate Bus Mode T1 TW T2 CLKOUT (output) <67> <67> CS0 to CS3 (output) A0 to A23 (output) <68> Hi-Z <69> Hi-Z <70> AD0 to AD15 (I/O) <70> RD (output) <71> <72> <71> <72> WAIT (input) Remark WR0 and WR1 are high level. User's Manual U16889EJ1V0UD 797 CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) (d) Write cycle (CLKOUT synchronous): In separate bus mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 4.0 to 5.5 V, 4.0 V BVDD VDD, 4.0 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (1/2) Parameter Delay time from CLKOUT to address, CS Data output delay time from CLKOUT Delay time from CLKOUT to WRm WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) tDKSW tSWTK tHKWT <75> <76> <77> 0 20 0 10 ns ns ns tDKSD <74> 0 10 ns Symbol tDKSA <73> Conditions MIN. 0 MAX. 35 Unit ns Remarks 1. m = 0, 1 2. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (2/2) Parameter Delay time from CLKOUT to address, CS Data output delay time from CLKOUT Delay time from CLKOUT to WRm WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) tDKSW tSWTK tHKWT <75> <76> <77> 0 40 0 15 ns ns ns tDKSD <74> 0 15 ns Symbol tDKSA <73> Conditions MIN. 0 MAX. 65 Unit ns Remarks 1. m = 0, 1 2. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. 798 User's Manual U16889EJ1V0UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) Write Cycle (CLKOUT Synchronous): In Separate Bus Mode T1 TW T2 CLKOUT (output) <73> <73> CS0 to CS3 (output) A0 to A23 (output) <74> Hi-Z <74> Hi-Z AD0 to AD15 (I/O) <75> <75> WR0, WR1 (output) <76> <77> <76> <77> WAIT (input) Remark RD is high level. User's Manual U16889EJ1V0UD 799 CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) (3) Bus hold (a) CLKOUT asynchronous (TA = -40 to +85C, VDD = EVDD = AVREF0 = 4.0 to 5.5 V, 4.0 V BVDD VDD, 4.0 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (1/2) Parameter HLDRQ high-level width HLDAK low-level width Delay time from HLDAK to bus output Delay time from HLDRQ to HLDAK Delay time from HLDRQ to HLDAK tWHQH tWHAL tDHAC tDHQHA1 tDHQHA2 Symbol <78> <79> <80> <81> <82> 0.5T Conditions MIN. T + 10 T - 15 -40 (2n + 7.5)T + 40 1.5T + 40 MAX. Unit ns ns ns ns ns Remarks 1. T = 1/fCPU (fCPU: CPU operating clock frequency) 2. n: Number of wait clocks inserted in the bus cycle The sampling timing changes when a programmable wait is inserted. 3. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (2/2) Parameter HLDRQ high-level width HLDAK low-level width Delay time from HLDAK to bus output Delay time from HLDRQ to HLDAK Delay time from HLDRQ to HLDAK tWHQH tWHAL tDHAC tDHQHA1 tDHQHA2 Symbol <78> <79> <80> <81> <82> 0.5T Conditions MIN. T + 10 T - 15 -80 (2n + 7.5)T + 70 1.5T + 70 MAX. Unit ns ns ns ns ns Remarks 1. T = 1/fCPU (fCPU: CPU operating clock frequency) 2. n: Number of wait clocks inserted in the bus cycle The sampling timing changes when a programmable wait is inserted. 3. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. 800 User's Manual U16889EJ1V0UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) Bus Hold (CLKOUT Asynchronous) TI CLKOUT (output) TH TH TH TI <78> HLDRQ (input) <81> <82> HLDAK (output) <79> Address bus (output) Data bus (I/O) Hi-Z <80> CS0 to CS3 (output) Hi-Z ASTB (output) Hi-Z RD (output), WR0 (output), WR1 (output) Hi-Z User's Manual U16889EJ1V0UD 801 CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) (b) CLKOUT synchronous (TA = -40 to +85C, VDD = EVDD = AVREF0 = 4.0 to 5.5 V, 4.0 V BVDD VDD, 4.0 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (1/2) Parameter HLDRQ setup time (to CLKOUT) HLDRQ hold time (from CLKOUT) Delay time from CLKOUT to bus float Delay time from CLKOUT to HLDAK tSHQK tHKHQ tDKF tDKHA Symbol <83> <84> <85> <86> Conditions MIN. 15 0 20 20 MAX. Unit ns ns ns ns Remark The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) (2/2) Parameter HLDRQ setup time (to CLKOUT) HLDRQ hold time (from CLKOUT) Delay time from CLKOUT to bus float Delay time from CLKOUT to HLDAK tSHQK tHKHQ tDKF tDKHA Symbol <83> <84> <85> <86> Conditions MIN. 25 0 40 40 MAX. Unit ns ns ns ns Remark The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1. 802 User's Manual U16889EJ1V0UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) Bus Hold (CLKOUT Synchronous) T2 CLKOUT (output) T3 TI TH TH TH TI <83> <84> <83> HLDRQ (input) <86> <86> HLDAK (output) <85> Address bus (output) Data bus (I/O) Hi-Z CS0 to CS3 (output) Hi-Z ASTB (output) Hi-Z RD (output), WR0 (output), WR1 (output) Hi-Z User's Manual U16889EJ1V0UD 803 CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) Basic Operation (1) Reset/external interrupt timing (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter RESET low-level width Symbol tWRSL1 tWRSL2 <87> <88> Conditions Reset in power-on status Power-on-reset when REGC = VDD Note tVR > 150 s tVR 150 s NMI high-level width NMI low-level width INTPn high-level width INTPn low-level width tWNIH tWNIL tWITH tWITL <89> <90> <91> <92> Analog noise elimination Analog noise elimination n = 0 to 6 (analog noise elimination) n = 0 to 6 (analog noise elimination) MIN. 2 2 10 40 1 1 600 600 MAX. Unit s s s s s s ns ns Note Power-on-reset when REGC = Capacity Remarks 1. tVR: Time required for VDD to reach 0 V to 4.0 V (= operation lower-limit voltage) 2. The above specification shows the pulse width that is accurately detected as a valid edge. If a pulse narrower than the above specification is input, therefore, it may also be detected as a valid edge. Reset/Interrupt VDD tVR RESET (input) <88> <87> <89> <90> NMI (input) <91> <92> INTPn (input) Remark n = 0 to 6 804 User's Manual U16889EJ1V0UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) Timer Timing (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter TI0n high-level width Symbol tTI0H <93> Conditions REGC = VDD = 5 V 10% MIN. 2/fsam + 100 Note MAX. Unit ns TI0n low-level width tTI0L <94> REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V 2/fsam + 200 Note ns TI5m high-level width TI5m low-level width tTI5H tTI5L <95> <96> REGC = VDD = 5 V 10% REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V 50 100 ns ns Note fsam = Timer count clock However, fsam = fXX/4 when the TI0n valid edge is selected as the timer count clock. Remarks 1. n = 00, 01, 10, 11, 20, 21, 30, 31, 40, 41, 50, 51 m = 0, 1 2. The above specification shows the pulse width that is accurately detected as a valid edge. If a pulse narrower than the above specification is input, therefore, it may also be detected as a valid edge. Timer Input Timing <93>/<95> TI0n (input) TI5m (input) <94>/<96> Remark n = 00, 01, 10, 11, 20, 21, 30, 31, 40, 41, 50, 51 m = 0, 1 UART Timing (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Transmit rate ASCK0 frequency REGC = VDD = 5 V 10% REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V Symbol Conditions MIN. MAX. 312.5 12 6 Unit kbps MHz MHz User's Manual U16889EJ1V0UD 805 CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) CSI0 Timing (1) Master mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter SCK0n cycle time tKCY1 Symbol <99> Conditions REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V SCK0n high-/low-level width SI0n setup time (to SCK0n) tKH1, tKL1 tSIK1 <100> <101> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V SI0n hold time (from SCK0n) tKSI1 <102> REGC = VDD = 5 V 10% REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V Delay time from SCK0n to SO0n output tKSO1 <103> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V 30 60 ns ns 30 50 ns ns tKCY1/2 - 30 30 50 ns ns ns MIN. 200 400 MAX. Unit ns ns Remark n = 0 to 2 (2) Slave mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter SCK0n cycle time tKCY2 Symbol <99> Conditions REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V SCK0n high-/low-level width tKH2, tKL2 <100> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V SI0n setup time (to SCK0n) tSIK2 <101> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V SI0n hold time (from SCK0n) tKSI2 <102> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V Delay time from SCK0n to SO0n output tKSO2 <103> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V 50 100 ns ns 30 60 ns ns 30 60 ns ns 45 90 ns ns MIN. 200 400 MAX. Unit ns ns Remark n = 0 to 2 806 User's Manual U16889EJ1V0UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) <99> <100> SCK0n (I/O) <100> <101> <102> Hi-Z SI0n (input) Input data Hi-Z <103> SO0n (output) Output data Remarks 1. When transmit/receive type 1 (CSICn.CKPn, CSICn.DAPn bits = 00) 2. n = 0 to 2 User's Manual U16889EJ1V0UD 807 CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) CSIA Timing (1) Master mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter SCKAn cycle time tKCY3 Symbol <99> Conditions REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V SCKAn high-/low-level width tKH3, tKL3 SIAn setup time (to SCKAn) tSIK3 <101> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V SIAn hold time (from SCKAn) tKSI3 <102> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V Delay time from SCKAn to SOAn output tKSO3 <103> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V 30 60 ns ns 30 60 ns ns 30 60 ns ns <100> tKCY3/2 - 30 ns MIN. 500 1000 MAX. Unit ns ns Remark n = 0, 1 (2) Slave mode (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter SCKAn cycle time tKCY4 Symbol <99> Conditions REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V SCKAn high-/low-level width SIAn setup time (to SCKAn) tKH4, tKL4 tSIK4 <100> <101> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V SIAn hold time (from SCKAn) tKSI4 <102> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V Delay time from SCKAn to SOAn output tKSO4 <103> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 2.7 to 5.5 V tCY x 2 + 30 tCY x 2 + 60 Note MIN. 840 1700 tKCY4/2 - 30 50 100 MAX. Unit ns ns ns ns ns 50 100 ns ns ns ns Note Note tCY: Internal clock output cycle fXX (CSISn.CKSAn1, CSISn.CKSAn0 bits = 00), fXX/2 (CKSAn1, CKSAn0 bits = 01) fXX/22 (CKSAn1, CKSAn0 bits = 10), fXX/23 (CKSAn1, CKSAn0 bits = 11) Remark n = 0, 1 808 User's Manual U16889EJ1V0UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) <99> <100> SCKAn (I/O) <100> <101> <102> Hi-Z SIAn (input) Input data Hi-Z <103> SOAn (output) Output data Remark n = 0, 1 User's Manual U16889EJ1V0UD 809 CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) I2C Bus Mode (Y Products (Products with On-Chip I2C) Only) (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Normal Mode MIN. SCLn clock frequency Bus free time (Between start and stop conditions) Hold time Note 1 High-Speed Mode MIN. 0 1.3 MAX. 400 - Unit MAX. 100 - fCLK tBUF <104> 0 4.7 kHz s s s s s s s ns ns tHD:STA tLOW tHIGH tSU:STA <105> <106> <107> <108> <109> 4.0 4.7 4.0 4.7 - - - - - - - 1000 0.6 1.3 0.6 0.6 - Note 2 - - - - - Note 3 SCLn clock low-level width SCLn clock high-level width Setup time for start/restart conditions Data hold time CBUS compatible master I C mode Data setup time SDAn and SCLn signal rise time 2 tHD:DAT 5.0 Note 2 0 tSU:DAT tR <110> <111> 0 0.9 250 - - 4.0 - - 100 Note 4 - 300 20 + 0.1Cb Note 5 SDAn and SCLn signal fall time tF <112> 300 - - 20 + 0.1Cb Note 5 300 - 50 ns Stop condition setup time Pulse width of spike suppressed by input filter Capacitance load of each bus line tSU:STO tSP <113> <114> 0.6 0 - s ns Cb 400 400 pF Notes 1. At the start condition, the first clock pulse is generated after the hold time. 2. The system requires a minimum of 300 ns hold time internally for the SDAn signal (at VIHmin. of SCLn signal) in order to occupy the undefined area at the falling edge of SCLn. 3. If the system does not extend the SCLn signal low hold time (tLOW), only the maximum data hold time (tHD:DAT) needs to be satisfied. 4. The high-speed mode I2C bus can be used in the normal-mode I2C bus system. In this case, set the highspeed mode I C bus so that it meets the following conditions. * If the system does not extend the SCLn signal's low state hold time: tSU:DAT 250 ns * If the system extends the SCLn signal's low state hold time: Transmit the following data bit to the SDAn line prior to the SCLn line release (tRmax. + tSU:DAT = 1000 + 250 = 1250 ns: Normal mode I2C bus specification). 5. Cb: Total capacitance of one bus line (unit: pF) Remark n = 0, 1 2 810 User's Manual U16889EJ1V0UD CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) I2C Bus Mode (Y Products (Products with On-Chip I2C) Only) <106> <107> SCLn (I/O) <112> <111> <105> <109> <110> <108> <105> <114> <113> SDAn (I/O) <104> <111> <112> Stop condition Start condition Restart condition Stop condition Remark n = 0, 1 User's Manual U16889EJ1V0UD 811 CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) A/D Converter (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Resolution Overall error Note 1 Symbol Conditions MIN. 10 TYP. 10 0.2 0.3 MAX. 10 0.4 0.6 100 100 0.4 0.6 0.4 0.6 2.5 4.5 1.5 2.0 Unit bit %FSR %FSR 4.0 AVREF0 5.5 V 2.7 AVREF0 4.0 V Conversion time tCONV 4.0 AVREF0 5.5 V 2.7 AVREF0 4.0 V 14 17 s s %FSR %FSR %FSR %FSR LSB LSB LSB LSB V mA Zero-scale error Note 1 4.0 AVREF0 5.5 V 2.7 AVREF0 4.0 V Full-scale error Note 1 4.0 AVREF0 5.5 V 2.7 AVREF0 4.0 V Non-linearity error Note 2 4.0 AVREF0 5.5 V 2.7 AVREF0 4.0 V Differential linearity error Note 2 4.0 AVREF0 5.5 V 2.7 AVREF0 4.0 V VIAN IAREF0 When using A/D converter When not using A/D converter 0 1.0 1.0 Analog input voltage AVREF0 current AVREF0 2.0 10 A Notes 1. Excluding quantization error (0.05 %FSR). 2. Excluding quantization error (0.5 LSB). Remark LSB: Least Significant Bit FSR: Full Scale Range D/A Converter (TA = -40 to +85C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Resolution Overall error Notes 1, 2 Symbol Conditions MIN. TYP. MAX. 8 Unit bit %FSR %FSR %FSR Load condition = 2 M Load condition = 4 M Load condition = 10 M 1.2 0.8 0.6 10 15 8 1.5 1.0 3.0 10 Settling time Note 2 C = 30 pF VDD = 4.5 to 5.5 V VDD = 2.7 to 4.5 V s s k mA Output resistance AVREF1 current Note 3 RO IAVREF1 Output data: DACSn register = 55H During D/A conversion When D/A conversion stopped Note 4 A Notes 1. Excluding quantization error (0.2 %FSR). 2. R is the D/A converter output pin load resistance, and C is the D/A converter output pin load capacitance. 3. Value of 1 channel of D/A converter 4. Value of 2 channels of D/A converter Remark n = 0, 1 User's Manual U16889EJ1V0UD 812 CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) Flash Memory Programming Characteristics (TA = 10 to 40C, VDD = EVDD = AVREF0 = 2.7 to 5.5 V, 2.7 V BVDD VDD, 2.7 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) (1) Basic characteristics Parameter Programming operation frequency VPP supply voltage VDD supply current VPP2 IDD During flash memory programming When VPP = VPP2, fXX = 10 MHz, VDD = 5.5 V VPP supply current Step erase time Overall erase time Writeback time Number of writebacks Number of erases/writebacks Step write time Overall write time per word IPP tER tERA tWB CWB CERWB tWR tWRW Note 5 When step write time = 50 s (1 word = 4 bytes), Note 6 Number of rewrites per area CERWR 1 erase + 1 write after erase = 1 rewrite, Note 7 20 Count/area 49 49 50 When VPP = VPP2 Note 1 When step erase time = 0.2 s, Note 2 Note 3 When writeback time = 1 ms, Note 4 4.9 5.0 0.196 0.2 100 0.204 20 5.1 100 16 51 510 mA s s/area ms Times Times 9.7 10.0 10.3 60 V mA Symbol Conditions MIN. 2 TYP. MAX. 10 Unit MHz s s/word Notes 1. The recommended setting value of the step erase time is 0.2 s. 2. The prewrite time prior to erasure and the erase verify time (writeback time) are not included. 3. The recommended setting value of the writeback time is 5.0 ms. 4. Writeback is executed once by the issuance of the writeback command. Therefore, the retry count must be the maximum value minus the number of commands issued. 5. The recommended setting value of the step writing time is 50 s. 6. 100 s is added to the actual writing time per word. The internal verify time during and after the writing is not included. 7. When writing initially to shipped products, it is counted as one rewrite for both "erase to write" and "write only". Example (P: Write, E: Erase) Shipped product PEPEP: 3 rewrites Shipped product E PEPEP: 3 rewrites User's Manual U16889EJ1V0UD 813 CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) (2) Serial write operation characteristics Parameter Setup time from VDD to VPP Setup time from VPP to RESET Count start time from RESET to VPPH Count complete time VPP counter high-/low-level width VPP pulse low-level input voltage VPP pulse high-level input voltage Symbol tDPRSR tPSRRF tRFOF tCOUNT tCH/tCL VPPL VPPH 8 0.8VDD 9.7 10.0 1.2VDD 10.3 Conditions MIN. 15 10 2 20 TYP. MAX. Unit s s s ms s V V Flash Write Mode Setting Timing VDD VDD 0V VPPH VPP VDD VPPL tPSRRF tCOUNT tCL tDRPSR tRFCF tCH EVDD RESET (input) 0V 814 User's Manual U16889EJ1V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (TARGET) (A1) grade products are as follows. PD703216(A1), 703216Y(A1), 703217(A1), 703217Y(A1) Absolute Maximum Ratings (TA = 25C) (1/2) Parameter Supply voltage Symbol VDD BVDD EVDD AVREF0 AVREF1 Conditions VDD = EVDD = AVREF0 BVDD VDD VDD = EVDD = AVREF0 VDD = EVDD = AVREF0 AVREF1 VDD (D/A output mode) AVREF1 = AVREF0 = VDD (port mode) VSS AVSS BVSS EVSS Input voltage VI1 VSS = EVSS = BVSS = AVSS VSS = EVSS = BVSS = AVSS VSS = EVSS = BVSS = AVSS VSS = EVSS = BVSS = AVSS P00 to P06, P30 to P35, P38, P39, P40 to P42, P50 to P55, P60 to P613, P80, P81, P90 to P915, RESET VI2 PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7, PDL0 to PDL15, PDH0 to PDH7 VI3 VI4 VI5 Analog input voltage VIAN P10, P11 P36, P37, P614, P615 X1, X2, XT1, XT2 P70 to P715 -0.3 to AVREF1 + 0.3 -0.3 to +13 Note 2 Note 1 Ratings -0.3 to +6.5 -0.3 to VDD + 0.3 -0.3 to +6.5 -0.3 to +6.5 -0.3 to VDD + 0.3 -0.3 to +0.3 -0.3 to +0.3 -0.3 to +0.3 -0.3 to +0.3 -0.3 to EVDD + 0.3 Note 1 Note 1 Note 1 Unit V V V V V V V V V V -0.3 to BVDD + 0.3 Note 1 V V V V V -0.3 to VDD + 0.3 Note 1 -0.3 to AVREF0 + 0.3 Note 1 Notes 1. Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage. 2. When an on-chip pull-up resistor is not specified by a mask option. The same as VI1 when a pull-up resistor is specified. User's Manual U16889EJ1V0UD 815 CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (TARGET) Absolute Maximum Ratings (TA = 25C) (2/2) Parameter Output current, low Symbol IOL Conditions P00 to P06, P10, P11, P30 to P35, P40 to P42, P50 to P55, P60 to P613, P80, P81, P90 to P915, PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7, PDL0 to PDL15, PDH0 to PDH7 P36 to P39, P614, P615 P00 to P06, P30 to P39, P40 to P42 P50 to P55, P60 to P615, P80, P81, P90 to P915 PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7 PDL0 to PDL15, PDH0 to PDH7 Output current, high IOH Per pin P00 to P06, P30 to P35, P40 to P42 P50 to P55, P60 to P613, P80, P81, P90 to P915 PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7 PDL0 to PDL15, PDH0 to PDH7 P10, P11 Operating ambient temperature Storage temperature Tstg -65 to +150 C TA Total of all pins: -48 mA Total of all pins: -48 mA Per pin -24 -8 -40 to +110 C mA Total of all pins: 56 mA Total of all pins: 56 mA 28 -8 -24 -24 -24 mA mA mA mA 28 mA 24 28 28 mA mA Per pin Ratings 16 Unit mA Cautions 1. Do not directly connect the output (or I/O) pins of IC products to each other, or to VDD, VCC, and GND. Open-drain pins or open-collector pins, however, can be directly connected to each other. Direct connection of the output pins between an IC product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Capacitance (TA = 25C, VDD = EVDD = AVREF0 = BVDD = AVREF1 = VSS = EVSS = BVSS = AVSS = 0 V) Parameter Input capacitance I/O capacitance Symbol CI CIO fX = 1 MHz Unmeasured pins returned to 0 V Conditions P70 to P715 Note P36 to P39, P614, P615 MIN. TYP. MAX. 15 15 20 Unit pF pF pF Note P00 to P06, P10, P11, P30 to P35, P40 to P42, P50 to P55, P60 to P613, P80, P81, P90 to P915, PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7, PDL0 to PDL15, PDH0 to PDH7 Remark fX: Main clock oscillation frequency User's Manual U16889EJ1V0UD 816 CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (TARGET) Operating Conditions (TA = -40 to +110C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Internal system clock frequency Symbol fCLK Conditions REGC = VDD = 5 V 10% In PLL mode (fX = 2 to 5 MHz) REGC = Capacity, VDD = 4.0 to 5.5 V In PLL mode (fX = 2 to 4 MHz) REGC = VDD = 3.5 to 5.5 V In PLL mode (fX = 2 to 3 MHz) REGC = VDD = 3.5 to 5.5 V REGC = VDD = 3.5 to 5.5 V, operating with subclock 0.0625 32.768 10 MHz kHz 0.25 12 MHz 0.25 16 MHz MIN. 0.25 TYP. MAX. 20 Unit MHz Remark fX: Main clock oscillation frequency Internal System Clock Frequency vs. Supply Voltage 100 When REGC = Capacity Internal system clock frequency fCLK [MHz] 20.0 16.0 12.0 10.0 1.0 0.1 0.032 0.01 2.0 3.0 3.5 4.0 5.0 6.0 Supply voltage VDD [V] PLL Characteristics (TA = -40 to +110C, VDD = 3.5 to 5.5 V, VSS = 0 V) Parameter Input frequency Output frequency Lock time Symbol fX fXX tPLL After VDD reaches 3.5 V (MIN.) Conditions MIN. 2 8 TYP. MAX. 5 20 200 Unit MHz MHz s User's Manual U16889EJ1V0UD 817 CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (TARGET) Main Clock Oscillator Characteristics (TA = -40 to +110C, VDD = 3.5 to 5.5 V, VSS = 0 V) Resonator Ceramic resonator X1 X2 Recommended Circuit Parameter Oscillation frequency (fX) Note 1 Conditions MIN. 2 TYP. MAX. 10 Unit MHz Oscillation stabilization time Note 2 After reset is released After STOP mode is released 2 /fX 15 s Note 3 s Crystal resonator X1 X2 Oscillation frequency (fX) Note 1 2 15 10 MHz Oscillation stabilization time Note 2 After reset is released After STOP mode is released 2 /fX s Note 3 s External clock X1 X2 X1, X2 input frequency (fX) REGC = VDD Duty = 50% 5% 2 10 MHz External clock Notes 1. Indicates only oscillator characteristics. 2. Time required to stabilize the resonator after reset or STOP mode is released. 3. The value differs depending on the OSTS register settings. Cautions 1. When using the main clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main clock is stopped and the device is operating on the subclock, wait until the oscillation stabilization time has been secured by the program before switching back to the main clock. 818 User's Manual U16889EJ1V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (TARGET) Subclock Oscillator Characteristics (TA = -40 to +110C, VDD = 3.5 to 5.5 V, VSS = 0 V) Resonator Crystal resonator XT1 XT2 Recommended Circuit Parameter Oscillation frequency (fXT) Note 1 Conditions MIN. 32 TYP. 32.768 MAX. 35 Unit kHz Oscillation stabilization time Note 2 10 s External clock XT1 XT2 XT1 input frequency (fXT) Note 1 REGC = VDD 32 35 kHz Duty = 50% 5% External clock Notes 1. Indicates only oscillator characteristics. 2. Time required from when VDD reaches oscillation voltage range (3.5 V (MIN.)) to when the crystal resonator stabilizes. Cautions 1. When using the subclock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subclock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the main clock oscillator. Particular care is therefore required with the wiring method when the subclock is used. User's Manual U16889EJ1V0UD 819 CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (TARGET) DC Characteristics (TA = -40 to +110C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) (1/4) Parameter Output current, high Symbol IOH1 Conditions Per pin for P00 to P06, P10, P11, P30 to P35, P40 to P42, P50 to P55, P60 to P613, P80, P81, P90 to P915 Total of P00 to P06, P30 to P35, P40 to P42 Total of P50 to P55, P60 to P613, P80, P81, P90 to P915 IOH2 EVDD = 4.0 to 5.5 V EVDD = 3.5 to 5.5 V EVDD = 4.0 to 5.5 V EVDD = 3.5 to 5.5 V -24 -12 -24 -12 -4.0 -24 -12 -24 -12 8 mA mA mA mA mA MAX. -4.0 Unit mA Per pin for PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7, PDH0 to PDH7, PDL0 to PDL15 Total of PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7 Total of PDL0 to PDL15, PDH0 to PDH7 BVDD = 4.0 to 5.5 V BVDD = 3.5 to 5.5 V BVDD = 4.0 to 5.5 V BVDD = 3.5 to 5.5 V mA mA mA mA mA Output current, low IOL1 Per pin for P00 to P06, P10, P11, P30 to P35, P40 to P42, P50 to P55, P60 to P613, P80, P81, P90 to P915 Per pin for P36 to P39 EVDD = 4.0 to 5.5 V EVDD = 3.5 to 5.5 V Per pin for P614, P615 EVDD = 4.0 to 5.5 V EVDD = 3.5 to 5.5 V Total of P00 to P06, P30 to P37, P40 to P42 Total of P38, P39, P50 to P55, P60 to P615, P80, P81, P90 to P915 12 6.4 8 4 24 24 mA mA mA mA mA mA IOL2 Per pin for PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7, PDH0 to PDH7, PDL0 to PDL15 Total of PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7 Total of PDL0 to PDL15, PDH0 to PDH7 8 mA 24 mA 24 mA 820 User's Manual U16889EJ1V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (TARGET) DC Characteristics (TA = -40 to +110C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) (2/4) Parameter Input voltage, high Symbol VIH1 VIH2 VIH3 VIH4 VIH5 VIH6 VIH7 Input voltage, low VIL1 VIL2 VIL3 VIL4 VIL5 VIL6 VIL7 Note 1 Note 2 Note 3 P70 to P715 P10, P11 Note 4 Conditions MIN. 0.7EVDD 0.8EVDD 0.7BVDD 0.7AVREF0 0.7AVREF1 0.7EVDD VDD - 0.5 EVSS EVSS BVSS AVSS AVSS EVSS VSS TYP. MAX. EVDD EVDD BVDD AVREF0 AVREF1 12 Note 5 Unit V V V V V V V V V V V V V V P36, P37, P614, P615 X1, X2, XT1, XT2 Note 1 Note 2 Note 3 P70 to P715 P10, P11 Note 4 VDD 0.3EVDD 0.2EVDD 0.3BVDD 0.3AVREF0 0.3AVREF1 0.3EVDD 0.4 P36, P37, P614, P615 X1, X2, XT1, XT2 Notes 1. P00, P01, P30, P41, P60 to P65, P67, P611, P98, P911 and their alternate-function pins. 2. RESET, P02 to P06, P31 to P35, P38, P39, P40, P42, P50 to P55, P66, P68 to P610, P612, P613, P80, P81, P90 to P97, P99, P910, P912 to P915 and their alternate-function pins. 3. PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7, PDL0 to PDL15, PDH0 to PDH7 and their alternate-function pins. 4. When used as port pins, set AVREF1 = AVREF0 = VDD. 5. When an on-chip pull-up resistor is not specified by a mask option. EVDD when a pull-up resistor is specified. User's Manual U16889EJ1V0UD 821 CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (TARGET) DC Characteristics (TA = -40 to +110C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) (3/4) Parameter Output voltage, high Symbol VOH1 Note 1 Conditions IOH = -1.6 mA, EVDD = 4.0 to 5.5 V Note 2 IOH = -0.08 mA, EVDD = 3.5 to 5.5 V VOH2 Note 3 IOH = -1.6 mA, BVDD = 4.0 to 5.5 V Note 4 Note 5 MIN. EVDD - 1.0 EVDD - 0.5 BVDD - 1.0 BVDD - 0.5 AVREF1 - 1.0 AVREF1 - 0.5 0 0 0 0 TYP. MAX. EVDD Unit V EVDD V BVDD V IOH = -0.08 mA, BVDD = 3.5 to 5.5 V IOH = -1.6 mA IOH = -0.08 mA BVDD V VOH3 P10, P11 AVREF1 AVREF1 0.8 0.8 0.8 2.0 V V V V V V Output voltage, low VOL1 VOL2 VOL3 VOL4 Note 6 Note 8 P10, P11 Note 5 IOL = 1.6 mA IOL = 1.6 mA IOL = 1.6 mA IOL = 12 mA, Note 7 Note 7 P36 to P39 EVDD = 4.0 to 5.5 V IOL = 6.4 mA, EVDD = 3.5 to 5.5 V VOL5 P614, P615 IOL = 8 mA, EVDD = 4.0 to 5.5 V IOL = 4 mA, EVDD = 3.5 to 5.5 V Input leakage current, high Input leakage current, low Output leakage current, high Output leakage current, low Pull-up resistor ILIH ILIL ILOH ILOL RL VIN = VDD VIN = 0 V VO = VDD VO = 0 V VIN = 0 V 10 30 10.0 -10.0 10.0 -10.0 120 0 1.0 V 0 2.0 V 0 1.0 V A A A A k Notes 1. Total of P00 to P06, P30 to P35, P40 to P42 and their alternate-function pins: IOH = -24 mA, total of P50 to P55, P60 to P613, P80, P81, P90 to P915 and their alternate-function pins: IOH = -24 mA. 2. Total of P00 to P06, P30 to P35, P40 to P42 and their alternate-function pins: IOH = -12 mA, total of P50 to P55, P60 to P613, P80, P81, P90 to P915 and their alternate-function pins: IOH = -12 mA. 3. Total of PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7: IOH = -24 mA, total of PDH0 to PDH7, PDL0 to PDL15 and their alternate-function pins: IOH = -24 mA. 4. Total of PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7: IOH = -12 mA, total of PDH0 to PDH7, PDL0 to PDL15 and their alternate-function pins: IOH = -12 mA. 5. When used as port pins, set AVREF1 = AVREF0 = VDD. 6. Total of P00 to P06, P30 to P37, P40 to P42 and their alternate-function pins: IOL = 24 mA, total of P38, P39, P50 to P55, P60 to P615, P80, P81, P90 to P915 and their alternate-function pins: IOL = 24 mA. 7. Refer to IOL1 for IOL of P36 to P39, P614, and P615. 8. Total of PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7 and their alternate-function pins: IOL = 24 mA, total of PDH0 to PDH7, PDL0 to PDL15 and their alternate-function pins: IOL = 24 mA. 822 User's Manual U16889EJ1V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (TARGET) DC Characteristics (TA = -40 to +110C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) (4/4) Parameter Supply current Note Symbol IDD1 Normal operation All peripheral functions operating Conditions fXX = 20 MHz (fX = 5 MHz) (in PLL mode) REGC = VDD = 5 V 10% fXX = 16 MHz (fX = 4 MHz) (in PLL mode) REGC = Capacity VDD = 5 V 10% MIN. TYP. 30 MAX. 47 Unit mA 18 32 mA IDD2 HALT mode All peripheral functions operating fXX = 20 MHz (fX = 5 MHz) (in PLL mode) REGC = VDD = 5 V 10% fXX = 16 MHz (fX = 4 MHz) (in PLL mode) REGC = Capacity VDD = 5 V 10% 17 27 mA 10 20 mA IDD3 IDLE mode Watch timer operating fX = 5 MHz (when PLL mode off) REGC = VDD = 5 V 10% fX = 4 MHz (when PLL mode off) REGC = Capacity VDD = 5 V 10% 900 3300 A 600 2300 A IDD4 Subclock operating mode fXT = 32.768 kHz Main clock stopped 70 1460 A IDD5 Subclock IDLE fXT = 32.768 kHz mode Main clock stopped, watch timer operating 15 1360 A IDD6 STOP mode Subclock stopped (XT1 = VSS, when PSMR.XTSTP bit = 1) 0.1 1330 A Note Total current of VDD, EVDD, and BVDD (all ports stopped). AVREF0 is not included. Remark fXX: Main clock frequency fX: Main clock oscillation frequency fXT: Subclock frequency User's Manual U16889EJ1V0UD 823 CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (TARGET) Data Retention Characteristics STOP Mode (TA = -40 to +110C) Parameter Data retention voltage STOP release signal input time Symbol VDDDR tDREL Conditions STOP mode MIN. 2.0 0 TYP. MAX. 5.5 Unit V s Caution Shifting to STOP mode and restoring from STOP mode must be performed within the rated operating range. STOP mode setting Operating voltage lower limit VDD STOP release signal input VDDDR tDREL RESET (input) STOP mode release interrupt (NMI, etc.) (Released by falling edge) STOP mode release interrupt (NMI, etc.) (Released by rising edge) 824 User's Manual U16889EJ1V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (TARGET) AC Characteristics AC Test Input Measurement Points (VDD, AVREF0, EVDD, BVDD) VDD VIH Measurement points VIH VIL 0V VIL AC Test Output Measurement Points VOH Measurement points VOH VOL VOL Load Conditions DUT (Device under measurement) CL = 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means. User's Manual U16889EJ1V0UD 825 CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (TARGET) CLKOUT Output Timing (TA = -40 to +110C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Output cycle High-level width Symbol tCYK tWKH <1> <2> VDD = 4.0 to 5.5 V VDD = 3.5 to 5.5 V Low-level width tWKL <3> VDD = 4.0 to 5.5 V VDD = 3.5 to 5.5 V Rise time tKR <4> VDD = 4.0 to 5.5 V VDD = 3.5 to 5.5 V Fall time tKF <5> VDD = 4.0 to 5.5 V VDD = 3.5 to 5.5 V Conditions MIN. 50 ns tCYK/2 - 18 tCYK/2 - 26 tCYK/2 - 18 tCYK/2 - 26 18 26 18 26 MAX. 30.6 s ns ns ns ns ns ns ns ns Unit Clock Timing <1> <2> <3> CLKOUT (output) <4> <5> 826 User's Manual U16889EJ1V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (TARGET) Basic Operation (1) Reset/external interrupt timing (TA = -40 to +110C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter RESET low-level width Symbol tWRSL1 tWRSL2 <87> <88> Conditions Reset in power-on status Power-on-reset when REGC = VDD Note tVR > 150 s tVR 150 s NMI high-level width NMI low-level width INTPn high-level width INTPn low-level width tWNIH tWNIL tWITH tWITL <89> <90> <91> <92> Analog noise elimination Analog noise elimination n = 0 to 6 (analog noise elimination) n = 0 to 6 (analog noise elimination) MIN. 2 2 10 45 1 1 600 600 MAX. Unit s s s s s s ns ns Note Power-on-reset when REGC = Capacity Remarks 1. tVR: Time required for VDD to reach 0 V to 4.0 V (= operation lower-limit voltage) 2. The above specification shows the pulse width that is accurately detected as a valid edge. If a pulse narrower than the above specification is input, therefore, it may also be detected as a valid edge. Reset/Interrupt VDD tVR RESET (input) <88> <87> <89> <90> NMI (input) <91> <92> INTPn (input) Remark n = 0 to 6 User's Manual U16889EJ1V0UD 827 CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (TARGET) Timer Timing (TA = -40 to +110C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter TI0n high-level width Symbol tTI0H <93> Conditions REGC = VDD = 5 V 10% MIN. 2/fsam + 100 Note MAX. Unit ns TI0n low-level width tTI0L <94> REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V 2/fsam + 200 Note ns TI5m high-level width TI5m low-level width tTI5H tTI5L <95> <96> REGC = VDD = 5 V 10% REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V 50 100 ns ns Note fsam = Timer count clock However, fsam = fXX/4 when the TI0n valid edge is selected as the timer count clock. Remarks 1. n = 00, 01, 10, 11, 20, 21, 30, 31, 40, 41, 50, 51 m = 0, 1 2. The above specification shows the pulse width that is accurately detected as a valid edge. If a pulse narrower than the above specification is input, therefore, it may also be detected as a valid edge. Timer Input Timing <93>/<95> TI0n (input) TI5m (input) <94>/<96> Remark n = 00, 01, 10, 11, 20, 21, 30, 31, 40, 41, 50, 51 m = 0, 1 UART Timing (TA = -40 to +110C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Transmit rate ASCK0 frequency REGC = VDD = 5 V 10% REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V Symbol Conditions MIN. MAX. 312.5 12 6 Unit kbps MHz MHz 828 User's Manual U16889EJ1V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (TARGET) CSI0 Timing (1) Master mode (TA = -40 to +110C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter SCK0n cycle time tKCY1 Symbol <99> Conditions REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V SCK0n high-/low-level width SI0n setup time (to SCK0n) tKH1, tKL1 tSIK1 <100> <101> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V SI0n hold time (from SCK0n) tKSI1 <102> REGC = VDD = 5 V 10% REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V Delay time from SCK0n to SO0n output tKSO1 <103> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V 30 60 ns ns 30 50 ns ns tKCY1/2 - 30 33 58 ns ns ns MIN. 200 400 MAX. Unit ns ns Remark n = 0 to 2 (2) Slave mode (TA = -40 to +110C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter SCK0n cycle time tKCY2 Symbol <99> Conditions REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V SCK0n high-/low-level width tKH2, tKL2 <100> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V SI0n setup time (to SCK0n) tSIK2 <101> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V SI0n hold time (from SCK0n) tKSI2 <102> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V Delay time from SCK0n to SO0n output tKSO2 <103> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V 50 100 ns ns 30 60 ns ns 30 60 ns ns 45 90 ns ns MIN. 200 400 MAX. Unit ns ns Remark n = 0 to 2 User's Manual U16889EJ1V0UD 829 CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (TARGET) <99> <100> SCK0n (I/O) <100> <101> <102> Hi-Z SI0n (input) Input data Hi-Z <103> SO0n (output) Output data Remarks 1. When transmit/receive type 1 (CSICn.CKPn, CSICn.DAPn bits = 00) 2. n = 0 to 2 830 User's Manual U16889EJ1V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (TARGET) CSIA Timing (1) Master mode (TA = -40 to +110C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter SCKAn cycle time tKCY3 Symbol <99> Conditions REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V SCKAn high-/low-level width tKH3, tKL3 SIAn setup time (to SCKAn) tSIK3 <101> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V SIAn hold time (from SCKAn) tKSI3 <102> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V Delay time from SCKAn to SOAn output tKSO3 <103> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V 30 60 ns ns 30 60 ns ns 39 68 ns ns <100> tKCY3/2 - 30 ns MIN. 500 1000 MAX. Unit ns ns Remark n = 0, 1 (2) Slave mode (TA = -40 to +110C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter SCKAn cycle time tKCY4 Symbol <99> Conditions REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V SCKAn high-/low-level width SIAn setup time (to SCKAn) tKH4, tKL4 tSIK4 <100> <101> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V SIAn hold time (from SCKAn) tKSI4 <102> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V Delay time from SCKAn to SOAn output tKSO4 <103> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V tCY x 2 + 30 tCY x 2 + 60 Note MIN. 840 1700 tKCY4/2 - 30 50 100 MAX. Unit ns ns ns ns ns 50 100 ns ns ns ns Note Note tCY: Internal clock output cycle fXX (CSISn.CKSAn1, CSISn.CKSAn0 bits = 00), fXX/2 (CKSAn1, CKSAn0 bits = 01) fXX/22 (CKSAn1, CKSAn0 bits = 10), fXX/23 (CKSAn1, CKSAn0 bits = 11) Remark n = 0, 1 User's Manual U16889EJ1V0UD 831 CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (TARGET) <99> <100> SCKAn (I/O) <100> <101> <102> Hi-Z SIAn (input) Input data Hi-Z <103> SOAn (output) Output data Remark n = 0, 1 832 User's Manual U16889EJ1V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (TARGET) I2C Bus Mode (Y Products (Products with On-Chip I2C) Only) (TA = -40 to +110C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Normal Mode MIN. SCLn clock frequency Bus free time (Between start and stop conditions) Hold time Note 1 High-Speed Mode MIN. 0 1.3 MAX. 400 - Unit MAX. 100 - fCLK tBUF <104> 0 4.7 kHz s s s s s s s ns ns ns tHD:STA tLOW tHIGH tSU:STA <105> <106> <107> <108> <109> 4.0 4.7 4.0 4.7 - - - - - - - 1000 300 - - 0.6 1.3 0.6 0.6 - Note 2 - - - - - Note 3 SCLn clock low-level width SCLn clock high-level width Setup time for start/restart conditions Data hold time CBUS compatible master I C mode Data setup time SDAn and SCLn signal rise time SDAn and SCLn signal fall time Stop condition setup time Pulse width of spike suppressed by input filter Capacitance load of each bus line 2 tHD:DAT 5.0 Note 2 0 tSU:DAT tR tF tSU:STO tSP <110> <111> <112> <113> <114> 0 0.9 250 - - 4.0 - - 100 Note 4 - Note 5 20 + 0.1Cb 20 + 0.1Cb 0.6 0 - 300 300 - 50 Note 5 s ns Cb 400 400 pF Notes 1. At the start condition, the first clock pulse is generated after the hold time. 2. The system requires a minimum of 300 ns hold time internally for the SDAn signal (at VIHmin. of SCLn signal) in order to occupy the undefined area at the falling edge of SCLn. 3. If the system does not extend the SCLn signal low hold time (tLOW), only the maximum data hold time (tHD:DAT) needs to be satisfied. 4. The high-speed mode I2C bus can be used in the normal-mode I2C bus system. In this case, set the highspeed mode I C bus so that it meets the following conditions. * If the system does not extend the SCLn signal's low state hold time: tSU:DAT 250 ns * If the system extends the SCLn signal's low state hold time: Transmit the following data bit to the SDAn line prior to the SCLn line release (tRmax. + tSU:DAT = 1000 + 250 = 1250 ns: Normal mode I2C bus specification). 5. Cb: Total capacitance of one bus line (unit: pF) Remark n = 0, 1 2 User's Manual U16889EJ1V0UD 833 CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (TARGET) I2C Bus Mode (Y Products (Products with On-Chip I2C) Only) <106> <107> SCLn (I/O) <112> <111> <105> <109> <110> <108> <105> <114> <113> SDAn (I/O) <104> <111> <112> Stop condition Start condition Restart condition Stop condition Remark n = 0, 1 834 User's Manual U16889EJ1V0UD CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (TARGET) A/D Converter (TA = -40 to +110C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Resolution Overall error Note 1 Symbol Conditions MIN. 10 TYP. 10 0.2 0.3 MAX. 10 0.6 0.8 60 60 0.6 0.8 0.6 0.8 4.5 6.5 2.0 2.5 Unit bit %FSR %FSR 4.0 AVREF0 5.5 V 3.5 AVREF0 4.0 V 4.0 AVREF0 5.5 V 3.5 AVREF0 4.0 V 4.0 AVREF0 5.5 V 3.5 AVREF0 4.0 V 4.0 AVREF0 5.5 V 3.5 AVREF0 4.0 V 4.0 AVREF0 5.5 V 3.5 AVREF0 4.0 V 4.0 AVREF0 5.5 V 3.5 AVREF0 4.0 V VIAN IAREF0 When using A/D converter When not using A/D converter 0 Conversion time tCONV 14 17 s s %FSR %FSR %FSR %FSR LSB LSB LSB LSB V mA Zero-scale error Note 1 Full-scale error Note 1 Non-linearity error Note 2 Differential linearity error Note 2 Analog input voltage AVREF0 current AVREF0 1.0 1.0 2.0 10 A Notes 1. Excluding quantization error (0.05 %FSR). 2. Excluding quantization error (0.5 LSB). Remark LSB: Least Significant Bit FSR: Full Scale Range D/A Converter (TA = -40 to +110C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Resolution Overall error Notes 1, 2 Symbol Conditions MIN. TYP. MAX. 8 Unit bit %FSR %FSR %FSR Load condition = 2 M Load condition = 4 M Load condition = 10 M 1.2 0.8 0.6 10 15 8 1.5 1.0 3.0 10 Settling time Note 2 C = 30 pF VDD = 4.5 to 5.5 V VDD = 3.5 to 4.5 V s s k mA Output resistance AVREF1 current Note 3 RO IAVREF1 Output data: DACSn register = 55H During D/A conversion When D/A conversion stopped Note 4 A Notes 1. Excluding quantization error (0.2 %FSR). 2. R is the D/A converter output pin load resistance, and C is the D/A converter output pin load capacitance. 3. Value of 1 channel of D/A converter 4. Value of 2 channels of D/A converter Remark n = 0, 1 User's Manual U16889EJ1V0UD 835 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (TARGET) (A2) grade products are as follows. PD703216(A2), 703216Y(A2), 703217(A2), 703217Y(A2) Absolute Maximum Ratings (TA = 25C) (1/2) Parameter Supply voltage Symbol VDD BVDD EVDD AVREF0 AVREF1 Conditions VDD = EVDD = AVREF0 BVDD VDD VDD = EVDD = AVREF0 VDD = EVDD = AVREF0 AVREF1 VDD (D/A output mode) AVREF1 = AVREF0 = VDD (port mode) VSS AVSS BVSS EVSS Input voltage VI1 VSS = EVSS = BVSS = AVSS VSS = EVSS = BVSS = AVSS VSS = EVSS = BVSS = AVSS VSS = EVSS = BVSS = AVSS P00 to P06, P30 to P35, P38, P39, P40 to P42, P50 to P55, P60 to P613, P80, P81, P90 to P915, RESET VI2 PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7, PDL0 to PDL15, PDH0 to PDH7 VI3 VI4 VI5 Analog input voltage VIAN P10, P11 P36, P37, P614, P615 X1, X2, XT1, XT2 P70 to P715 -0.3 to AVREF1 + 0.3 -0.3 to +13 Note 2 Note 1 Ratings -0.3 to +6.5 -0.3 to VDD + 0.3 -0.3 to +6.5 -0.3 to +6.5 -0.3 to VDD + 0.3 -0.3 to +0.3 -0.3 to +0.3 -0.3 to +0.3 -0.3 to +0.3 -0.3 to EVDD + 0.3 Note 1 Note 1 Note 1 Unit V V V V V V V V V V -0.3 to BVDD + 0.3 Note 1 V V V V V -0.3 to VDD + 0.3 Note 1 -0.3 to AVREF0 + 0.3 Note 1 Notes 1. Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage. 2. When an on-chip pull-up resistor is not specified by a mask option. The same as VI1 when a pull-up resistor is specified. 836 User's Manual U16889EJ1V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (TARGET) Absolute Maximum Ratings (TA = 25C) (2/2) Parameter Output current, low Symbol IOL Conditions P00 to P06, P10, P11, P30 to P35, P40 to P42, P50 to P55, P60 to P613, P80, P81, P90 to P915, PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7, PDL0 to PDL15, PDH0 to PDH7 P36 to P39, P614, P615 P00 to P06, P30 to P39, P40 to P42 P50 to P55, P60 to P615, P80, P81, P90 to P915 PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7 PDL0 to PDL15, PDH0 to PDH7 Output current, high IOH Per pin P00 to P06, P30 to P35, P40 to P42 P50 to P55, P60 to P613, P80, P81, P90 to P915 PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7 PDL0 to PDL15, PDH0 to PDH7 P10, P11 Operating ambient temperature Storage temperature Tstg -65 to +150 C TA Total of all pins: -42 mA Total of all pins: -42 mA Per pin -21 -7 -40 to +125 C mA Total of all pins: 49 mA Total of all pins: 49 mA 24.5 -7 -21 -21 -21 mA mA mA mA 24.5 mA 21 24.5 24.5 mA mA Per pin Ratings 14 Unit mA Cautions 1. Do not directly connect the output (or I/O) pins of IC products to each other, or to VDD, VCC, and GND. Open-drain pins or open-collector pins, however, can be directly connected to each other. Direct connection of the output pins between an IC product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Capacitance (TA = 25C, VDD = EVDD = AVREF0 = BVDD = AVREF1 = VSS = EVSS = BVSS = AVSS = 0 V) Parameter Input capacitance I/O capacitance Symbol CI CIO fX = 1 MHz Unmeasured pins returned to 0 V Conditions P70 to P715 Note P36 to P39, P614, P615 MIN. TYP. MAX. 15 15 20 Unit pF pF pF Note P00 to P06, P10, P11, P30 to P35, P40 to P42, P50 to P55, P60 to P613, P80, P81, P90 to P915, PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7, PDL0 to PDL15, PDH0 to PDH7 Remark fX: Main clock oscillation frequency User's Manual U16889EJ1V0UD 837 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (TARGET) Operating Conditions (TA = -40 to +125C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Internal system clock frequency Symbol fCLK Conditions REGC = VDD = 5 V 10% In PLL mode (fX = 2 to 4 MHz) REGC = VDD = 4.0 to 5.5 V In PLL mode (fX = 2 to 4 MHz) REGC = Capacity, VDD = 4.0 to 5.5 V In PLL mode (fX = 2 to 4 MHz) REGC = VDD = 3.5 to 5.5 V In PLL mode (fX = 2 to 3 MHz) REGC = VDD = 3.5 to 5.5 V REGC = VDD = 3.5 to 5.5 V, operating with subclock 0.0625 32.768 10 MHz kHz 0.25 12 MHz 0.25 16 MHz 0.25 16 MHz MIN. 0.25 TYP. MAX. 20 Unit MHz Remark fX: Main clock oscillation frequency Internal System Clock Frequency vs. Supply Voltage 100 When REGC = Capacity Internal system clock frequency fCLK [MHz] 20.0 16.0 12.0 10.0 1.0 0.1 0.032 0.01 2.0 3.0 3.5 4.0 5.0 6.0 Supply voltage VDD [V] PLL Characteristics (TA = -40 to +125C, VDD = 3.5 to 5.5 V, VSS = 0 V) Parameter Input frequency Output frequency Lock time Symbol fX fXX tPLL After VDD reaches 3.5 V (MIN.) Conditions MIN. 2 8 TYP. MAX. 4 16 200 Unit MHz MHz s 838 User's Manual U16889EJ1V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (TARGET) Main Clock Oscillator Characteristics (TA = -40 to +125C, VDD = 3.5 to 5.5 V, VSS = 0 V) Resonator Ceramic resonator X1 X2 Recommended Circuit Parameter Oscillation frequency (fX) Note 1 Conditions MIN. 2 TYP. MAX. 10 Unit MHz Oscillation stabilization time Note 2 After reset is released After STOP mode is released 2 /fX 15 s Note 3 s Crystal resonator X1 X2 Oscillation frequency (fX) Note 1 2 15 10 MHz Oscillation stabilization time Note 2 After reset is released After STOP mode is released 2 /fX s Note 3 s External clock X1 X2 X1, X2 input frequency (fX) REGC = VDD Duty = 50% 5% 2 10 MHz External clock Notes 1. Indicates only oscillator characteristics. 2. Time required to stabilize the resonator after reset or STOP mode is released. 3. The value differs depending on the OSTS register settings. Cautions 1. When using the main clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main clock is stopped and the device is operating on the subclock, wait until the oscillation stabilization time has been secured by the program before switching back to the main clock. User's Manual U16889EJ1V0UD 839 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (TARGET) Subclock Oscillator Characteristics (TA = -40 to +125C, VDD = 3.5 to 5.5 V, VSS = 0 V) Resonator Crystal resonator XT1 XT2 Recommended Circuit Parameter Oscillation frequency (fXT) Note 1 Conditions MIN. 32 TYP. 32.768 MAX. 35 Unit kHz Oscillation stabilization time Note 2 10 s External clock XT1 XT2 XT1 input frequency (fXT) Note 1 REGC = VDD 32 35 kHz Duty = 50% 5% External clock Notes 1. Indicates only oscillator characteristics. 2. Time required from when VDD reaches oscillation voltage range (3.5 V (MIN.)) to when the crystal resonator stabilizes. Cautions 1. When using the subclock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subclock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the main clock oscillator. Particular care is therefore required with the wiring method when the subclock is used. 840 User's Manual U16889EJ1V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (TARGET) DC Characteristics (TA = -40 to +125C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) (1/4) Parameter Output current, high Symbol IOH1 Conditions Per pin for P00 to P06, P10, P11, P30 to P35, P40 to P42, P50 to P55, P60 to P613, P80, P81, P90 to P915 Total of P00 to P06, P30 to P35, P40 to P42 Total of P50 to P55, P60 to P613, P80, P81, P90 to P915 IOH2 EVDD = 4.0 to 5.5 V EVDD = 3.5 to 5.5 V EVDD = 4.0 to 5.5 V EVDD = 3.5 to 5.5 V -21 -10.5 -21 -10.5 -3.5 -21 -10.5 -21 -10.5 7 mA mA mA mA mA MAX. -3.5 Unit mA Per pin for PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7, PDH0 to PDH7, PDL0 to PDL15 Total of PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7 Total of PDL0 to PDL15, PDH0 to PDH7 BVDD = 4.0 to 5.5 V BVDD = 3.5 to 5.5 V BVDD = 4.0 to 5.5 V BVDD = 3.5 to 5.5 V mA mA mA mA mA Output current, low IOL1 Per pin for P00 to P06, P10, P11, P30 to P35, P40 to P42, P50 to P55, P60 to P613, P80, P81, P90 to P915 Per pin for P36 to P39 EVDD = 4.0 to 5.5 V EVDD = 3.5 to 5.5 V Per pin for P614, P615 EVDD = 4.0 to 5.5 V EVDD = 3.5 to 5.5 V Total of P00 to P06, P30 to P37, P40 to P42 Total of P38, P39, P50 to P55, P60 to P615, P80, P81, P90 to P915 10.5 5.6 7 3.5 21 21 mA mA mA mA mA mA IOL2 Per pin for PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7, PDH0 to PDH7, PDL0 to PDL15 Total of PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7 Total of PDL0 to PDL15, PDH0 to PDH7 7 mA 21 mA 21 mA User's Manual U16889EJ1V0UD 841 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (TARGET) DC Characteristics (TA = -40 to +125C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) (2/4) Parameter Input voltage, high Symbol VIH1 VIH2 VIH3 VIH4 VIH5 VIH6 VIH7 Input voltage, low VIL1 VIL2 VIL3 VIL4 VIL5 VIL6 VIL7 Note 1 Note 2 Note 3 P70 to P715 P10, P11 Note 4 Conditions MIN. 0.7EVDD 0.8EVDD 0.7BVDD 0.7AVREF0 0.7AVREF1 0.7EVDD VDD - 0.5 EVSS EVSS BVSS AVSS AVSS EVSS VSS TYP. MAX. EVDD EVDD BVDD AVREF0 AVREF1 12 Note 5 Unit V V V V V V V V V V V V V V P36, P37, P614, P615 X1, X2, XT1, XT2 Note 1 Note 2 Note 3 P70 to P715 P10, P11 Note 4 VDD 0.3EVDD 0.2EVDD 0.3BVDD 0.3AVREF0 0.3AVREF1 0.3EVDD 0.4 P36, P37, P614, P615 X1, X2, XT1, XT2 Notes 1. P00, P01, P30, P41, P60 to P65, P67, P611, P98, P911 and their alternate-function pins. 2. RESET, P02 to P06, P31 to P35, P38, P39, P40, P42, P50 to P55, P66, P68 to P610, P612, P613, P80, P81, P90 to P97, P99, P910, P912 to P915 and their alternate-function pins. 3. PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7, PDL0 to PDL15, PDH0 to PDH7 and their alternate-function pins. 4. When used as port pins, set AVREF1 = AVREF0 = VDD. 5. When an on-chip pull-up resistor is not specified by a mask option. EVDD when a pull-up resistor is specified. 842 User's Manual U16889EJ1V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (TARGET) DC Characteristics (TA = -40 to +125C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) (3/4) Parameter Output voltage, high Symbol VOH1 Note 1 Conditions IOH = -1.4 mA, EVDD = 4.0 to 5.5 V Note 2 IOH = -0.07 mA, EVDD = 3.5 to 5.5 V VOH2 Note 3 IOH = -1.4 mA, BVDD = 4.0 to 5.5 V Note 4 Note 5 MIN. EVDD - 1.0 EVDD - 0.5 BVDD - 1.0 BVDD - 0.5 AVREF1 - 1.0 AVREF1 - 0.5 0 0 0 0 TYP. MAX. EVDD Unit V EVDD V BVDD V IOH = -0.07 mA, BVDD = 3.5 to 5.5 V IOH = -1.4 mA IOH = -0.07 mA BVDD V VOH3 P10, P11 AVREF1 AVREF1 0.8 0.8 0.8 2.0 V V V V V V Output voltage, low VOL1 VOL2 VOL3 VOL4 Note 6 Note 8 P10, P11 Note 5 IOL = 1.4 mA IOL = 1.4 mA IOL = 1.4 mA Note 7 Note 7 P36 to P39 IOL = 10.5 mA, EVDD = 4.0 to 5.5 V IOL = 5.6 mA, EVDD = 3.5 to 5.5 V 0 1.0 V VOL5 P614, P615 IOL = 7 mA, EVDD = 4.0 to 5.5 V IOL = 3.5 mA, EVDD = 3.5 to 5.5 V 0 2.0 V 0 1.0 V Input leakage current, high Input leakage current, low Output leakage current, high Output leakage current, low Pull-up resistor ILIH ILIL ILOH ILOL RL VIN = VDD VIN = 0 V VO = VDD VO = 0 V VIN = 0 V 10 30 10.0 -10.0 10.0 -10.0 120 A A A A k Notes 1. Total of P00 to P06, P30 to P35, P40 to P42 and their alternate-function pins: IOH = -21 mA, total of P50 to P55, P60 to P613, P80, P81, P90 to P915 and their alternate-function pins: IOH = -21 mA. 2. Total of P00 to P06, P30 to P35, P40 to P42 and their alternate-function pins: IOH = -10.5 mA, total of P50 to P55, P60 to P613, P80, P81, P90 to P915 and their alternate-function pins: IOH = -10.5 mA. 3. Total of PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7: IOH = -21 mA, total of PDH0 to PDH7, PDL0 to PDL15 and their alternate-function pins: IOH = -21 mA. 4. Total of PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7: IOH = -10.5 mA, total of PDH0 to PDH7, PDL0 to PDL15 and their alternate-function pins: IOH = -10.5 mA. 5. When used as port pins, set AVREF1 = AVREF0 = VDD. 6. Total of P00 to P06, P30 to P37, P40 to P42 and their alternate-function pins: IOL = 21 mA, total of P38, P39, P50 to P55, P60 to P615, P80, P81, P90 to P915 and their alternate-function pins: IOL = 21 mA. 7. Refer to IOL1 for IOL of P36 to P39, P614, and P615. 8. Total of PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7 and their alternate-function pins: IOL = 21 mA, total of PDH0 to PDH7, PDL0 to PDL15 and their alternate-function pins: IOL = 21 mA. User's Manual U16889EJ1V0UD 843 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (TARGET) DC Characteristics (TA = -40 to +125C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) (4/4) Parameter Supply current Note Symbol IDD1 Normal operation All peripheral functions operating Conditions fXX = 16 MHz (fX = 4 MHz) (in PLL mode) REGC = VDD = 5 V 10% fXX = 16 MHz (fX = 4 MHz) (in PLL mode) REGC = Capacity VDD = 5 V 10% MIN. TYP. 30 MAX. 43 Unit mA 18 33 mA IDD2 HALT mode All peripheral functions operating fXX = 16 MHz (fX = 4 MHz) (in PLL mode) REGC = VDD = 5 V 10% fXX = 16 MHz (fX = 4 MHz) (in PLL mode) REGC = Capacity VDD = 5 V 10% 17 26 mA 10 21 mA IDD3 IDLE mode Watch timer operating fX = 4 MHz (when PLL mode off) REGC = VDD = 5 V 10% fX = 4 MHz (when PLL mode off) REGC = Capacity VDD = 5 V 10% 900 3700 A 600 2900 A IDD4 Subclock operating mode fXT = 32.768 kHz Main clock stopped 70 2060 A IDD5 Subclock IDLE fXT = 32.768 kHz mode Main clock stopped, watch timer operating 15 1960 A IDD6 STOP mode Subclock stopped (XT1 = VSS, when PSMR.XTSTP bit = 1) 0.1 1930 A Note Total current of VDD, EVDD, and BVDD (all ports stopped). AVREF0 is not included. Remark fXX: Main clock frequency fX: Main clock oscillation frequency fXT: Subclock frequency 844 User's Manual U16889EJ1V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (TARGET) Data Retention Characteristics STOP Mode (TA = -40 to +125C) Parameter Data retention voltage STOP release signal input time Symbol VDDDR tDREL Conditions STOP mode MIN. 2.0 0 TYP. MAX. 5.5 Unit V s Caution Shifting to STOP mode and restoring from STOP mode must be performed within the rated operating range. STOP mode setting Operating voltage lower limit VDD STOP release signal input VDDDR tDREL RESET (input) STOP mode release interrupt (NMI, etc.) (Released by falling edge) STOP mode release interrupt (NMI, etc.) (Released by rising edge) User's Manual U16889EJ1V0UD 845 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (TARGET) AC Characteristics AC Test Input Measurement Points (VDD, AVREF0, EVDD, BVDD) VDD VIH Measurement points VIH VIL 0V VIL AC Test Output Measurement Points VOH Measurement points VOH VOL VOL Load Conditions DUT (Device under measurement) CL = 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means. 846 User's Manual U16889EJ1V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (TARGET) CLKOUT Output Timing (TA = -40 to +125C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Output cycle High-level width Symbol tCYK tWKH <1> <2> VDD = 4.0 to 5.5 V VDD = 3.5 to 5.5 V Low-level width tWKL <3> VDD = 4.0 to 5.5 V VDD = 3.5 to 5.5 V Rise time tKR <4> VDD = 4.0 to 5.5 V VDD = 3.5 to 5.5 V Fall time tKF <5> VDD = 4.0 to 5.5 V VDD = 3.5 to 5.5 V Conditions MIN. 62.5 ns tCYK/2 - 18 tCYK/2 - 26 tCYK/2 - 18 tCYK/2 - 26 18 26 18 26 MAX. 30.6 s ns ns ns ns ns ns ns ns Unit Clock Timing <1> <2> <3> CLKOUT (output) <4> <5> User's Manual U16889EJ1V0UD 847 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (TARGET) Basic Operation (1) Reset/external interrupt timing (TA = -40 to +125C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter RESET low-level width Symbol tWRSL1 tWRSL2 <87> <88> Conditions Reset in power-on status Power-on-reset when REGC = VDD Note tVR > 150 s tVR 150 s NMI high-level width NMI low-level width INTPn high-level width INTPn low-level width tWNIH tWNIL tWITH tWITL <89> <90> <91> <92> Analog noise elimination Analog noise elimination n = 0 to 6 (analog noise elimination) n = 0 to 6 (analog noise elimination) MIN. 2 2 10 45 1 1 600 600 MAX. Unit s s s s s s ns ns Note Power-on-reset when REGC = Capacity Remarks 1. tVR: Time required for VDD to reach 0 V to 4.0 V (= operation lower-limit voltage) 2. The above specification shows the pulse width that is accurately detected as a valid edge. If a pulse narrower than the above specification is input, therefore, it may also be detected as a valid edge. Reset/Interrupt VDD tVR RESET (input) <88> <87> <89> <90> NMI (input) <91> <92> INTPn (input) Remark n = 0 to 6 848 User's Manual U16889EJ1V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (TARGET) Timer Timing (TA = -40 to +125C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter TI0n high-level width Symbol tTI0H <93> Conditions REGC = VDD = 5 V 10% MIN. 2/fsam + 100 Note MAX. Unit ns TI0n low-level width tTI0L <94> REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V 2/fsam + 200 Note ns TI5m high-level width TI5m low-level width tTI5H tTI5L <95> <96> REGC = VDD = 5 V 10% REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V 50 100 ns ns Note fsam = Timer count clock However, fsam = fXX/4 when the TI0n valid edge is selected as the timer count clock. Remarks 1. n = 00, 01, 10, 11, 20, 21, 30, 31, 40, 41, 50, 51 m = 0, 1 2. The above specification shows the pulse width that is accurately detected as a valid edge. If a pulse narrower than the above specification is input, therefore, it may also be detected as a valid edge. Timer Input Timing <93>/<95> TI0n (input) TI5m (input) <94>/<96> Remark n = 00, 01, 10, 11, 20, 21, 30, 31, 40, 41, 50, 51 m = 0, 1 UART Timing (TA = -40 to +125C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Transmit rate ASCK0 frequency REGC = VDD = 5 V 10% REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V Symbol Conditions MIN. MAX. 312.5 12 6 Unit kbps MHz MHz User's Manual U16889EJ1V0UD 849 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (TARGET) CSI0 Timing (1) Master mode (TA = -40 to +125C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter SCK0n cycle time tKCY1 Symbol <99> Conditions REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V SCK0n high-/low-level width SI0n setup time (to SCK0n) tKH1, tKL1 tSIK1 <100> <101> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V SI0n hold time (from SCK0n) tKSI1 <102> REGC = VDD = 5 V 10% REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V Delay time from SCK0n to SO0n output tKSO1 <103> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V 30 60 ns ns 30 50 ns ns tKCY1/2 - 30 33 58 ns ns ns MIN. 200 400 MAX. Unit ns ns Remark n = 0 to 2 (2) Slave mode (TA = -40 to +125C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter SCK0n cycle time tKCY2 Symbol <99> Conditions REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V SCK0n high-/low-level width tKH2, tKL2 <100> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V SI0n setup time (to SCK0n) tSIK2 <101> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V SI0n hold time (from SCK0n) tKSI2 <102> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V Delay time from SCK0n to SO0n output tKSO2 <103> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V 50 100 ns ns 30 60 ns ns 30 60 ns ns 45 90 ns ns MIN. 200 400 MAX. Unit ns ns Remark n = 0 to 2 850 User's Manual U16889EJ1V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (TARGET) <99> <100> SCK0n (I/O) <100> <101> <102> Hi-Z SI0n (input) Input data Hi-Z <103> SO0n (output) Output data Remarks 1. When transmit/receive type 1 (CSICn.CKPn, CSICn.DAPn bits = 00) 2. n = 0 to 2 User's Manual U16889EJ1V0UD 851 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (TARGET) CSIA Timing (1) Master mode (TA = -40 to +125C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter SCKAn cycle time tKCY3 Symbol <99> Conditions REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V SCKAn high-/low-level width tKH3, tKL3 SIAn setup time (to SCKAn) tSIK3 <101> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V SIAn hold time (from SCKAn) tKSI3 <102> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V Delay time from SCKAn to SOAn output tKSO3 <103> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V 30 60 ns ns 30 60 ns ns 39 68 ns ns <100> tKCY3/2 - 30 ns MIN. 500 1000 MAX. Unit ns ns Remark n = 0, 1 (2) Slave mode (TA = -40 to +125C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter SCKAn cycle time tKCY4 Symbol <99> Conditions REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V SCKAn high-/low-level width SIAn setup time (to SCKAn) tKH4, tKL4 tSIK4 <100> <101> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V SIAn hold time (from SCKAn) tKSI4 <102> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V Delay time from SCKAn to SOAn output tKSO4 <103> REGC = VDD = 4.0 to 5.5 V REGC = Capacity, VDD = 4.0 to 5.5 V, REGC = VDD = 3.5 to 5.5 V tCY x 2 + 30 tCY x 2 + 60 Note MIN. 840 1700 tKCY4/2 - 30 50 100 MAX. Unit ns ns ns ns ns 50 100 ns ns ns ns Note Note tCY: Internal clock output cycle fXX (CSISn.CKSAn1, CSISn.CKSAn0 bits = 00), fXX/2 (CKSAn1, CKSAn0 bits = 01) fXX/22 (CKSAn1, CKSAn0 bits = 10), fXX/23 (CKSAn1, CKSAn0 bits = 11) Remark n = 0, 1 852 User's Manual U16889EJ1V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (TARGET) <99> <100> SCKAn (I/O) <100> <101> <102> Hi-Z SIAn (input) Input data Hi-Z <103> SOAn (output) Output data Remark n = 0, 1 User's Manual U16889EJ1V0UD 853 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (TARGET) I2C Bus Mode (Y Products (Products with On-Chip I2C) Only) (TA = -40 to +125C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V, CL = 50 pF) Parameter Symbol Normal Mode MIN. SCLn clock frequency Bus free time (Between start and stop conditions) Hold time Note 1 High-Speed Mode MIN. 0 1.3 MAX. 400 - Unit MAX. 100 - fCLK tBUF <104> 0 4.7 kHz s s s s s s s ns ns ns tHD:STA tLOW tHIGH tSU:STA <105> <106> <107> <108> <109> 4.0 4.7 4.0 4.7 - - - - - - - 1000 300 - - 0.6 1.3 0.6 0.6 - Note 2 - - - - - Note 3 SCLn clock low-level width SCLn clock high-level width Setup time for start/restart conditions Data hold time CBUS compatible master I C mode Data setup time SDAn and SCLn signal rise time SDAn and SCLn signal fall time Stop condition setup time Pulse width of spike suppressed by input filter Capacitance load of each bus line 2 tHD:DAT 5.0 Note 2 0 tSU:DAT tR tF tSU:STO tSP <110> <111> <112> <113> <114> 0 0.9 250 - - 4.0 - - 100 Note 4 - Note 5 20 + 0.1Cb 20 + 0.1Cb 0.6 0 - 300 300 - 50 Note 5 s ns Cb 400 400 pF Notes 1. At the start condition, the first clock pulse is generated after the hold time. 2. The system requires a minimum of 300 ns hold time internally for the SDAn signal (at VIHmin. of SCLn signal) in order to occupy the undefined area at the falling edge of SCLn. 3. If the system does not extend the SCLn signal low hold time (tLOW), only the maximum data hold time (tHD:DAT) needs to be satisfied. 4. The high-speed mode I2C bus can be used in the normal-mode I2C bus system. In this case, set the highspeed mode I C bus so that it meets the following conditions. * If the system does not extend the SCLn signal's low state hold time: tSU:DAT 250 ns * If the system extends the SCLn signal's low state hold time: Transmit the following data bit to the SDAn line prior to the SCLn line release (tRmax. + tSU:DAT = 1000 + 250 = 1250 ns: Normal mode I2C bus specification). 5. Cb: Total capacitance of one bus line (unit: pF) Remark n = 0, 1 2 854 User's Manual U16889EJ1V0UD CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (TARGET) I2C Bus Mode (Y Products (Products with On-Chip I2C) Only) <106> <107> SCLn (I/O) <112> <111> <105> <109> <110> <108> <105> <114> <113> SDAn (I/O) <104> <111> <112> Stop condition Start condition Restart condition Stop condition Remark n = 0, 1 User's Manual U16889EJ1V0UD 855 CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (TARGET) A/D Converter (TA = -40 to +125C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Resolution Overall error Note 1 Symbol Conditions MIN. 10 TYP. 10 0.2 0.3 MAX. 10 0.7 0.9 60 60 0.7 0.9 0.7 0.9 5.5 7.5 2.5 3.0 Unit bit %FSR %FSR 4.0 AVREF0 5.5 V 3.5 AVREF0 4.0 V Conversion time tCONV 4.0 AVREF0 5.5 V 3.5 AVREF0 4.0 V 14 17 s s %FSR %FSR %FSR %FSR LSB LSB LSB LSB V mA Zero-scale error Note 1 4.0 AVREF0 5.5 V 3.5 AVREF0 4.0 V Full-scale error Note 1 4.0 AVREF0 5.5 V 3.5 AVREF0 4.0 V Non-linearity error Note 2 4.0 AVREF0 5.5 V 3.5 AVREF0 4.0 V Differential linearity error Note 2 4.0 AVREF0 5.5 V 3.5 AVREF0 4.0 V VIAN IAREF0 When using A/D converter When not using A/D converter 0 1.0 1.0 Analog input voltage AVREF0 current AVREF0 2.0 10 A Notes 1. Excluding quantization error (0.05 %FSR). 2. Excluding quantization error (0.5 LSB). Remark LSB: Least Significant Bit FSR: Full Scale Range D/A Converter (TA = -40 to +125C, VDD = EVDD = AVREF0 = 3.5 to 5.5 V, 3.5 V BVDD VDD, 3.5 V AVREF1 VDD, VSS = EVSS = BVSS = AVSS = 0 V) Parameter Resolution Overall error Notes 1, 2 Symbol Conditions MIN. TYP. MAX. 8 Unit bit %FSR %FSR %FSR Load condition = 2 M Load condition = 4 M Load condition = 10 M 1.2 0.8 0.6 10 15 8 1.5 1.0 3.0 10 Settling time Note 2 C = 30 pF VDD = 4.5 to 5.5 V VDD = 2.7 to 4.5 V s s k mA Output resistance AVREF1 current Note 3 RO IAVREF1 Output data: DACSn register = 55H During D/A conversion When D/A conversion stopped Note 4 A Notes 1. Excluding quantization error (0.2 %FSR). 2. R is the D/A converter output pin load resistance, and C is the D/A converter output pin load capacitance. 3. Value of 1 channel of D/A converter 4. Value of 2 channels of D/A converter Remark n = 0, 1 856 User's Manual U16889EJ1V0UD CHAPTER 32 PACKAGE DRAWING 144-PIN PLASTIC LQFP (FINE PITCH) (20x20) A B 108 109 73 72 detail of lead end S C D R Q 144 1 37 36 F G H I M J P K S L M N NOTE S Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 22.00.2 20.00.2 20.00.2 22.00.2 1.25 1.25 0.220.05 0.08 0.5 (T.P.) 1.00.2 0.50.2 0.17 +0.03 -0.07 0.08 1.4 0.100.05 3 +4 -3 1.50.1 S144GJ-50-UEN User's Manual U16889EJ1V0UD 857 CHAPTER 33 RECOMMENDED SOLDERING CONDITIONS The V850ES/KJ1 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 33-1. Surface Mounting Type Soldering Conditions (1/2) (1) PD703216GJ-xxx-UEN: 144-pin plastic LQFP (fine pitch) (20 x 20) PD703216YGJ-xxx-UEN: 144-pin plastic LQFP (fine pitch) (20 x 20) PD703217GJ-xxx-UEN: 144-pin plastic LQFP (fine pitch) (20 x 20) PD703217YGJ-xxx-UEN: 144-pin plastic LQFP (fine pitch) (20 x 20) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 230C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less, Exposure limit: 3 days 72 hours) VPS Package peak temperature: 215C, Time: 25 to 40 seconds (at 200C or higher), Count: Two times or less, Exposure limit: 3 days 72 hours) Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) - Note Note IR30-103-2 (after that, prebake at 125C for 10 to VP15-103-2 (after that, prebake at 125C for 10 to Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). Remark Soldering conditions for the (A), (A1), and (A2) grade products are the same as for the standard products. 858 User's Manual U16889EJ1V0UD CHAPTER 33 RECOMMENDED SOLDERING CONDITIONS Table 33-1. Surface Mounting Type Soldering Conditions (2/2) (2) PD70F3217GJ-UEN: 144-pin plastic LQFP (fine pitch) (20 x 20) PD70F3217YGJ-UEN: 144-pin plastic LQFP (fine pitch) (20 x 20) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less, Exposure limit: 3 days hours) VPS Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Two times or less, Exposure limit: 3 days hours) Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) - Note Note IR35-363-2 (after that, prebake at 125C for 36 VP15-363-2 (after that, prebake at 125C for 36 Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). (3) PD70F3217HGJ-UEN: 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) PD70F3217HYGJ-UEN: PD70F3218HGJ-UEN: PD70F3218HYGJ-UEN: Undefined User's Manual U16889EJ1V0UD 859 APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the V850ES/KJ1. Figure A-1 shows the development tool configuration. * Support for PC98-NX series Unless otherwise specified, products supported by IBM PC/ATTM compatibles are compatible with PC98-NX series computers. When using PC98-NX series computers, refer to the explanation for IBM PC/AT compatibles. * WindowsTM Unless otherwise specified, "Windows" means the following OSs. * Windows 98, 2000 * Windows Me * Windows XP * Windows NTTM Ver. 4.0 860 User's Manual U16889EJ1V0UD APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration Software package Language processing software * C compiler package * Device file Debugging software * Integrated debugger * System simulator Control software * Project manager (Windows only)Note 1 Embedded software * Real-time OS * Network library * File system Host machine (PC or EWS) Interface adapterNote 2 Power supply unit Flash memory write environment Flash programmer Flash memory write adapter In-circuit emulator (IE-V850ES-G1)Note 3 (IE-V850ESK1-ET)Note 4 (QB-V850ESKX1H)Note 5 Flash memory Conversion socket or conversion adapter Target system Notes 1. 2. 3. 4. The project manager PM plus is included in the assembler package. The PM plus is only used for Windows. QB-V850ESKX1H supports USB only. Products other than in-circuit emulator IE-V850ES-G1 are all sold separately. In-circuit emulator IE-V850ESK1-ET is supplied with integrated debugger ID850, a device file, power supply unit, PCI bus interface adapter IE-70000-PCI-IF-A, and emulation probe. Any other products are sold separately. 5. In-circuit emulator QB-V850ESKX1H is supplied with integrated debugger ID850, a device file, and power supply unit. Any other products are sold separately. User's Manual U16889EJ1V0UD 861 APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP850 V850 Series software package Development tools (software) common to the V850 Series are combined in this package. Part number: SxxxxSP850 Remark xxxx in the part number differs depending on the host machine and OS used. SxxxxSP850 xxxx AB17 BB17 Host Machine PC-9800 series, IBM PC/AT compatibles OS Windows (Japanese version) Windows (English version) Supply Medium CD-ROM A.2 Language Processing Software CA850 C compiler package This compiler converts programs written in C language into object codes executable with a microcontroller. This compiler is started from project manager PM plus. Part number: SxxxxCA703000 DF703217 Device file Note 1 , Note 2 This file contains information peculiar to the device. This device file should be used in combination with a tool (CA850, SM850, and ID850). The corresponding OS and host machine differ depending on the tool to be used. DF703218 (provisional name) Notes 1. 2. Remark Only in the PD703216, 703216Y, 703217, 703217Y, 70F3217, 70F3217Y Under development xxxx in the part number differs depending on the host machine and OS used. SxxxxCA703000 xxxx AB17 BB17 3K17 Host Machine PC-9800 series, IBM PC/AT compatibles SPARCstation TM OS Windows (Japanese version) Windows (English version) SunOS Solaris TM Supply Medium CD-ROM (Rel. 4.1.4), (Rel. 2.5.1) TM A.3 Control Software PM plus Project manager This is control software designed to enable efficient user program development in the Windows environment. All operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from the PM plus. 862 User's Manual U16889EJ1V0UD APPENDIX A DEVELOPMENT TOOLS A.4 Debugging Tools (Hardware) A.4.1 When using in-circuit emulator IE-V850ES-G1 The in-circuit emulator serves to debug hardware and software when developing application systems using a V850 Series product. It corresponds to the integrated debugger ID850. This emulator should be used in combination with a power supply unit, emulation probe, and the interface adapter required to connect this emulator to the host machine. This is PC card and interface cable required when using a notebook-type computer as the host machine (PCMCIA socket compatible). This adapter is required when using a computer with a PCI bus as the host machine. This board emulates the operations of the peripheral hardware peculiar to a device. It should be used in combination with an in-circuit emulator. This probe is used to connect the in-circuit emulator and target system. This is supplied with emulation board IE-703217-G1-EM1. EV-703217GJ Conversion adapter This conversion adapter is used to connect the emulation probe and target system board on which a 144-pin plastic LQFP (GJ-UEN type) can be mounted. IE-V850ES-G1 In-circuit emulator IE-70000-CD-IF-A PC card interface IE-70000-PCI-IF-A Interface adapter IE-703217-G1-EM1 Emulation board GXP-CABLE Emulation probe Remark EV-703217GJ is a product of Application Corporation. TEL: +81-42-732-1377 Application Corporation A.4.2 When using in-circuit emulator IE-V850ESK1-ET Note IE-V850ESK1-ET In-circuit emulator The in-circuit emulator serves to debug hardware and software when developing application systems using a V850ES/KJ1 product. It corresponds to the integrated debugger ID850. This emulator should be used in combination with a power supply unit, emulation probe, and the interface adapter required to connect this emulator to the host machine. This adapter is required when using a computer with a PCI bus as the host machine. This is supplied with IE-V850ESK1-ET. This probe is used to connect the in-circuit emulator and target system. This is supplied with IE-V850ESK1-ET. EV-703217GJ Conversion adapter This conversion adapter is used to connect the emulation probe and target system board on which a 144-pin plastic LQFP (GJ-UEN type) can be mounted. IE-70000-PCI-IF-A Interface adapter Emulation probe Note IE-V850ESK1-ET is supplied with a power supply unit and PCI bus interface adapter IE-70000-PCI-IF-A. It is also supplied with integrated debugger ID850 and a device file as control software. Remark EV-703217GJ is a product of Application Corporation. TEL: +81-42-732-1377 Application Corporation A.4.3 When using in-circuit emulator QB-V850ESKX1H Notes 1, 2 QB-V850ESKX1H In-circuit emulator The in-circuit emulator serves to debug hardware and software when developing application systems using a V850ES/KJ1 product. It corresponds to the integrated debugger ID850. This emulator should be used in combination with a power supply unit and emulation probe. Use USB to connect this emulator to the host machine. Note 2 Emulation probe for GJ package (part number pending) This probe is used to connect the in-circuit emulator and target system, and is designed for a 144-pin plastic LQFP (GJ-UEN type). Notes 1. 2. QB-V850ESKX1H is supplied with a power supply unit. It is also supplied with integrated debugger ID850 and a device file as control software. Under development User's Manual U16889EJ1V0UD 863 APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Software) SM850 System simulator This is a system simulator for the V850 Series. The SM850 is Windows-based software. It is used to perform debugging at the C source level or assembler level while simulating the operation of the target system on a host machine. Use of the SM850 allows the execution of application logical testing and performance testing on an independent basis from hardware development, thereby providing higher development efficiency and software quality. The SM850 should be used in combination with the device file (sold separately). Part number: SxxxxSM703000 ID850 Integrated debugger (supporting in-circuit emulators IE-V850ES-G1 and IE-V850ESK1-ET) ID850 QB (provisional name) Integrated debugger (supporting in-circuit emulator QB-V850ESKX1H) This debugger supports the in-circuit emulators for the V850 Series. The ID850 and ID850 QB (provisional name) are Windows-based software. It has improved C-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory display with the trace result. It should be used in combination with the device file (sold separately). Part number: SxxxxID703000, SxxxxID703000-GC Remark xxxx in the part number differs depending on the host machine and OS used. SxxxxSM703000 SxxxxID703000 SxxxxID703000-GC xxxx AB17 BB17 Host Machine PC-9800 series, IBM PC/AT compatibles OS Windows (Japanese version) Windows (English version) Supply Medium CD-ROM 864 User's Manual U16889EJ1V0UD APPENDIX A DEVELOPMENT TOOLS A.6 Embedded Software RX850, RX850 Pro Real-time OS The RX850 and RX850 Pro are real-time OSs conforming to ITRON 3.0 specifications. A tool (configurator) for generating multiple information tables is supplied. RX850 Pro has more functions than RX850. Part number: SxxxxRX703000- (RX850) SxxxxRX703100- (RX850 Pro) V850mini-NET (provisional name) (Network library) This is a network library conforming to RFC. It is a lightweight TCP/IP of compact design, requiring only a small memory. In addition to the TCP/IP standard set, an HTTP server, SMTP client, and POP client are also supported. RX-FS850 (File system) This is a FAT file system function. It is a file system that supports the CD-ROM file system function. This file system is used with the real-time OS RX850 Pro. Caution To purchase the RX850 or RX850 Pro, first fill in the purchase application form and sign the user agreement. Remark xxxx and in the part number differ depending on the host machine and OS used. SxxxxRX703000- SxxxxRX703100- 001 100K 001M 010M S01 Source program Product Outline Evaluation object Mass-production object Maximum Number for Use in Mass Production Do not use for mass-produced product. 0.1 million units 1 million units 10 million units Object source program for mass production xxxx AB17 BB17 3K17 Host Machine PC-9800 series, IBM PC/AT compatibles SPARCstation OS Windows (Japanese version) Windows (English version) Solaris (Rel. 2.5.1) Supply Medium CD-ROM A.7 Flash Memory Writing Tools Flashpro IV (part number: PG-FP4) Flash programmer FA-144GJ-UEN Flash memory writing adapter Flash memory writing adapter used connected to the Flashpro IV. * FA-144GJ-UEN: For 144-pin plastic LQFP (GJ-UEN type) Flash programmer dedicated to microcontrollers with on-chip flash memory. Remark FA-144GJ-UEN is a product of Naito Densei Machida Mfg. Co., Ltd. TEL: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd. User's Manual U16889EJ1V0UD 865 APPENDIX B INSTRUCTION SET LIST B.1 Conventions (1) Register symbols used to describe operands Register Symbol reg1 reg2 Explanation General-purpose registers: Used as source registers. General-purpose registers: Used mainly as destination registers. Also used as source register in some instructions. reg3 General-purpose registers: Used mainly to store the remainders of division results and the higher 32 bits of multiplication results. bit#3 immX dispX regID vector cccc sp ep listX 3-bit data for specifying the bit number X bit immediate data X bit displacement data System register number 5-bit data that specifies the trap vector (00H to 1FH) 4-bit data that shows the condition codes Stack pointer (r3) Element pointer (r30) X item register list (2) Register symbols used to describe opcodes Register Symbol R r w d I i cccc CCCC bbb L 1-bit data of a code that specifies reg1 or regID 1-bit data of the code that specifies reg2 1-bit data of the code that specifies reg3 1-bit displacement data 1-bit immediate data (indicates the higher bits of immediate data) 1-bit immediate data 4-bit data that shows the condition codes 4-bit data that shows the condition codes of Bcond instruction 3-bit data for specifying the bit number 1-bit data that specifies a program register in the register list Explanation 866 User's Manual U16889EJ1V0UD APPENDIX B INSTRUCTION SET LIST (3) Register symbols used in operations Register Symbol GR [ ] SR [ ] zero-extend (n) sign-extend (n) load-memory (a, b) store-memory (a, b, c) load-memory-bit (a, b) store-memory-bit (a, b, c) saturated (n) Input for General-purpose register System register Expand n with zeros until word length. Expand n with signs until word length. Read size b data from address a. Write data b into address a in size c. Read bit b of address a. Write c to bit b of address a. Execute saturated processing of n (n is a 2's complement). If, as a result of calculations, n 7FFFFFFFH, let it be 7FFFFFFFH. n 80000000H, let it be 80000000H. result Byte Halfword Word + - ll x / % AND OR XOR NOT logically shift left by logically shift right by arithmetically shift right by Reflects the results in a flag. Byte (8 bits) Halfword (16 bits) Word (32 bits) Addition Subtraction Bit concatenation Multiplication Division Remainder from division results Logical product Logical sum Exclusive OR Logical negation Logical shift left Logical shift right Arithmetic shift right Explanation (4) Register symbols used in execution clock Register Symbol i r l Explanation If executing another instruction immediately after executing the first instruction (issue). If repeating execution of the same instruction immediately after executing the first instruction (repeat). If using the results of instruction execution in the instruction immediately after the execution (latency). User's Manual U16889EJ1V0UD 867 APPENDIX B INSTRUCTION SET LIST (5) Register symbols used in flag operations Identifier (Blank) 0 X R No change Clear to 0 Set or cleared in accordance with the results. Previously saved values are restored. Explanation (6) Condition codes Condition Name (cond) V NV C/L Condition Code (cccc) 0000 1000 0001 OV = 1 OV = 0 CY = 1 Overflow No overflow Carry Lower (Less than) NC/NL 1001 CY = 0 No carry Not lower (Greater than or equal) Z NZ NH H S/N NS/P T SA LT GE LE GT 0010 1010 0011 1011 0100 1100 0101 1101 0110 1110 0111 1111 SAT = 1 (S xor OV) = 1 (S xor OV) = 0 ((S xor OV) or Z) = 1 ((S xor OV) or Z) = 0 Z=1 Z=0 (CY or Z) = 1 (CY or Z) = 0 S=1 S=0 - Zero Not zero Not higher (Less than or equal) Higher (Greater than) Negative Positive Always (Unconditional) Saturated Less than signed Greater than or equal signed Less than or equal signed Greater than signed Condition Formula Explanation 868 User's Manual U16889EJ1V0UD APPENDIX B INSTRUCTION SET LIST B.2 Instruction Set (in Alphabetical Order) (1/6) Mnemonic Operand Opcode Operation Execution Clock i ADD reg1,reg2 imm5,reg2 ADDI imm16,reg1,reg2 r r rr r0 01 11 0 RRRRR rrrrr010010iiiii r r rr r1 10 00 0 RRRRR iiiiiiiiiiiiiiii AND ANDI reg1,reg2 imm16,reg1,reg2 r r rr r0 01 01 0 RRRRR r r rr r1 10 11 0 RRRRR iiiiiiiiiiiiiiii Bcond disp9 ddddd1011dddcccc if conditions are satisfied Note 1 then PCPC+sign-extend(disp9) When conditions are satisfied When conditions are not satisfied BSH reg2,reg3 rrrrr11111100000 GR[reg3]GR[reg2] (23 : 16) ll GR[reg2] (31 : 24) ll 1 1 1 x 0 x x 2 2 2 GR[reg2]GR[reg2]AND GR[reg1] GR[reg2]GR[reg1]AND zero-extend(imm16) 1 1 1 1 1 1 0 0 x x x x GR[reg2]GR[reg2]+GR[reg1] GR[reg2]GR[reg2]+sign-extend(imm5) GR[reg2]GR[reg1]+sign-extend(imm16) 1 1 1 r 1 1 1 l 1 1 1 CY OV S x x x x x x x x x Z SAT x x x Flags Note 2 Note 2 Note 2 1 1 1 wwwww01101000010 GR[reg2] (7 : 0) ll GR[reg2] (15 : 8) BSW reg2,reg3 rrrrr11111100000 GR[reg3]GR[reg2] (7 : 0) ll GR[reg2] (15 : 8) ll GR 1 1 1 x 0 x x wwwww01101000000 [reg2] (23 : 16) ll GR[reg2] (31 : 24) CALLT imm6 0000001000iiiiii CTPCPC+2(return PC) CTPSWPSW adrCTBP+zero-extend(imm6 logically shift left by 1) PCCTBP+zero-extend(Load-memory(adr,Halfword)) CLR1 bit#3,disp16[reg1] 10bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd Z flagNot(Load-memory-bit(adr,bit#3)) Store-memory-bit(adr,bit#3,0) reg2,[reg1] r r rr r1 11 11 1 RRRRR 0000000011100100 adrGR[reg1] Z flagNot(Load-memory-bit(adr,reg2)) Store-memory-bit(adr,reg2,0) CMOV cccc,imm5,reg2,reg3 r r r r r 1 1 1 1 1 1 i i i i i wwwww011000cccc0 if conditions are satisfied then GR[reg3]sign-extended(imm5) else GR[reg3]GR[reg2] cccc,reg1,reg2,reg3 r r rr r1 11 11 1 RRRR if conditions are satisfied else GR[reg3]GR[reg2] CMP reg1,reg2 imm5,reg2 CTRET r r rr r0 01 11 1 RRRRR rrrrr010011iiiii 0000011111100000 0000000101000100 DBRET 0000011111100000 0000000101000110 resultGR[reg2]-GR[reg1] resultGR[reg2]-sign-extend(imm5) PCCTPC PSWCTPSW PCDBPC PSWDBPSW 3 3 3 R R R R R 1 1 3 1 1 3 1 1 3 x x R x x R x x R x x R R 1 1 1 1 1 1 3 3 3 x 3 3 3 x 4 4 4 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 wwwww011001cccc0 then GR[reg3]GR[reg1] User's Manual U16889EJ1V0UD 869 APPENDIX B INSTRUCTION SET LIST (2/6) Mnemonic Operand Opcode Operation Execution Clock i DBTRAP 1111100001000000 DBPCPC+2 (restored PC) DBPSWPSW PSW.NP1 PSW.EP1 PSW.ID1 PC00000060H DI 0000011111100000 0000000101100000 DISPOSE imm5,list12 0000011001iiiiiL LLLLLLLLLLL00000 spsp+zero-extend(imm5 logically shift left by 2) GR[reg in list12]Load-memory(sp,Word) spsp+4 repeat 2 steps above until all regs in list12 is loaded imm5,list12,[reg1] 0000011001iiiiiL spsp+zero-extend(imm5 logically shift left by 2) n+3 n+3 n+3 Note 4 Note 4 Note 4 Flags r 3 l 3 CY OV S Z SAT 3 PSW.ID1 1 1 1 n+1 n+1 n+1 Note 4 Note 4 Note 4 LLLLLLLLLLLRRRRR GR[reg in list12]Load-memory(sp,Word) Note 5 spsp+4 repeat 2 steps above until all regs in list12 is loaded PCGR[reg1] DIV reg1,reg2,reg3 r r rr r1 11 11 1 RRRRR GR[reg2]GR[reg2]/GR[reg1] 35 35 35 x x x wwwww01011000000 GR[reg3]GR[reg2]%GR[reg1] DIVH reg1,reg2 reg1,reg2,reg3 r r rr r0 00 01 0 RRRRR r r rr r1 11 11 1 RRRRR GR[reg2]GR[reg2]/GR[reg1]Note 6 GR[reg2]GR[reg2]/GR[reg1] Note 6 35 35 35 35 35 35 x x x x x x wwwww01010000000 GR[reg3]GR[reg2]%GR[reg1] DIVHU reg1,reg2,reg3 r r rr r1 11 11 1 RRRRR GR[reg2]GR[reg2]/GR[reg1]Note 6 34 34 34 x x x wwwww01010000010 GR[reg3]GR[reg2]%GR[reg1] DIVU reg1,reg2,reg3 r r rr r1 11 11 1 RRRRR GR[reg2]GR[reg2]/GR[reg1] 34 34 34 x x x wwwww01011000010 GR[reg3]GR[reg2]%GR[reg1] EI 1000011111100000 0000000101100000 HALT 0000011111100000 0000000100100000 HSW reg2,reg3 rrrrr11111100000 wwwww01101000100 JARL disp22,reg2 rrrrr11110dddddd ddddddddddddddd0 Note 7 JMP JR [reg1] disp22 00000000011RRRRR PCGR[reg1] 0000011110dddddd ddddddddddddddd0 Note 7 LD.B disp16[reg1],reg2 r r rr r1 11 00 0 RRRRR dddddddddddddddd LD.BU disp16[reg1],reg2 r r rr r1 11 10 b RRRRR dddddddddddddd1 Notes 8, 10 adrGR[reg1]+sign-extend(disp16) GR[reg2]sign-extend(Load-memory(adr,Byte)) adrGR[reg1]+sign-extend(disp16) GR[reg2]zero-extend(Load-memory(adr,Byte)) 1 1 1 1 Note 11 Note 11 PSW.ID0 1 1 1 Stop 1 1 1 GR[reg3]GR[reg2](15 : 0) ll GR[reg2] (31 : 16) 1 1 1 x 0 x x GR[reg2]PC+4 PCPC+sign-extend(disp22) 2 2 2 3 2 3 2 3 2 PCPC+sign-extend(disp22) 870 User's Manual U16889EJ1V0UD APPENDIX B INSTRUCTION SET LIST (3/6) Mnemonic Operand Opcode Operation Execution Clock i LD.H disp16[reg1],reg2 rrrrr111001RRRRR ddddddddddddddd0 Note 8 LDSR reg2,regID rrrrr111111RRRRR 0000000000100000 Note 12 LD.HU disp16[reg1],reg2 r r rr r1 11 11 1 RRRRR ddddddddddddddd1 Note 8 LD.W disp16[reg1],reg2 r r rr r1 11 00 1 RRRRR ddddddddddddddd1 Note 8 MOV reg1,reg2 imm5,reg2 imm32,reg1 r r rr r0 00 00 0 RRRRR rrrrr010000iiiii GR[reg2]GR[reg1] GR[reg2]sign-extend(imm5) 1 1 2 1 1 2 1 1 2 adrGR[reg1]+sign-exend(disp16) GR[reg2]Load-memory(adr,Word) 1 1 Note 11 Flags r 1 l Note 11 CY OV S Z SAT adrGR[reg1]+sign-extend(disp16) GR[reg2]sign-extend(Load-memory(adr,Halfword)) 1 SR[regID]GR[reg2] Other than regID = PSW regID = PSW 1 1 1 1 1 1 x x x x x adrGR[reg1]+sign-exend(disp16) GR[reg2]zero-extend(Load-memory(adr,Halfword) 1 1 Note 11 00000110001RRRRR GR[reg1]imm32 iiiiiiiiiiiiiiii IIIIIIIIIIIIIIII MOVEA imm16,reg1,reg2 r r rr r1 10 00 1 RRRRR iiiiiiiiiiiiiiii GR[reg2]GR[reg1]+sign-extend(imm16) 1 1 1 MOVHI imm16,reg1,reg2 r r rr r1 10 01 0 RRRRR iiiiiiiiiiiiiiii GR[reg2]GR[reg1]+(imm16 ll 016) 1 1 1 MUL reg1,reg2,reg3 r r rr r1 11 11 1 RRRRR GR[reg3] ll GR[reg2]GR[reg2]xGR[reg1] 1 4 5 wwwww01000100000 Note 14 imm9,reg2,reg3 rrrrr111111iiiii wwwww01001IIII 00 Note 13 MULH reg1,reg2 imm5,reg2 MULHI imm16,reg1,reg2 r r rr r0 00 11 1 RRRRR rrrrr010111iiiii r r rr r1 10 11 1 RRRRR iiiiiiiiiiiiiiii MULU reg1,reg2,reg3 r r rr r1 11 11 1 RRRRR GR[reg3] ll GR[reg2]GR[reg2]xGR[reg1] 1 4 5 GR[reg2]GR[reg2]Note 6xGR[reg1]Note 6 GR[reg2]GR[reg2] GR[reg2]GR[reg1] Note 6 GR[reg3] ll GR[reg2]GR[reg2]xsign-extend(imm9) 1 4 5 1 1 1 1 1 1 2 2 2 xsign-extend(imm5) ximm16 Note 6 wwwww01000100010 Note 14 imm9,reg2,reg3 rrrrr111111iiiii wwwww01001IIII 10 Note 13 NOP NOT NOT1 reg1,reg2 bit#3,disp16[reg1] 0000000000000000 Pass at least one clock cycle doing nothing. r r rr r0 00 00 1 RRRRR GR[reg2]NOT(GR[reg1]) 1 1 3 1 1 3 1 1 3 0 x x x GR[reg3] ll GR[reg2]GR[reg2]xzero-extend(imm9) 1 4 5 01bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd Z flagNot(Load-memory-bit(adr,bit#3)) Store-memory-bit(adr,bit#3,Z flag) Note 3 Note 3 Note 3 reg2,[reg1] r r rr r1 11 11 1 RRRRR 0000000011100010 adrGR[reg1] Z flagNot(Load-memory-bit(adr,reg2)) Store-memory-bit(adr,reg2,Z flag) 3 3 3 x Note 3 Note 3 Note 3 User's Manual U16889EJ1V0UD 871 APPENDIX B INSTRUCTION SET LIST (4/6) Mnemonic Operand Opcode Operation Execution Clock i OR ORI reg1,reg2 imm16,reg1,reg2 r r rr r0 01 00 0 RRRRR r r rr r1 10 10 0 RRRRR iiiiiiiiiiiiiiii PREPARE list12,imm5 0000011110iiiiiL Store-memory(sp-4,GR[reg in list12],Word) repeat 1 step above until all regs in list12 is stored spsp-zero-extend(imm5) list12,imm5, sp/immNote 15 0000011110iiiiiL LLLLLLLLLLLff011 imm16/imm32 Store-memory(sp-4,GR[reg in list12],Word) spsp+4 repeat 1 step above until all regs in list12 is stored Note 16 spsp-zero-extend (imm5) epsp/imm RETI 0000011111100000 if PSW.EP=1 0000000101000000 then PC EIPC PSW EIPSW else if PSW.NP=1 then else PC PC FEPC EIPC PSW FEPSW PSW EIPSW SAR reg1,reg2 r r rr r1 11 11 1 RRRRR 0000000010100000 imm5,reg2 rrrrr010101iiiii GR[reg2]GR[reg2]arithmetically shift right by GR[reg1] GR[reg2]GR[reg2]arithmetically shift right by zero-extend (imm5) SASF cccc,reg2 rrrrr1111110cccc 0000001000000000 if conditions are satisfied then GR[reg2](GR[reg2]Logically shift left by 1) OR 00000001H else GR[reg2](GR[reg2]Logically shift left by 1) OR 00000000H SATADD reg1,reg2 imm5,reg2 SATSUB SATSUBI reg1,reg2 imm16,reg1,reg2 r r rr r0 00 11 0 RRRRR rrrrr010001iiiii r r rr r0 00 10 1 RRRRR r r rr r1 10 01 1 RRRRR iiiiiiiiiiiiiiii SATSUBR reg1,reg2 SETF cccc,reg2 r r rr r0 00 10 0 RRRRR rrrrr1111110cccc 0000000000000000 GR[reg2]saturated(GR[reg1]-GR[reg2]) If conditions are satisfied then GR[reg2]00000001H else GR[reg2]00000000H 1 1 1 1 1 1 x x x x x GR[reg2]saturated(GR[reg2]+GR[reg1]) GR[reg2]saturated(GR[reg2]+sign-extend(imm5)) GR[reg2]saturated(GR[reg2]-GR[reg1]) GR[reg2]saturated(GR[reg1]-sign-extend(imm16)) 1 1 1 1 1 1 1 1 1 1 1 1 x x x x x x x x x x x x x x x x x x x x 1 1 1 1 1 1 x 0 x x 1 1 1 x 0 x x Note17 Note17 Note17 Flags r 1 1 l 1 1 CY OV S 0 0 x x Z SAT x x GR[reg2]GR[reg2]OR GR[reg1] GR[reg2]GR[reg1]OR zero-extend(imm16) 1 1 n+1 n+1 n+1 Note 4 Note 4 Note 4 LLLLLLLLLLL00001 spsp-4 n+2 n+2 n+2 Note 4 Note 4 Note 4 3 3 3 R R R R R 872 User's Manual U16889EJ1V0UD APPENDIX B INSTRUCTION SET LIST (5/6) Mnemonic Operand Opcode Operation Execution Clock i SET1 bit#3,disp16[reg1] 00bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd Z flagNot (Load-memory-bit(adr,bit#3)) Store-memory-bit(adr,bit#3,1) reg2,[reg1] r r rr r1 11 11 1 RRRRR 0000000011100000 adrGR[reg1] Z flagNot(Load-memory-bit(adr,reg2)) Store-memory-bit(adr,reg2,1) SHL reg1,reg2 r r rr r1 11 11 1 RRRRR 0000000011000000 imm5,reg2 rrrrr010110iiiii GR[reg2]GR[reg2] logically shift left by zero-extend(imm5) SHR reg1,reg2 r r rr r1 11 11 1 RRRRR 0000000010000000 imm5,reg2 rrrrr010100iiiii GR[reg2]GR[reg2] logically shift right by zero-extend(imm5) SLD.B disp7[ep],reg2 rrrrr0110ddddddd adrep+zero-extend(disp7) GR[reg2]sign-extend(Load-memory(adr,Byte)) SLD.BU disp4[ep],reg2 r r r r r 0 0 0 0 1 1 0 d d d d adrep+zero-extend(disp4) Note 18 GR[reg2]zero-extend(Load-memory(adr,Byte)) SLD.H disp8[ep],reg2 r r r r r 1 0 0 0 d d d d d d d adrep+zero-extend(disp8) Note 19 GR[reg2]sign-extend(Load-memory(adr,Halfword)) SLD.HU disp5[ep],reg2 r r r r r 0 0 0 0 1 1 1 d d d d adrep+zero-extend(disp5) Notes 18, 20 GR[reg2]zero-extend(Load-memory(adr,Halfword)) SLD.W disp8[ep],reg2 r r r r r 1 0 1 0 d d d d d d 0 adrep+zero-extend(disp8) Note 21 GR[reg2]Load-memory(adr,Word) SST.B reg2,disp7[ep] rrrrr0111ddddddd adrep+zero-extend(disp7) Store-memory(adr,GR[reg2],Byte) SST.H reg2,disp8[ep] r r r r r 1 0 0 1 d d d d d d d adrep+zero-extend(disp8) Note 19 Store-memory(adr,GR[reg2],Halfword) SST.W reg2,disp8[ep] r r r r r 1 0 1 0 d d d d d d 1 adrep+zero-extend(disp8) Note 21 Store-memory(adr,GR[reg2],Word) ST.B reg2,disp16[reg1] r r rr r1 11 01 0 RRRRR dddddddddddddddd ST.H reg2,disp16[reg1] adrGR[reg1]+sign-extend(disp16) Store-memory(adr,GR[reg2],Byte) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 9 Flags r 3 l 3 CY OV S Z SAT x 3 Note 3 Note 3 Note 3 3 3 3 x Note 3 Note 3 Note 3 GR[reg2]GR[reg2] logically shift left by GR[reg1] 1 1 1 x 0 x x 1 1 1 x x 0 x x x x GR[reg2]GR[reg2] logically shift right by GR[reg1] 1 1 1 0 1 1 1 x 0 x x 1 1 Note 9 1 1 Note 9 1 1 Note 9 1 1 Note 9 r r rr r1 11 01 1 RRRRR adrGR[reg1]+sign-extend(disp16) ddddddddddddddd0 Store-memory (adr,GR[reg2], Halfword) Note 8 ST.W reg2,disp16[reg1] rrrrr111011RRRRR adrGR[reg1]+sign-extend(disp16) ddddddddddddddd1 Store-memory (adr,GR[reg2], Word) Note 8 1 1 1 STSR regID,reg2 r r rr r1 11 11 1 RRRRR 0000000001000000 GR[reg2]SR[regID] 1 1 1 User's Manual U16889EJ1V0UD 873 APPENDIX B INSTRUCTION SET LIST (6/6) Mnemonic Operand Opcode Operation Execution Clock i SUB SUBR SWITCH reg1,reg2 reg1,reg2 reg1 r r rr r0 01 10 1 RRRRR r r rr r0 01 10 0 RRRRR GR[reg2]GR[reg2]-GR[reg1] GR[reg2]GR[reg1]-GR[reg2] 1 1 5 r 1 1 5 l 1 1 5 CY OV S x x x x x x Z SAT x x Flags 00000000010RRRRR adr(PC+2) + (GR [reg1] logically shift left by 1) PC(PC+2) + (sign-extend (Load-memory (adr,Halfword)) logically shift left by 1 SXB reg1 00000000101RRRRR GR[reg1]sign-extend (GR[reg1] (7 : 0)) 1 1 1 SXH reg1 00000000111RRRRR GR[reg1]sign-extend (GR[reg1] (15 : 0)) 1 1 1 TRAP vector 00000111111iiiii 0000000100000000 EIPC EIPSW PSW.EP PSW.ID PC PC+4 (Restored PC) PSW 1 1 00000040H (when vector is 00H to 0FH) 00000050H (when vector is 10H to 1FH) 3 3 3 ECR.EICC Interrupt code TST TST1 reg1,reg2 bit#3,disp16[reg1] r r rr r0 01 01 1 RRRRR resultGR[reg2] AND GR[reg1] 1 3 1 3 1 3 0 x x x 11bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd Z flagNot (Load-memory-bit (adr,bit#3)) adrGR[reg1] Z flagNot (Load-memory-bit (adr,reg2)) GR[reg2]GR[reg2] XOR GR[reg1] GR[reg2]GR[reg1] XOR zero-extend (imm16) Note 3 Note 3 Note 3 reg2, [reg1] r r rr r1 11 11 1 RRRRR 0000000011100110 3 3 3 x Note 3 Note 3 Note 3 XOR XORI reg1,reg2 imm16,reg1,reg2 r r rr r0 01 00 1 RRRRR r r rr r1 10 10 1 RRRRR iiiiiiiiiiiiiiii 1 1 1 1 1 1 0 0 x x x x ZXB ZXH reg1 reg1 00000000100RRRRR GR[reg1]zero-extend (GR[reg1] (7 : 0)) 00000000110RRRRR GR[reg1]zero-extend (GR[reg1] (15 : 0)) 1 1 1 1 1 1 Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. dddddddd: Higher 8 bits of disp9. 3 if there is an instruction that rewrites the contents of the PSW immediately before. If there is no wait state (3 + the number of read access wait states). n is the total number of list12 load registers. (According to the number of wait states. Also, if there are no wait states, n is the total number of list12 registers. If n = 0, same operation as when n = 1) RRRRR: other than 00000. The lower halfword data only are valid. ddddddddddddddddddddd: The higher 21 bits of disp22. ddddddddddddddd: The higher 15 bits of disp16. According to the number of wait states (1 if there are no wait states). 10. b: bit 0 of disp16. 11. According to the number of wait states (2 if there are no wait states). 874 User's Manual U16889EJ1V0UD APPENDIX B INSTRUCTION SET LIST Notes 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the reg1 field is used in the opcode. Therefore, the meaning of register specification in the mnemonic description and in the opcode differs from other instructions. rrrrr = regID specification RRRRR = reg2 specification 13. i i i i i : Lower 5 bits of imm9. I I I I : Higher 4 bits of imm9. 14. Do not specify the same register for general-purpose registers reg1 and reg3. 15. sp/imm: specified by bits 19 and 20 of the sub-opcode. 16. ff = 00: Load sp in ep. 01: Load sign expanded 16-bit immediate data (bits 47 to 32) in ep. 10: Load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep. 11: Load 32-bit immediate data (bits 63 to 32) in ep. 17. If imm = imm32, n + 3 clocks. 18. r r r r r : Other than 00000. 19. ddddddd: Higher 7 bits of disp8. 20. dddd: Higher 4 bits of disp5. 21. dddddd: Higher 6 bits of disp8. User's Manual U16889EJ1V0UD 875 APPENDIX C REGISTER INDEX (1/8) Symbol ADCR ADIC ADM ADS ADTC0 ADTC1 ADTI0 ADTI1 ADTP0 ADTP1 ASIF0 ASIF1 ASIF2 ASIM0 ASIM1 ASIM2 ASIS0 ASIS1 ASIS2 AWC BCC BRGC0 BRGC1 BRGC2 BRGCA0 BRGCA1 BRGIC BSC CKSR0 CKSR1 CKSR2 CMP00 CMP01 CMP10 CMP11 CORAD0 CORAD1 CORAD2 CORAD3 CORCN A/D conversion result register Interrupt control register A/D converter mode register Analog input channel specification register Automatic data transfer address count register 0 Automatic data transfer address count register 1 Automatic data transfer interval specification register 0 Automatic data transfer interval specification register 1 Automatic data transfer address point specification register 0 Automatic data transfer address point specification register 1 Asynchronous serial interface transmit status register 0 Asynchronous serial interface transmit status register 1 Asynchronous serial interface transmit status register 2 Asynchronous serial interface mode register 0 Asynchronous serial interface mode register 1 Asynchronous serial interface mode register 2 Asynchronous serial interface status register 0 Asynchronous serial interface status register 1 Asynchronous serial interface status register 2 Address wait control register Bus cycle control register Baud rate generator control register 0 Baud rate generator control register 1 Baud rate generator control register 2 Divisor selection register 0 Divisor selection register 1 Interrupt control register Bus size configuration register Clock select register 0 Clock select register 1 Clock select register 2 8-bit timer H compare register 00 8-bit timer H compare register 01 8-bit timer H compare register 10 8-bit timer H compare register 11 Correction address register 0 Correction address register 1 Correction address register 2 Correction address register 3 Correction control register Name Unit ADC INTC ADC ADC CSI CSI CSI CSI CSI CSI UART UART UART UART UART UART UART UART UART BCU BCU UART UART UART CSI CSI INIC BCU UART UART UART Timer Timer Timer Timer ROMC ROMC ROMC ROMC ROMC Page 439 634 436 438 520 520 526 526 524 524 466 466 466 463 463 463 465 465 465 196 197 484 484 484 524 524 634 185 483 483 483 382 382 382 382 681 681 681 681 682 876 User's Manual U16889EJ1V0UD APPENDIX C REGISTER INDEX (2/8) Symbol CR000 CR001 CR010 CR011 CR020 CR021 CR030 CR031 CR040 CR041 CR050 CR051 CR5 CR50 CR51 CRC00 CRC01 CRC02 CRC03 CRC04 CRC05 CSI0IC0 CSI0IC1 CSI0IC2 CSIA0Bn CSIA1Bn CSIAIC0 CSIAIC1 CSIC0 CSIC1 CSIC2 CSIM00 CSIM01 CSIM02 CSIMA0 CSIMA1 CSIS0 CSIS1 CSIT0 CSIT1 DACS0 DACS1 DAM DWC0 Name 16-bit timer capture/compare register 000 16-bit timer capture/compare register 001 16-bit timer capture/compare register 010 16-bit timer capture/compare register 011 16-bit timer capture/compare register 020 16-bit timer capture/compare register 021 16-bit timer capture/compare register 030 16-bit timer capture/compare register 031 16-bit timer capture/compare register 040 16-bit timer capture/compare register 041 16-bit timer capture/compare register 050 16-bit timer capture/compare register 051 16-bit timer compare register 5 8-bit timer compare register 50 8-bit timer compare register 51 Capture/compare control register 00 Capture/compare control register 01 Capture/compare control register 02 Capture/compare control register 03 Capture/compare control register 04 Capture/compare control register 05 Interrupt control register Interrupt control register Interrupt control register CSIA0 buffer RAMn (n = 0 to F) CSIA1 buffer RAMn (n = 0 to F) Interrupt control register Interrupt control register Clocked serial interface clock selection register 0 Clocked serial interface clock selection register 1 Clocked serial interface clock selection register 2 Clocked serial interface mode register 00 Clocked serial interface mode register 01 Clocked serial interface mode register 02 Serial operation mode specification register 0 Serial operation mode specification register 1 Serial status register 0 Serial status register 1 Serial trigger register 0 Serial trigger register 1 D/A conversion value setting register 0 D/A conversion value setting register 1 D/A converter mode register Data wait control register 0 Unit Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer INTC INTC INTC CSI CSI INTC INTC CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI DAC DAC DAC BCU Page 308 310 308 310 308 310 308 310 308 310 308 310 363, 375, 378 363 363 315 315 315 315 315 315 634 634 634 526 526 634 634 496 496 496 494 494 494 521 521 522 522 523 523 456 456 456 193 User's Manual U16889EJ1V0UD 877 APPENDIX C REGISTER INDEX (3/8) Symbol EXIMC IIC0 IIC1 IICC0 IICC1 IICCL0 IICCL1 IICF0 IICF1 IICIC0 IICIC1 IICS0 IICS1 IICX0 IICX1 IMR0 IMR1 IMR2 IMR3 IMR3L INTF0 INTF9H INTR0 INTR9H ISPR KRIC KRM OCDM OSTS P0 P0NFC P1 P1NFC P3 P4 P5 P6 P7 P8 P9 PCC PCD PCM Name External bus interface mode control register IIC shift register 0 IIC shift register 1 IIC control register 0 IIC control register 1 IIC clock selection register 0 IIC clock selection register 1 IIC flag register 0 IIC flag register 1 Interrupt control register Interrupt control register IIC status register 0 IIC status register 1 IIC function expansion register 0 IIC function expansion register 1 Interrupt mask register 0 Interrupt mask register 1 Interrupt mask register 2 Interrupt mask register 3 Interrupt mask register 3L External interrupt falling edge specification register 0 External interrupt falling edge specification register 9H External interrupt rising edge specification register 0 External interrupt rising edge specification register 9H In-service priority register Interrupt control register Key return mode register On-chip debug mode register Oscillation stabilization time selection register Port 0 register TIP00 noise elimination control register Port 1 register TIP01 noise elimination control register Port 3 register Port 4 register Port 5 register Port 6 register Port 7 register Port 8 register Port 9 register Processor clock control register Port CD register Port CM register Unit BCU IC IC IC IC IC IC IC IC INTC INTC IC IC IC IC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC KR - Standby Port Timer Port Timer Port Port Port Port Port Port Port CG Port Port 2 2 2 2 2 2 2 2 2 2 2 2 Page 184 567 567 555 555 565 565 563 563 634 635 560 560 566 566 636 636 636 636 636 642 643 642 643 638 634 656 99 662 97 303 100 303 103 107 109 113 117 118 122 211 129 130 878 User's Manual U16889EJ1V0UD APPENDIX C REGISTER INDEX (4/8) Symbol PCS PCT PDH PDL PF3H PF4 PF5 PF6 PF8 PF9H PFC3 PFC5 PFC6H PFC8 PFC9 PFCE3 PFM PFT PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 PLLCTL PM0 PM1 PM3 PM4 PM5 PM6 PM8 PM9 PMC0 PMC3 PMC4 PMC5 PMC6 PMC8 PMC9 PMCCM PMCCS PMCCT Port CS register Port CT register Port DH register Port DL register Port 3 function register H Port 4 function register Port 5 function register Port 6 function register Port 8 function register Port 9 function register H Port 3 function control register Port 5 function control register Port 6 function control register H Port 8 function control register Port 9 function control register Port 3 function control expansion register Power fail comparison mode register Power fail comparison threshold register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register PLL control register Port 0 mode register Port 1 mode register Port 3 mode register Port 4 mode register Port 5 mode register Port 6 mode register Port 8 mode register Port 9 mode register Port 0 mode control register Port 3 mode control register Port 4 mode control register Port 5 mode control register Port 6 mode control register Port 8 mode control register Port 9 mode control register Port CM mode control register Port CS mode control register Port CT mode control register Name Unit Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port ADC ADC INTC INTC INTC INTC INTC INTC INTC CG Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Page 132 134 136 139 105 108 110 115 119 125 105 111 115 120 125 106 441 441 634 634 634 634 634 634 634 216, 431 97 100 103 107 109 113 118 122 98 104 108 110 114 119 122 131 133 135 User's Manual U16889EJ1V0UD 879 APPENDIX C REGISTER INDEX (5/8) Symbol PMCDH PMCDL PMCD PMCM PMCS PMCT PMDH PMDL PRCMD PRM00 PRM01 PRM02 PRM03 PRM04 PRM05 PRSCM PRSM PSC PSMR PU0 PU1 PU3 PU4 PU5 PU6 PU8 PU9 RTBH0 RTBH1 RTBL0 RTBL1 RTPC0 RTPC1 RTPM0 RTPM1 RXB0 RXB1 RXB2 SIO0 SIO1 SIO2 SIOA0 SIOA1 SIRB0 Port DH mode control register Port DL mode control register Port CD mode register Port CM mode register Port CS mode register Port CT mode register Port DH mode register Port DL mode register Command register Prescaler mode register 00 Prescaler mode register 01 Prescaler mode register 02 Prescaler mode register 03 Prescaler mode register 04 Prescaler mode register 05 Interval timer BRG compare register Interval timer BRG mode register Power save control register Power save mode register Pull-up resistor option register 0 Pull-up resistor option register 1 Pull-up resistor option register 3 Pull-up resistor option register 4 Pull-up resistor option register 5 Pull-up resistor option register 6 Pull-up resistor option register 8 Pull-up resistor option register 9 Real-time output buffer register H0 Real-time output buffer register H1 Real-time output buffer register L0 Real-time output buffer register L1 Real-time output port control register 0 Real-time output port control register 1 Real-time output port mode register 0 Real-time output port mode register 1 Receive buffer register 0 Receive buffer register 1 Receive buffer register 2 Serial I/O shift register 0 Serial I/O shift register 1 Serial I/O shift register 2 Serial I/O shift register A0 Serial I/O shift register A1 Clocked serial interface receive buffer register 0 Name Unit Port Port Port Port Port Port Port Port CPU Timer Timer Timer Timer Timer Timer Timer Timer Standby Standby Port Port Port Port Port Port Port Port RTP RTP RTP RTP RTP RTP RTP RTP UART UART UART CSI CSI CSI CSI CSI CSI Page 137 140 129 130 132 134 136 139 86 319 320 321 322 323 324 406 405 660 661 98 101 106 108 111 116 120 128 425 425 425 425 427 427 426 426 467 467 467 501 501 501 520 520 497 880 User's Manual U16889EJ1V0UD APPENDIX C REGISTER INDEX (6/8) Symbol SIRB0L SIRB1 SIRB1L SIRB2 SIRB2L SIRBE0 SIRBE0L SIRBE1 SIRBE1L SIRBE2 SIRBE2L SOTB0 SOTB0L SOTB1 SOTB1L SOTB2 SOTB2L SOTBF0 SOTBF0L SOTBF1 SOTBF1L SOTBF2 SOTBF2L SREIC0 SREIC1 SREIC2 SRIC0 SRIC1 SRIC2 STIC0 STIC1 STIC2 SVA0 SVA1 SYS TCL50 TCL51 TM00 TM01 TM02 TM03 TM04 TM05 TM0IC00 Name Clocked serial interface receive buffer register 0L Clocked serial interface receive buffer register 1 Clocked serial interface receive buffer register 1L Clocked serial interface receive buffer register 2 Clocked serial interface receive buffer register 2L Clocked serial interface read-only receive buffer register 0 Clocked serial interface read-only receive buffer register 0L Clocked serial interface read-only receive buffer register 1 Clocked serial interface read-only receive buffer register 1L Clocked serial interface read-only receive buffer register 2 Clocked serial interface read-only receive buffer register 2L Clocked serial interface transmit buffer register 0 Clocked serial interface transmit buffer register 0L Clocked serial interface transmit buffer register 1 Clocked serial interface transmit buffer register 1L Clocked serial interface transmit buffer register 2 Clocked serial interface transmit buffer register 2L Clocked serial interface initial transmit buffer register 0 Clocked serial interface initial transmit buffer register 0L Clocked serial interface initial transmit buffer register 1 Clocked serial interface initial transmit buffer register 1L Clocked serial interface initial transmit buffer register 2 Clocked serial interface initial transmit buffer register 2L Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Slave address register 0 Slave address register 1 System status register Timer clock selection register 50 Timer clock selection register 51 16-bit timer counter 00 16-bit timer counter 01 16-bit timer counter 02 16-bit timer counter 03 16-bit timer counter 04 16-bit timer counter 05 Interrupt control register Unit CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI CSI INTC INTC INTC INTC INTC INTC INTC INTC INTC IC IC CPU Timer Timer Timer Timer Timer Timer Timer Timer INTC 2 2 Page 497 497 497 497 497 498 498 498 498 498 498 499 499 499 499 499 499 500 500 500 500 500 500 634 634 635 634 634 635 634 634 635 567 567 86 364 364 308 308 308 308 308 308 634 User's Manual U16889EJ1V0UD 881 APPENDIX C REGISTER INDEX (7/8) Symbol TM0IC01 TM0IC10 TM0IC11 TM0IC20 TM0IC21 TM0IC30 TM0IC31 TM0IC40 TM0IC41 TM0IC50 TM0IC51 TM5 TM50 TM51 TM5IC0 TM5IC1 TMC00 TMC01 TMC02 TMC03 TMC04 TMC05 TMC50 TMC51 TMCYC0 TMCYC1 TMHIC0 TMHIC1 TMHMD0 TMHMD1 TOC00 TOC01 TOC02 TOC03 TOC04 TOC05 TP0CCIC0 TP0CCIC1 TP0CCR0 TP0CCR1 TP0CNT TP0CTL0 TP0CTL1 TP0IOC0 Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register 16-bit timer counter 5 8-bit timer counter 50 8-bit timer counter 51 Interrupt control register Interrupt control register 16-bit timer mode control register 00 16-bit timer mode control register 01 16-bit timer mode control register 02 16-bit timer mode control register 03 16-bit timer mode control register 04 16-bit timer mode control register 05 8-bit timer mode control register 50 8-bit timer mode control register 51 8-bit timer H carrier control register 0 8-bit timer H carrier control register 1 Interrupt control register Interrupt control register 8-bit timer H mode register 0 8-bit timer H mode register 1 16-bit timer output control register 00 16-bit timer output control register 01 16-bit timer output control register 02 16-bit timer output control register 03 16-bit timer output control register 04 16-bit timer output control register 05 Interrupt control register Interrupt control register TMP0 capture/compare register 0 TMP0 capture/compare register 1 TMP0 counter read buffer register TMP0 control register 0 TMP0 control register 1 TMP0 I/O control register 0 Name Unit INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC Timer Timer Timer INTC INTC Timer Timer Timer Timer Timer Timer Timer Timer Timer Timer INTC INTC Timer Timer Timer Timer Timer Timer Timer Timer INTC INTC Timer Timer Timer Timer Timer Timer Page 634 634 634 634 634 634 634 634 634 634 634 377 362 362 634 634 312 312 312 312 312 312 365 365 386 386 634 634 384 385 316 316 316 316 316 316 635 635 227 229 231 221 222 223 882 User's Manual U16889EJ1V0UD APPENDIX C REGISTER INDEX (8/8) Symbol TP0IOC1 TP0IOC2 TP0OPT0 TP0OVIC TXB0 TXB1 TXB2 VSWC WDCS WDT1IC WDTE WDTM1 WDTM2 WTIC WTIIC WTM TMP0 I/O control register 1 TMP0 I/O control register 2 TMP0 option register 0 Interrupt control register Transmit buffer register 0 Transmit buffer register 1 Transmit buffer register 2 System wait control register Watchdog timer clock selection register Interrupt control register Watchdog timer enable register Watchdog timer mode register 1 Watchdog timer mode register 2 Interrupt control register Interrupt control register Watch timer operation mode register Name Unit Timer Timer Timer INTC UART UART UART CPU WDT INTC WDT WDT WDT INTC INTC WT Page 224 225 226 635 468 468 468 88 416 634 422 417, 640 421 634 634 409 User's Manual U16889EJ1V0UD 883 APPENDIX D REVISION HISTORY D.1 Modifications from Document Number U15862EJ4V1UD00 Page Throughout * Addition of following products Description * Extraction of only descriptions concerning V850ES/KJ1 PD70F3217H, 70F3217HY, 70F3218H, 70F3218HY * Addition of pins supporting added products * Addition of internal ROM, RAM, and flash memory capacities of added products p.35 p.50 p.60 p.65 p.67 p.73 p.88 Modification of description in 1.7 Overview of Functions Modification of I/O circuit type 13-B to 13-AH in 2.4 Pin I/O Circuits Modification of description in 3.3 (2) Flash memory programming mode Addition of 3.4.4 (1) (a) Internal ROM (256 KB) Addition of 3.4.4 (2) (a) Internal RAM (16 KB) Modification of description in 3.4.6 Peripheral I/O registers Modification of description in 3.4.8 (1) System wait control register and (2) Access to special on-chip peripheral I/O register p.94 p.96 p.99 p.105 p.106 p.106 pp.141 to 169 p.171 p.218 p.526 p.661 p.684 p.721 Addition of 4.3 (5) Port n function control expansion register (PFCEn) Modification of description in Figure 4-1 Register Settings and Pin Functions Addition of 4.3.1 (5) Cautions Modification of description in 4.3.3 (5) Port 3 function control register (PFC3) Addition of 4.3.3 (6) Port 3 function control expansion register (PFCE3) Addition of 4.3.3 (8) Specifying alternate-function pins of port 3 Modification of Figures 4-3 to 4-31 (partial addition) Modification of description in Table 4-19 Settings When Port Pins Are Used for Alternate Functions Addition of CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Addition of Caution 1 in 18.3 (7) CSIAn buffer RAM (CSIAnBm) Modification of bit 7 in 22.2 (2) Power save mode register (PSMR) Addition of CHAPTER 26 FLASH MEMORY (SINGLE POWER) Addition of CHAPTER 28 ELECTRICAL SPECIFICATIONS (SINGLE-POWER FLASH MEMORY VERSION) (TARGET) pp.783 to 805 Modification of bus timing, basic operation, and timer timing in CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION AND TWO-POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS) pp.827, 828 Modification of basic operation and timer timing in CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS) (TARGET) pp.848, 849 Modification of basic operation and timer timing in CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) (TARGET) p.860 p.866 Addition of APPENDIX A DEVELOPMENT TOOLS Addition of APPENDIX B INSTRUCTION SET LIST 884 User's Manual U16889EJ1V0UD |
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